Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/
ircuit Optimization Simplest implementation ost criterion literal cost (L) gate input cost (G) gate input cost with NOTs (GN) Examples (all the same function): F = BD + AB + A D L = F = BD + AB + AB D + AB L = F = (A + B)(A + D)(B + + D )( B + + D) L = Which solution is best? 2
Half Adder Truth Table Expression S = X Y = X Y X Y S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Logic Implementation X Y S 3
4 Full Adder Expression S i = A i B i i or i+1 =A i B i + (A i B i ) i o = AB + (A B) i G i A i B i Alternatively G = generate (=AB) and P = propagate (=A B) P i i i+1 S i+1 = G i + P i i i or o = (G = Generate) OR (P =Propagate AND i = arry In)
Propagation Delay 5
Delay of a Full Adder Delay of the Sum and arry bit S 0 = A 0 B 0 0 2 delays 2+2=4 delays G i A i B i 1 =A 0 B 0 + (A 0 B 0 ) 0 @2 @3 2+2=4 delays P i i n? S n? i+1 S i 6
7 Ripple arry Adder B i A i ascade four 1-bit full adders i+1 FA i S i @0 @0 @8 @6 @4 @10 @10 @8 @6 @4
8 arry Lookahead Adder Separate circuit to calculate the carry
Revisit Number Representation Represent real numbers in hardware accuracy implementation complexity robustness to errors Fixed-point e.g. (11.0101) 2 2 s complement fractional binary number 9
Fractional Binary Numbers 16-bit DSP digital signal processor (DSP) 1.15 (15) format Two 15 number multiply = 30 (2.30 format) 10
Fixed Point Multiplication Two 15 number multiply 15 15 = 30 2.30 format, 32 bits, two sign bits MSB: extended sign bit need to truncate back to 1.15 format left shift by one bit, storing upper 16 bits right shift by 15 bits, storing lower 16 bits Dynamic range in a b-bit system 11
12 Outline Arithmetic Logic Sequential Logic Memory ircuit
Sequential Logic Next state function Next State = f(inputs, State) Output function Inputs ombinational Logic Next State Storage Elements Outputs urrent State LOK Synchronous machine 13
Finite State Machine (FSM) Mathematical model of computation consist of a finite number of states only one state at a time (urrent State) change state at a trigging event or condition Mealy machine Outputs = g(inputs, State) Moore machine Outputs = h(state) 14
SR Latch Basic NOR latch R (reset) S (set) S R 0 0 0 set 1 reset t pd No change not allowed unstable 15
Other SR Latches locked S lk R 1 2 NAND SR latch S (set) S S R (reset) R R 16
D Latch Truth table SR latch: S R + + 0 0 hold, 0 1 0 1 1 0 1 0 1 1 0 0 D D latch D (t+1) 0 0 1 1 D 17
18 Flip-Flop Latch timing issue transparent when = 1 state should change only once every new clock cycle Inputs Outputs ombinational X 0 X 1 Logic X 1 X 2 X 3 D Latch X 0 X 1 X 2 Next State (storage) State =0 1 Master-slave flip flop break feedthrough S R S R /Y Y S R
Flip-Flop Timing Issue S 1 catching Glitch R Y Master out Slave out Master active S R Slave active S R Y Y S R 1 catching wrong output should have been 0 19
Edge-Triggered D Flip-Flop (DFF) Why edge trigger? D replace S and R input D D Y S R D Y Master out Slave out Master active Slave active no 1 catching correct output 20
Sequential ircuit Analysis Design steps word description state diagram state table select flip-flop types input x D A input to FF and output verification Reverse engineering A states D B LK ' y output 21
Input Equations To flip-flops D A = A(t)x(t)+B(t)x(t) D B = A(t)x(t) input Output y x D A y(t) = x(t)(b(t) + A(t)) A states D B LK ' y output 22
2 3 rows (2 m+n ) rows 23 State Table For the example: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A (t)x(t) y(t) = x (t)(b(t) + A(t)) Inputs of the table Outputs of the table m: no. of FF n: no. of inputs Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t) 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0
State Diagram onventions Moore Machine in to next state Mealy Machine in/out State out State Example: x 1 x=1/y=0 x/y AB y 01 1 01 01 Moore type output depends only on state Mealy type output depends on state and input 24
25 Outline Arithmetic Logic Sequential Logic Memory ircuit
Static RAM Applications PU register file, cache, embedded memory, DSP haracteristics 6 transistor per cell, other topologies no need to refresh access time ~ cycle time no charge to leak faster, more area, more expensive 26
SRAM Operation Standby word line de-asserted Read precharge bit lines assert WL BL rise/drop slightly Write apply value to BL assert WL input drivers stronger 27
28 Summary Number Representation Boolean Logic and Gates ombinational Logic Arithmetic Logic Sequential Logic Memory ircuit
29 uestions? omments? Discussion?
Homework #2 Download problem sets from class website Due 09/12 (Monday) in class 2-day grace period 30