FET Inrush Protection Chris Pavlina https://semianalog.com 2015-11-23 CC0 1.0 Universal Abstract It is possible to use a simple one-transistor FET circuit to provie inrush protection for low voltage DC circuits. With the aition of only one more FET, reverse-polarity protection can also be provie. Suggeste applications inclue USB evices (as the USB specification is strict about inrush) an anything requiring significant bulk ecoupling. TL;DR: If you on t care how this circuit works, feel free to skip to section 6 (Design equations) an section 7 (Gotchas). Contents 1 What not to o 2 2 Better, but not quite 2 3 Debugging 3 4 The working circuit 4 5 Deriving the esign equations 4 6 Design equations 6 7 Gotchas 7 8 Worke example 8 1
1 What not to o There is a circuit that is occasionally seen[4], that as a single capacitor onto the familiar MOS reverse-polarity protection circuit: Figure 1: Don t o this! It shoul be fairly obvious why this won t work. The mechanism of the reverse-polarity circuit is that the boy ioe conucts until the loa is almost fully powere, an then the voltage at the loa provies enough V GS bias to the FET to turn it on completely. There is nothing we can o to control the behavior of the boy ioe, so clearly nothing can be built onto this circuit to slow the current. Flipping the FET aroun so the boy ioe is no longer in circuit (losing the reverse protection behavior) won t work either! The FET has very high voltage gain, so using an RC circuit to ramp its gate voltage won t o much. The output voltage will still spike up quickly, allowing a large inrush. This just elays startup. 2 Better, but not quite What is neee is something a bit more clever: = 100nF 1MΩ 1MΩ 100nF Figure 2: More clever, but still on t o it! Imagining the FET as a ifferential amplifier, we can see that the circuit is actually an integrator. When the input power is connecte, the waveform seen at the input is a step, an the integral of a step is a ramp perfect! If we can control the slope of that ramp, we can easily control the inrush into our circuit s capacitance. 2
3 Debugging Let s buil an test the circuit, with a 12 V source an a 1000 µf capacitor as a loa. The inrush current of this circuit, as will be seen later in the esign equations, shoul be on the orer of 120 ma. 12V 100nF 1MΩ 1000µF Figure 3: The circuit we re going to test. Figure 4: Test of faulty circuit. Channels: 1 = input, 2 = output, 3 = gate voltage, 4 = inrush current The inrush current spikes very high, saturating the oscilloscope at well over 1.4 A for about 1 ms, an sits at about 200 ma for about 14 ms until it tails off. The problem is that the FET only behaves as an integrator when it is in its linear region of operation. The 100 nf timing capacitor hols the gate to the rain as the input voltage is steppe, an the source quickly rises high enough for this to put it in saturation. Theoretically, any number of components can be ae between the input noe of an integrator an a fixe voltage without changing the behavior of the integrator. Taking avantage of this, we ll a a much larger capacitor between the FET s gate an source to swamp this effect. 3
4 The working circuit 1µF 100nF 12V 1MΩ 1000µF Figure 5: A secon capacitor is ae to prevent immeiate saturation. Figure 6: Test of goo circuit. Channels: 1 = input, 2 = output, 3 = gate voltage, 4 = inrush current This one works! The aitional capacitor elays startup by about 250 ms, at which point V GS reaches the threshol point an the FET begins to integrate the voltage step. The voltage rises at about 57 V/s, giving an inrush current of at most about 55 ma. 5 Deriving the esign equations The circuit is essentially just an integrator: 4
C START C TIME R TIME C R TIME CTIME C START C Figure 7: The full circuit an its equivalent integrator. Note that the equivalent integrator circuit sees the input step as the negative of the input voltage. This is because the noninverting input (the FET s source) sits at the positive rail, an the timing resistor runs to the negative rail. The behavior of an integrator is[1, p. 230]: V out (t) = 1 V in (t) t const R C For a steppe input voltage, we can rearrange this to get the slope of the output: t V out(t) = 1 R C V in(t) In the ieal integrator circuit above, the voltage across C START will be zero at all times, so it can be ignore. Therefore, the slope of the output voltage will be: t V out(t) = R TIME C TIME A capacitor behaves accoring to i = C v [1, p. 19], so we can fin the current into the t capacitor: I = C t V OUT = C R TIME C TIME The ramp time will be equal to the input voltage ivie by the slope: t RAMP = 5 t V OUT
We must compute the power issipation in the FET to select an appropriate one. The instantaneous power issipation is: The average over the pulse is: P = 1 p(t) = (v out v in ) i out t RAMP ((v out v in ) i out ) t i out is constant, an v out v in is a linear slope, making the area uner this curve triangular. The integral can be compute geometrically: A triangle = 1 (w h) 2 P = 1 t RAMP 1 2 ( t RAMP I OUT ) P = 1 2 ( I OUT ) Now, we must erive C START. At inrush, C START an C TIME behave as a capacitive voltage ivier, an these must keep V GS between zero an the threshol voltage at all times. C TIME V GS = C TIME C START ( ) VIN C START = C TIME 1 V GS(th) This equation escribes the critical case, so for error margin we want: ( ) VIN C START > C TIME 1 V GS(th) 6 Design equations C START C TIME R TIME C Figure 8: The full circuit with parts labele. Unknowns are in boxes. 1. The input voltage an the loa capacitance C are known as part of your application. 6
2. Determine I INR, the esire inrush current. 3. Compute the resulting output voltage slope, t V OUT: t V OUT = I INR C 4. Select R TIME an C TIME. Note that either one of them can be freely chosen, an the other one compute: R TIME C TIME = 5. Compute the power issipation an ramp time: t V OUT t RAMP = P = 1 2 (I IN ) t V OUT = R TIME C TIME 6. Select a MOSFET. Ensure that its V DS rating can hanle the supply voltage, its R DS(on) is low enough for your application, an that its FBSOA (forwar-bias safe operating area) allows for a pulse of the above compute amplitue an uration. Note its minimum V GS(th) for the next part. 7. Compute C START. For error margin, it shoul be at least ouble the compute value, but o not make it too big, or the startup elay will be unnecessarily long: C START > C TIME ( VIN V GS(th) ) 7 Gotchas This circuit isn t perfect. There are few traps an rawbacks: As presente, the MOSFET must have a V GS(max) rating in excess of. If this is impractical, a secon resistor R LIMIT can be place in parallel with C START, forming a voltage ivier to set the final gate voltage. Perhaps counter-intuitively, this oes not change the timing resistance to be the Thévenin equivalent of R LIMIT an R TIME, for the same reason that C START oes not affect the timing. This circuit only limits capacitive inrush. If your inrush is for other reasons, for instance V DD ramp inrush of a large igital evice like an FPGA, it may actually worsen it. Min the maximum ramp times of the evices you are powering. If you have voltage regulators ownstream, it may be esirable to a an RC elay to their enable inputs to start them after this circuit has stabilize. 7
This is not a precision circuit! For the example above, I INR shoul have been C 1000 µf 12 V 1 MΩ 100 nf R TIME C TIME = = 120 ma, but it was actually 55 ma, a massive 54% error! Note that SPICE simulation verifies the accuracy of these equations, so other real-worl effects were at play here. When using more ieal components (accurate ceramic capacitors with low C(V) epenence, in particular), the real measurements will be closer to the preicte values. This circuit oes not provie reverse-polarity protection. It can be moifie with one aitional FET, though ual MOSFETs with both evices in the same package are hany here: R LIMIT C TIME C START R TIME C Figure 9: The full circuit with aitional RPP. 8 Worke example As an example, we ll esign an inrush limiter for a USB evice. Specifications are: : 5 V nominal C : 220 µf I OUT at startup: 20 ma Maximum I IN : 113 ma [3] C IN : min. 1 µf, max. 10 µf [3] 1. The input voltage an the loa capacitance C are known as part of the application. 2. I IN must not excee 113 ma, an the loa will raw I OUT = 20 ma at startup, so I INR must not excee 113 ma 20 ma = 93 ma. 8
3. Compute the resulting output voltage slope, t V OUT: t V OUT = t V OUT = 93 ma 220 µf I INR C = 423 V/s 4. Select R TIME an C TIME. It is likely that the system will alreay contain 100 nf capacitors, so we ll set C TIME = 100 nf. R TIME = R TIME C TIME = C TIME t V OUT t V OUT = 118 kω 120 kω 5. Compute the power issipation an ramp time. Note that this uses I IN, the total input current, not I INR, the inrush current to the capacitor. P = 1 2 (I IN ) P = 1 (5 V 113 ma) = 283 mw 2 t RAMP = t V OUT = R TIME C TIME t RAMP = (120 kω) (100 nf) = 12 ms 6. Select a MOSFET. I m going to use International Rectifier s IRLML6402, which has a low R DS(on) of 65 mω, a minimum V GS(th) of 400 mv, an fits the above power issipation nicely into its FBSOA[2]. 7. Compute C START. For error margin, it shoul be at least ouble the compute value, but o not make it too big, or the startup elay will be unnecessarily long: C START > C TIME C START > (100 nf) ( VIN C START > 1.25 µf V GS(th) ) ( ) 5 V 0.4 V A 2.2 µf capacitor woul be reasonable for C START an give some error margin. 9
8. The USB example is unique in that it has a minimum input capacitance, of 1 µf. The input capacitance of this circuit itself is the series combination of C START, C TIME, an C, which is 96 nf. We ll a a secon 2.2 µf at the input, which places the total input capacitance at about 2.3 µf. V BUS IRLML6402 C TIME 100nF C IN 2.2µF C START 2.2µF R TIME 120kΩ C 220µF GND Figure 10: Example with values Figure 11: Simulate example References [1] P. Horowitz an W. Hill, The art of electronics, 3r e. Cambrige [Englan]: Cambrige University Press, 2014. 10
[2] International Rectifier, IRLML6402PbF HEXFET Power MOSFET, 2014. [Online]. Available: http://www.irf.com/prouct-info/atasheets/ata/ irlml6402pbf.pf. [Accesse: 23 Nov 2015]. [3] USB Implementers Forum, Universal Serial Bus Specification, rev 2.0. 2000, pp. 7.2.4.1. Available: http://www.usb.org/evelopers/ocs/usb20 ocs/. [4] J. Walker, FET Supplies Low-Voltage Reverse-Polarity Protection, ElectronicDesign.com, 2005. [Online]. Available: http://electronicesign.com/power/ fet-supplies-low-voltage-reverse-polarity-protection. [Accesse: 23 Nov 2015]. 11