ENGG1015 Homework 1 Question 1. ENGG1015: Homework 1

ENGG1015 Homework 1 Question 1 ENGG1015: Homework 1 Due: Nov 5, 2012, 11:55pm Instruction: Submit your answers electronically through Moodle (Link to Homework 1). You may type your answers using any text editor of your choice, or you may submit a scanned copy of your hand written answer. Acceptable file format: Text file (.txt) OpenDocument file (.odt) MS Word file (.doc /.docx) Portable Document File (.pdf) You need to design your circuit in Logisim for question 2. Logisim can be downloaded freely from http://ozark.hendrix.edu/~burch/logisim/. It runs on Linux, Mac, and Windows machines. Question 1 Four-bit subtractor You and your lab partner has just completed Lab 2 on the design of a four-bit adder. Feeling very adventurous, your group partner suggests to embark on a design of a four-bit subtractor using combinational logic. The circuit is intended to calculate x y = d, where x is represented by four bits as x 3 x 2 x 1 x 0, y is represented by four bits as y 3 y 2 y 1 y 0, and the difference, d, is also represented by four bits as d 3 d 2 d 1 d 0. Your group partner reasons that she should build a one-bit subtractor first, and use it as a building block to complete the entire four-bit subtraction. She also quickly realizes that even for a one-bit subtraction, she needs to borrow from the next bit if x 0 < y 0. She calls this signal borrow, and label it b 0. She requires that b 0 = 1 if and only if there is a need to borrow from the next bit. Part(a) Complete the following truth table for a 1-bit subtractor with a borrow bit. x 0 y 0 b 0 d 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 Part(b) Based on the above truth table, your partner has constructed the following one-bit subtractor circuit, which she then labels as a sub-circuit with the name HS. Label on the circuit input/output x 0, y 0, d 0, and b 0. HS x 0 y 0 d 0 b 0 EEE/ENGG1015/2012 Page 1 of 9

ENGG1015 Homework 1 Question 1 Part(c) Next, she proceeds to design a one-bit subtractor for the remaining bits. She argues that now she needs three inputs: for example, to calculate x 1 y 1, she also needs to know b 0, i.e. whether there has been a borrow in the previous calculation of the bit to the right. Complete the following truth table: Part(d) b 0 x 1 y 1 b 1 d 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 Write b 1 and d 1 as a sum-of-product of the three inputs. Part(e) b 1 = b 0 x 1 y 1 + b 0 x 1 ȳ 1 + b 0 x 1 y 1 + b 0 x 1 y 1 d 1 = b 0 x 1 y 1 + b 0 x 1 ȳ 1 + b 0 x 1 ȳ 1 + b 0 x 1 y 1 Use Karnaugh map to simplify the expressions for b 1 and d 1. Show your steps in the answer. The Karnaugh maps are as follows (b 1 on the left, d 1 on the right): x 1 y 1 b 0 00 01 11 10 0 0 1 0 0 1 Hence we can simplify b 1 to 1 1 1 0 b 1 = b 0 x 1 + b 0 y 1 + x 1 y 1 x 1 y 1 b 0 00 01 11 10 0 0 1 0 1 1 1 0 1 0 while the expression for d 1 given in the sum-of-product form in the previous part is already the simplest. Part(f) The HS sub-circuit, with the same positioning of the inputs and outputs, is now used to build the one-bit subtractor with x 1, y 1, and b 0. The student designs it as follows: x 1 HS HS r y 1 s b 0 Show that r and s give you d 1 and b 1. Which is which? EEE/ENGG1015/2012 Page 2 of 9

ENGG1015 Homework 1 Question 2 Let us label the upper output of the first HS as m, and the lower output as n. Note that n is also the input to the OR gate. The lower output of the second HS, which is also the other input to the OR gate, is labeled p. From the truth table in the first part of the problem, we know m = x 1 y 1 = x 1 ȳ 1 + x 1 y 1 Now we can use these to compute r and s: m = ( x 1 + y 1 )(x 1 + ȳ 1 ) = x 1 y 1 + x 1 ȳ 1 n = x 1 y 1 p = mb 0 = b 0 (x 1 y 1 + x 1 ȳ 1 ) r = m b 0 = b 0 x 1 y 1 + b 0 x 1 ȳ 1 + b 0 x 1 ȳ 1 + b 0 x 1 y 1 s = p + n = b 0 (x 1 y 1 + x 1 ȳ 1 ) + x 1 y 1 Therefore, r is d 1. Although the expression for s looks different from b 1 either from the sum-ofproduct or from the Karnaugh map simplification, they are in fact the same, as you can check by producing a truth table for s. Part(g) You are now ready to test the four-bit subtractor. subtractor. What is the output d? The output is d = 0111. Part(h) Try to perform 1101 0110 using your You then proceed to calculate 0110 1101. What is the output d? Explain why. The output is d = 1001. The result is wrong. This is because 0110 is smaller than 1101, and therefore the subtraction result is negative. Question 2 Traffic Light As an elite engg1015 student, the traffic department has just hired you to redesign the traffic light control in their new smart traffic light system. As shown in Figure 1, the basic operation of the traffic light is a very simple sequence: The light starts with lighting red for 60 seconds, turn to both red+yellow color for 5 seconds, then green for 60 seconds, then yellow for 5 seconds, and finally return to red and the cycle repeats. 60 seconds 5 seconds 60 seconds 5 seconds Figure 1: Traffic light sequence Part(a) State Transition Diagram You have decided to use four (4) states to represent the state during which the traffic light displays red, red+yellow, green, and yellow respectively. Furthermore, to keep track of the time a light is on, a simple binary counter is used. When the signal startcnt is asserted (set to 1 ), the counter starts counting from 0 after the clock edge. EEE/ENGG1015/2012 Page 3 of 9

ENGG1015 Homework 1 Question 2 The counter send two signals back to the state machine. The signal cnt5 is asserted when the counter s value is 5. The signal cnt60 is asserted when counter s value is 60. The counter is clocked at 1Hz. The following table summarizes the I/O signals for your traffic light control: Type Name Description input cnt5 1 when the counter s value is 5, indicating 5 seconds have passed. 0 otherwise. cnt60 1 when the counter s value is 60, indicating 60 seconds have passed. 0 otherwise. output startcnt Output to the binary counter to start counting from zero. R 1 to turns on red light, 0 otherwise Y 1 to turns on yellow light, 0 otherwise G 1 to turns on green light, 0 otherwise Complete the following state transition diagram for the traffic light control. Part(b) cnt60 = 0 / R=1,Y=G=0 startcnt = 0 cnt5 = 1 / R=G=0,Y=1 startcnt = 1 cnt5 = 0 / R=G=0,Y=1 startcnt = 0 RED YELLOW cnt60 = 1/ R=1,Y=G=0 startcnt=1 cnt60 = 1/ R=Y=0,G=1 startcnt=1 Next State & Output Logic cnt5 = 0 / R=Y=1,G=0 startcnt = 0 RED-YELLOW GREEN cnt60 = 0 / R=Y=0,G=1 startcnt = 0 cnt5 = 1 / R=Y=1,G=0 startcnt = 1 You have decided to utilize the following state encoding for the four states: State s1 s0 RED 0 0 RED-YELLOW 0 1 YELLOW 1 0 GREEN 1 1 Based on your state transition diagram and the above state encoding, complete the following truth table concerning the next state and output logic of the traffic light control state machine. EEE/ENGG1015/2012 Page 4 of 9

ENGG1015 Homework 1 Question 2 Part(c) s1 s0 cnt5 cnt60 ns1 ns0 startcnt R Y G 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 1 Logisim Implementation Implement the above traffic light control state machine in Logisim. Apart from the I/O described above, your machine should also include a clock input clk, and a reset input clr. The following table summarizes the input/output ports of your state machine. The column Order indicates the order of the pin in the circuit symbol. Direction Order Name Logisim Type input 1 cnt5 Pin 2 cnt60 Pin 3 clk Pin 4 clr Pin output 1 startcnt Pin 2 R Pin 3 Y Pin 4 G Pin Your circuit will be graded automatically, so it is very important for you to use the exact pin names in the above table in your circuit. Download the file http://www.eee.hku.hk/ ~engg1015/fa12/handouts/hw1src.zip. You may use the included tlight.circ as a template for your design. You may find the file tlight-test.circ useful for testing your circuit. Put the two files (tlight.circ and tlight-test.circ) in the same directory for the file tlight-test.circ to run. Save your answer in tlight.circ and submit this file via Moodle. Part(d) A Smarter Traffic Light System The traffic department wants to improve the basic traffic light from the previous part to relieve Hong Kong s traffic problem. A new sensor is installed in the road to determine the number of cars waiting in front of the traffic light. The sensor produces a signal carwait to your traffic light state machine. carwait is 1 when more than 10 cars are waiting in front of the traffic light, 0 otherwise. Using the new signal, a new light controlling algorithm is added on top of the basic control. With the new algorithm: If more than 10 cars are waiting while the light is RED, it should turn to GREEN (via RED-YELLOW) immediately. If more than 10 cars are waiting while the light is GREEN, it indicates the road is jammed. Turn the light to RED (via YELLOW) to relieve traffic in cross direction. If carwait is 0, the traffic light operates according to the simple sequence in Part (a). EEE/ENGG1015/2012 Page 5 of 9

ENGG1015 Homework 1 Question 3 Complete the following state diagram incorporating the improved smart algorithm: Part(e) cnt60=0 & carwait=0/ [R=1,Y=G=0 startcnt = 0] cnt60=1 & carwait=0/ [R=1,Y=G=0 startcnt=1] cnt5 = 1 / [R=G=0,Y=1 startcnt = 1] cnt5 = 0 / [R=G=0,Y=1 startcnt = 0] RED YELLOW carwait = 1 / [R=Y=0,G=1 startcnt=1] carwait=1 / [R=1,Y=G=0 startcnt=1] cnt5=0 / [R=Y=1,G=0 startcnt = 0] RED-YELLOW GREEN cnt5=1 / [R=Y=1,G=0 startcnt = 1] cnt60=1 & carwait=0/ [R=Y=0,G=1 startcnt=1] cnt60=0 & carwait=0/ [R=Y=0,G=1 startcnt = 0] Smart Traffic Light Control in Logisim Implement your improved state machine in Logisim. It should be similar to the above previous machine except for the additional carwait input. The carwait signal should have an order of 1 and is the top-left-most pin in the symbol. You may use the file smartlight.circ included in hw1files.zip you downloaded above as a starting point. Similarly, you may use smartlight-test.circ to test your design. Submit your design in smartlight.circ in Moodle. Question 3 Force Sensitive Resistor A force sensitive resistor (FSR) is a resistor with its resistance changed according to the force applied to it. The table below shows the resistance of a sample FSR. For your reference k and M are SI units that represents 10 3 and 10 6 respectively. Force (N) Resistance R fsr (Ω) 0 1 M 0.5 10k 1 6k 10 1k Your project partner has decided to use such FSR in the project. For simplicity sake, he has wired up the FSR using a simple potential divider circuit as shown in Figure 2. Vcc = 12V R fsr vout R ref Figure 2: Connecting an FSR with a potential divider configuration. Part(a) For each value of force shown in the above table, calculate the following quantities when R ref = 10kΩ: EEE/ENGG1015/2012 Page 6 of 9

ENGG1015 Homework 1 Question 3 1. Current flowing through the FSR; 2. Voltage across the FSR; 3. Voltage at V out. Part(b) R fsr I fsr V fsr V out 1M 11.9 µa 11.9V 0.1V 10k 0.6 ma 6 6 6k 0.75 ma 4.5 7.5 1k 1.09 ma 1.09V 10.91 V The output V out is used to detect the presence of a ball. Due to its light weight, the ball produces only 0.5N when it is located on top of the sensor. The rest of the system requires that V IL = 2V and V IH = 10V, where V IL is the maximum voltage that the system regards as logical LOW and V IH is the minimum voltage that the system regards as logical HIGH. Determine the range of value that R ref may take for correct functioning of the circuit It should output a logical HIGH when a ball is presence and a logical LOW otherwise. When the ball is on the sensor, R fsr = R H = 10000. The output voltage at that time should be higher than V IH. Similarly, when the ball is not on the sensor, then R fsr = R L = 10000000. the output voltage at this time should be lower than V IL. Therefore, { R VIH < 12 ref 12 R ref R L +R ref R H +R ref < V IL { R ref > R H R ref < R L 50k < R ref < 200k V IH 12 V IH V IL 12 V IL Part(c) Your group partner suggests that it may be possible to use 2 FSRs connected as shown in the following figure to perform a logical OR operation: When the ball rolls over either one of the 2 FSRs, the output V out is HIGH, and is LOW otherwise. EEE/ENGG1015/2012 Page 7 of 9

ENGG1015 Homework 1 Question 3 Vcc = 12V R fsr R fsr R ref What is the output voltage V out in the following three cases: (i) 1 of the FSRs is under pressure of 0.5N, (ii) both FSRs are under a pressure of 0.5N each, (iii) none of the FSRs is under pressure. Assume R ref is 100kΩ. Below, R eqv is the equivalent resistance of the parallel combination of the two FSRs. R ref = 100kΩ. Case R fsr1 R fsr2 R eqv V out (i) 10000 1000000 9901 10.9 (ii) 10000 10000 5000 11.4 (iii) 1000000 1000000 500000 2 Part(d) Recall that V IL is 2V and V IH is 10V, is the circuit functioning correctly as a 2-input OR function? If there are 3 FSRs connected in parallel, assumer R ref remains at 100kΩ, will the circuit behave as a 3-input OR function? Explain your answer. Yes, it works correctly as a 2-input OR gate because the output is HIGH when there is a ball on top of at least one of the input. However, even if we connect 3 FSRs in parallel, the circuit cannot correctly function as a 3-input OR gate. In the case when there is no ball falling on the circuit, the equivalent resistance of the parallel combination of the 3 FSRs drops too low that V out > 2V. As a result, the output fails to represent a logical LOW in this case. R fsr1 R fsr2 R fsr3 R eqv V out 1000000 1000000 1000000 333333.33 2.77 1000000 1000000 10000 9803.92 10.93 1000000 10000 1000000 9803.92 10.93 1000000 10000 10000 4975.12 11.43 10000 1000000 1000000 9803.92 10.93 10000 1000000 10000 4975.12 11.43 10000 10000 1000000 4975.12 11.43 10000 10000 10000 3333.33 11.61 vout EEE/ENGG1015/2012 Page 8 of 9

ENGG1015 Homework 1 Question 4 Question 4 Feedback Questions Answering this question is optional, but your answer will help us evaluate the course more effectively. Part(a) Mathematics for Signals, Systems & Control 1. Evaluate 1 + i, where i = 1. 2. Find the roots of z 2 + 5z + 1. 3. Find the roots of z 2 + 2z + 3. 4. We have Find A and B. 5. We have 3 + i = Ae iθ. Find A and θ. Part(b) Lectures & Labs 1 z 2 + 3z + 2 = A z + 2 + B z + 1. 1. How much time have you spent on this homework? 2. Do you think 2 hours of lab is enough? If not, is a 3-hour session a better option? 3. Have you checked off labs during TA office hours? If so, were the TAs helpful during office hour? 4. Any other comments on lecture? EEE/ENGG1015/2012 Page 9 of 9