XBee Wi-Fi Dev Kit Block Diagram Socketed Through-hole Variant PART NO O c Digi International Inc. 6. Disconnect switches

Similar documents
SM XBEE MODULE XBEE SMT MODULE NC GND GND RF_SELECT VCC COMM/AD0/DIO0 AD1/DIO1 DOUT/DIO13 AD2/DIO2 DIN/CONFIG/DIO14 DIO12 AD3/DIO3 RESET RTS/DIO6

XBee Interface Board XBIB-U-DEV TH/SMT Hybrid

Dev Board for CC IMX28. Mechanicals Board Size should be 7 X 8 inches Group similar connections together (ENET, USB, UART, etc) H5 ANT1

UART Switches. DIO Switches. SPI Switches TEST POINTS 2 x 0.1 Inch Header UART SPI. Other DIO. XLR radio. (1W linearity requires 4W DC)

Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power

Quickfilter Development Board, QF4A512 - DK

Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.

05 - Adaptacion Puerto Serie RXD_UC R35 0 DTR_UC R36 0 RI_UC Adaptacion Puerto Serie Señalizacion GSM R37 0 INFO_NETLIGHT R38 0

Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

HF SuperPacker Pro 100W Amp Version 3

MSP430F16x Processor

LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.

AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index

EDP-AM-DIO54 Digital IO Module User Manual. This document contains information on the DIO54 digital IO module for the RS EDP system.

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0

U1-1 R5F72115D160FPV

MARK WH-S1 SHELF 208V; 1 PHASE; 4.5 KW TMV-B FLOOR 199CFH, 2 HTRS, 2 STORAGE FLOOR - WALL HYDRANT ABV ABOVE AFF ABOVE FINISHED FLOOR

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-

S08P-LITE. 1 Title Page 2 Block Diagram 3 MCU & Arduino Headers 4 OSBDM & Power Supply 5 On-board Peripherials S08P-LITE. 23-Jun-17. V3.


P300. Technical Manual

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT

SERVICE MANUAL BG3R TRINITRON COLOR TV CHASSIS. KV-AR25M60 RM-995 Thailand. KV-AR25N90 RM-996 Philippines KV-AR25M80 RM-995 ME KV-AR25M66 RM-993 GE

Inverted Input A to make routing easier fix in FPGA U2 ADS62P4X LVDS ADC

MATC DIGITAL ELECTRONICS LAB ASYNCHRONOUS RIPPLE COUNTERS

FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13

P&E Embedded Multilink Circuitry

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1

Reference Schematic for LAN9252-HBI-Multiplexed Mode

Desired Part Placement. Max current set to 3A (motor Drive is 2.5A) SCI-DRV8814-MVK Mike Claassen B1 Dawn Ritz 40V. VDC_In GND. Board Test Points TP1

TX J WBX Common TITLE B 01 SCH,WBX,50 MHZ 2.2 GHZ TRANSCEIVER FILE: common_wbx.sch C104 NONE. C pF AGND:1 J101 C103 NONE RF_RX

DOCUMENT NUMBER PAGE SECRET

[1] [1] C7 10nF. C4 10nF SCL [2] SDA [2] CS_SD PWR_PRSNT [4] INT_BTN0 [2] INT_BTN1 [2] LOADER_EN [4] [1] TXLED [1] J11 [1] RST +3V3 RST

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History

Vr Vr

Host MSP430. dacqs_host_board 12/7/2016 9:26 PM. U1 Value +3V3 AVCC_HOST UART_1_TX UART_1_RX MSP_SCLK UART_2_TX UART_2_RX CUTDOWN_EN MSP_SS

Renesas Starter Kit for RL78/G13 CPU Board Schematics

Chapter 5 CMOS Logic Gate Design

U100. cgen_by BYPASS. cgen_cp CLK_FPGA_P (OUT0A) OUT0 CLK_FPGA_N (OUT0B) OUT0 (OUT1A) OUT1 (OUT1B) OUT1 (OUT2A) OUT2 U10 DS90LT012AH (OUT2B) OUT2

YROTATE-IT-RX23T YROTATE-IT-RX23T_3-10.SCH YROTATE-IT-RX23T YROTATE-IT-RX23T_9-10.SCH. Date APR, 29, 2015 Sheet.0 OF

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs

PM150CBS060 Intellimod Module MAXISS Series Multi AXIS Servo IPM 150 Amperes/600 Volts

24CKT POLARIZATION OPTIONS SHOWN BELOW ARE REPRESENTATIVE FOR 16 AND 20CKT

MIL-DTL-5015 Style Circular Connectors

+18VL. 220uf 25V. 0.1u C10UF. 100k AGND LEFT_OUT_+VE R19 22R -18VL. C9 150pF +18VL LEFT_OUT_-VE R uf 25V 22R

C107 C108 C uF/10V Ta. 10uF/10V Ta. 100nF. 100nF. 100nF C106 C111 C110 VCC VCC AVCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5

PS12038 Intellimod Module Application Specific IPM 25 Amperes/1200 Volts

Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11

9.9 L1N1F_JL 19bo. G)&) art9lej11 b&bo 51JY1511JEJ11141N0fM1NW15tIr1

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board

SA CH SEGMENT /COMMON DRIVER FOR DOT MATRIX LCD

X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA

Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:

:3 2 D e c o de r S ubs ys te m "0 " One "1 " Ze ro "0 " "0 " One I 1 "0 " One "1 " Ze ro "1 " Ze ro "0 " "0 "

PCAN-MicroMod Evaluation Kit. Test and Development Environment for the PCAN-MicroMod. User Manual

Chapter y. 8. n cd (x y) 14. (2a b) 15. (a) 3(x 2y) = 3x 3(2y) = 3x 6y. 16. (a)

CD300.

CENTER POINT MEDICAL CENTER

ML ML Digital to Analog Converters with Serial Interface

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode

7.5V~~12V DC INPUT 0.925V*(1+26.1/10.2)=3.3V 7.5V~~12V DC ADAPTER 0.925V*(1+44.2/10)=5V VCC_IN VCC_IN 5VD 5VD D5 1N4148 C102 10NF 3.

SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:

Scalar Diagram & C.B.A

The AN/ARC-54. Module Circuit Diagrams

Neotec Semiconductor Ltd. 新德科技股份有限公司

Chapter - 1 Direct Current Circuits

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N

p-n junction biasing, p-n I-V characteristics, p-n currents Norlaili Mohd. Noh EEE /09

MC1723C VOLTAGE REGULATOR

PCIextend 174 User s Manual

SWAGELOK BRISTOL SOPFAB SOPFAB04-AR-271A/B SAMPLE TO ANALYSER SURPLUS TUBE CUTBACK TO SUIT AIR IN CAL 1 FLARE CAL 2 STEAM IN AIR IN

Absolute encoders multiturn

The intersection and the union of the asynchronous systems

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

OPERATIONAL AMPLIFIER

OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP

ATS177. General Description. Features. Applications. Ordering Information SINGLE OUTPUT HALL EFFECT LATCH ATS177 - P L - X - X

Representative Schematic Diagram. Standard Application ORDERING INFORMATION DEVICE TYPE/NOMINAL VOLTAGE MOTOROLA ANALOG IC DEVICE DATA

VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD

Power. I/O Extensions. CPU Extensions. JADE-D Subsystem

WHAT A SINGLE JOINT IS MADE OF RA

PRECISION OPERATIONAL AMPLIFIERS

Winsome Winsome W Wins e ins e WUin ser some s Guide

EE100Su08 Lecture #9 (July 16 th 2008)

12.1 Triangle Proportionality Theorem

IX. TRANSISTOR CIRCUITS

A L A BA M A L A W R E V IE W

GR16. Technical Manual. 10 M SPS, 16-bit Analog Signal Digitizer up to 8MB FIFO

HYDRONIC EQUIPMENT SCHEDULE EQUIPMENT MANUFACTURER MODEL SPECIFICATIONS NOTES

4 4 N v b r t, 20 xpr n f th ll f th p p l t n p pr d. H ndr d nd th nd f t v L th n n f th pr v n f V ln, r dn nd l r thr n nt pr n, h r th ff r d nd

Transcription:

0 Xee Wi-i or Xee Z isconnect switches ar raph river ar raph U-to-serial converter U onnector Vibration Motor Power upply Input:.V to V Output:.V PWM-to-frequency converter circuit uzzer (kz) arrel ack uttons/witches/s Potentiometer Prototyping rea / readboard RV O RIPTI O N Y PPR T TIT PPROV: T: IN: RWN: : NINR: Xee Wi-i ev it lock iagram PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT RWIN 00-0 T of

0 U- TR OI OO V_U 00-000 0 00 Ohm/ 00 Ohm/ R M.n 0u U_ V_U M-0R VP VN U_- U_- 0u V_U [-] 00n TR requires.0v minimum to use the internal oscillator. V_U 0 U- TR V VIO N N N N U_ VOUT R 00n TT RT UP UM N N TX RX RT T TR R RI U0 U U U U 0 R R URT_TX URT_RX URT_RT URT_T Yellow U_UPN V_V R R Yellow V_V MR0T V_U P M-R VIN MR0T u U OZI_O VIN M M u 00u/V [-0] 0u 00u/V [-0] 0u 00p R.n R 0 u VP N OMP VI N 0 X P 00n MR0T u R. R 0 u [-] 00u 0 Ohm/ u 0u 00u V_V N OZ good for. V to V TP 0 TP 0 TP 0 TP 0 TP 0 RV O RIPTI O N Y PPR T round Test lips pread evenly around P. O c igi International Inc. 0 ll rights reserved O NOT RWIN PPROV: IN: RWN: : NINR: T: TIT PRT NO. Xee Wi-i ev it Power Input/upply and U 00-0 T RV. of

0 VIN 0 W-0-0-T- V_U W-0-0-T- V_V W-0-0-T- W-0-0-T- oop-back umper: llows loop-back testing of the Xee module while monitoring the communications over the serial port. V_V efault umper Not onnected TP0R These transistors make the URT connection open-collector preventing contention with the TR U chip. V_V R0 TP P TW-0-0-- TP0 V_V R V_V W-0-0-T- W0 -MT Q- TU-- Q- TU-- P W -MT W-0-0-T- URT_RX URT_TX URT_T URT_RT _RN PWM_U 0 X_IO/OUT X_IO/IN/I X_IO//PI_MIO X_IO0/PWM0 X_IO/PWM X_IO/TR/P_RQ X_IO0/0/ommtn X_IO//PI_TTN X_IO//PI_ X_IO//PI_ X_IO/RT X_IO/O 0 WIT_OMM N_POT N X N Y N Z I_VI PWM_UZZR WIT_I 0 This switch is upside-down so that the -direction of the switch points away from the Xee on the layout. This was done only for aesthetics of the design. Xee ignal isconnects ll switches by default. W -MT 0 _O _R I_UZZR WIT_UR0 X_IO/_P V_V TP0R X_IO/T X_IO/PI_MOI V_V TP0R P P RV O RIPTI O N Y PPR T P 00-0 P 00-0 TNI 000 TXT O c igi International Inc. 0 ll rights reserved O NOT RWIN PPROV: IN: RWN: : NINR: T: TIT PRT NO. Xee Wi-i ev it Mechanicals/eaders 00-0 T RV. of

0 V_V R U- IX P R R T VOUTX VOUTY VOUTZ.u R N X PWM_U R 0u R0 00 V_V R U- MV IN_IN MO_ 0 _0 _0 _0 _0 _0 -X0I V_V V_V 0u 00n U- IX V N N N N N N N N 0.u.u R R W -MT N Y N Z Potentiometer caling.k =>.V (nom),.0v (min).k.k =>.V (nom),.0v (min) R is currently unused. R_OUT ~=.V R. R 0u 00n 0 IVIR_I R_OUT R_UT IVIR_OW V_V V V- U- MV N 0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 0 0 0 R 0 0u N_POT W N MT O R. W MT/-MT R. R. V_V Potentiometer caling.k =>.V (nom),.0v (min).k.k =>.V (nom),.0v (min) R is currently unused. I_VI R u R 0 V_V Q NP V_V V_V V_V R I_UZZR PWM_UZZR R V_V R0 00 R 0 V_V R. Q NN R 0 R W MT/-MT 0u R 00 R R 0 Q0 NP R 0 R - R0 0 U- MP0T-/M 0 R0 0 R 0.n Q- TU-- R O c igi International Inc. 0 ll rights reserved O NOT RWIN - R 00 U- MP0T MR0T 0u R 00n Volume adjustment Q0P - Q- TU-- V_V V U- MP0T V- RV O PPROV: IN: RWN: : NINR: RIPTI O N T: TIT 0n PRT NO. Y M - M 0-0 PPR Xee Wi-i ev it Widgets T 00-0 T RV. of

0 X MT MOU N R V_X X_IO/OUT X_IO/IN/I X_IO//PI_MIO X_RT X_IO0/PWM0 X_IO/PWM RRV X_IO/TR/P_RQ N 0 0p/--00-0-00000 0p/--00-0-00000 0 X_IO0/0/ommtn X_IO//PI_TTN X_IO//PI_ X_IO//PI_ X_IO/RT X_IO/O X_VR X_IO/_P X_IO/T X_IO/PI_MOI V_X X_IO/OUT X_IO/IN/I X_IO//PI_MIO X_RT X_IO0/PWM0 X_IO/PWM X_U_WIO_ X_IO/TR/P_RQ 0 N N V OUT/IO IN/I/IO IO RT PWM RI/IO0 PWM/IO U/WIO_ TR/IO N TTN/IO N N R_T OMM/0/IO0 /IO /IO /IO RT/IO O/IO VR /P/IO T/IO IO W_ N 0 N X_IO0/0/ommtn X_IO//PI_TTN X_IO//PI_ X_IO//PI_ X_IO/RT X_IO/O X_VR X_IO/_P X_IO/T X_IO/PI_MOI W_ Xee ockets mm pitch, for OM only. PI_/IO PI_/IO PI_MOI/IO PI_MIO/IO T/W_0 TO/WO_0 TI/WO_ TM/WIO_0 X_U_WIO_ P0 xp/0xx X_RT 0 TP TP TP TP X_WIO X_TI X_WO X_W V_V W_ V_X P W-0-0-- X_IO/PI_O/x R V_X X_IO/PI_I/x X_IO/PI/x X_IO/PI_/x X_IO/PI_TTN V_X 00u 0u X_IO/OUT X_IO/IN/I X_IO//PI_MIO X_RT X_IO0/PWM0 X_IO/PWM RRV 00n X_IO/TR/P_RQ p.p N 0 N W-0-0-T- V OUT IN/I IO RT RRV Xee R MOU 0/IO0 /IO /IO /IO RT//IO PWM0/RI/IO0 O//IO PWM/IO TR/P_RQ/IO VR /P/IO T/IO 0 N /IO X MOU 0 0 W-0-0-T- X_IO0/0/ommtn X_IO//PI_TTN X_IO//PI_ X_IO//PI_ X_IO/RT X_IO/O X_IO/_P X_IO/PI_MOI O c igi International Inc. 0 ll rights reserved O NOT RWIN X_VR X_IO/T RV O PPROV: IN: RWN: : NINR: RIPTI O N T: TIT PRT NO. Y PPR Xee Wi-i ev it Xee T 00-0 T RV. of

0 V_U V_V R R R RN oftp W T00Q WIT_OMM U_UPN R R 00 Q NN R RN User utton IO _O R R 00 Q NN R RN WIT_UR0 W T00Q _RN R Q NN R R 00 R lide witch IO/P_RQ _R R0 R 00 Q NN WIT_I W 00M0Q Xee Reset W TW-R X_RT 00n RV O RIPTI O N Y PPR T TIT PPROV: T: IN: RWN: : NINR: Xee Wi-i ev it uttons/witches/s PRT NO. RV. O c igi International Inc. 0 ll rights reserved O NOT RWIN 00-0 T of

- P0 R W0 0 W W TP P TP U W P U R W R0 Q R U R R R M 0 P 0 TP R 0 TP W W RV O RIPTI O N Y PPR T PPROV: IN: RWN: T: TIT ssembly TOP : NINR: O c igi International Inc. ll rights reserved PRT NO. 00-0 O NOT RWIN T RV. of

R R W R R R TP TP0 TP R Q R R R TP TP TP R R R R TP R R R R0 W R R R R0 R Q R R R R R Q R R R R Q R R U 0 Q0 R Q R R R R R0 R R R R 0 R Q R R0 Q R R U 0 R0 R W R R RV O RIPTI O N Y PPR T PPROV: IN: RWN: T: TIT ssembly OTTOM : NINR: O c igi International Inc. ll rights reserved PRT NO. 00-0 O NOT RWIN T RV. of