Power power.sch udio SOUN_OUT audio.sch Phi P[0..] P[0..] Phi P[0..] P[0..] PU Phi P[0..] P[0..] [0..] [0..] I/O MP ROMIS Phi [0..] [0..] I/O MP ROMIS Phi UL [0..] [0..] VI_S MP ula.sch LUE RE SYN M[0..] RS S _RM SROM LUE RE SYN M[0..] RS S _RM SROM VideoGenerator LUE RE SYN video.sch Memory M[0..] RS S SROM ROMIS Phi SOUN_OUT SYN_IN [0..] [0..] Tape SOUN_OUT P[0..] SYN_IN cpu.sch memory.sch tape.sch Revision Log: Issue : Last official Oric version Issue : Include all official rework from Oric Product Inc Issue : Include changes from Oric International (dd TR, R, LK,, ), Issue.: dd official support for the VSYN "hack". RL changed to a Two Pole, SK changed to a IN to add on the same place as OI does. (pin and will provide SYN IN and UIO OUT.) dded LK to allow use of a single pole relay Issue : Make the hardware VSYN working dd pins for a reset button Remove unusefull I0 and change to make /ROMIS working on all type of ROM chips. dd the possibility to use a x storing to ROM banks Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: / File: Oric.sch Title: Oric- / tmos Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
V SK RREL_JK + 00uF 0V I nf nf 0 nf nf nf nf nf nf nf nf nf nf nf nf 0 nf GN VI VO 0 Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /Power/ File: power.sch Title: Power supply Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
P[0..] GN R K 0uF + - Pwr Gnd LM I Gain Gain 0uF 0V SP P 0 R n SPEKER K R KEYOR_ONN PL 0 K_V K_INT K_OL K_OL K_GN K_OL K_ROW0 K_ROW K_ROW K_OL K_OL K_OL K_OL K_OL0 P0 P P R K P[0..] S TO TR P[0..] E SOUN_OUT n GN GN 0n 0 R R K K R K_OL K_OL K_OL K_OL K_OL K_OL K_OL K_OL0 0 H_ 0 Test V H_ H_ Y-- IO_ IO_ I IO_ IO_ IO_ ir IO_ IO_ IO_0 LK 0 P0 P P P P P P P P[0..] Phi P[0..] K_OL[0..] SHUNT 0 GN Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /udio/ File: audio.sch Title: PSG Keyboard Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
M[0..] M[0..] M0 M M M M M M M 0 0 I O I 0 M0 M M M M M M M 0 0 I O I I I M0 0 O M0 0 O M M M I M I M M M M M 0 M 0 M M M M RS S RS S RS S RS S S RS M0 M M M M M M M 0 0 I O I I I I M0 0 O M0 0 O M0 0 O M M M M I M I M I M M M M M M M 0 M 0 M 0 M M M M M M RS S RS S RS S RS S GN 0 I LS00 I LS00 [0..] ROMIS ROMIS SROM K RP [0..] If I is x or Original ROM, shunt pin and pin If I is x PL can be connected to a switch to select between two rom bank ONN_0X0 I PL 0K R0 GN LS00 Phi 0K R0 I LS00 I LS0 0 0 [0..] 0 0 I 0 0 VPP E OE Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /Memory/ File: memory.sch Title: RM & ROM Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: / 0 0 [0..]
SOUN_OUT RP 0K R 00K K R SYN_IN TPE_OUT SK IN TPE_IN n TPE_MP R 0K IOE IOE 0K RP If you don't want to use VSYN, or use relay shunt LK - + V- V+ LM I GN R K 0K RP 00n + - V+ V- GN I LM TPE_MP K R LK JUMPER Shunt LK only you want to support VSYN TPE_MP K RELY_RT IOE JUMPER LK RP 0K S TO S TO TR P GN E n E TR GN SHUNT 0 n K R GN R K P P[0..] Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /Tape/ File: tape.sch Title: Oric Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: / P[0..] GN
LUE RE SYN LUE RE SYN 0 R SYN_IN 00n 0 I I I I I I E E I LS O O O O O O RP RP RP RP 0 0 0 0 OUT_LUE SYN_IN OUT_RE OUT_ OUT_SYN SYN_IN M R IN_ SK GN p 0 Sd d I I LS0 LS LS0 I SYN p d Sd I LS PL_LK PL_LK PL_LK I 0 O O O O E E S0 00pF 0 R 0K R R R R K K K K R K 0 RV R GN PL_OMPOSITE 00pF PL ONN_0X0 SOUN_OUT Rext ext 0 Rext ext PL_LK I LS0 R K V.pF 0pF XT.MHz R0 K IE 0 LS0 IF LS0 I LS0 p Sd d I LS p 0 Sd d I LS Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /VideoGenerator/ File: video.sch Title: PL Generation Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: / PL_LK PL_LK I LS lr I LS lr SHUNT 0 GN
Shunt LK if TR and R not fitted PU SW ONN_0X0 0K R SW_PUSH PL NMI K RPE Phi NMI IR 0 0 0 0 RY Phi IR N NMI SYN V 0 0 Phi SO N N 0 MOS0 I 0 0 Phi 0 [0..] LK TR JUMPER NPN [0..] E R Phi MP K RP Phi I/O 0 0 PL 0 0 0 HE0-0 0 0 I/O_ontrol IR 0 ROMIS Expansion Port [0..] [0..] K RP K RP [0..] uf 0V 0 0 Phi I/O_ontrol IR I/O 0 0 PI RS0 RS RS RS 0 MOS I Phi S S IR GN P0 P P P P P P P P0 P P P P P P P V 0 0 P0 P P P P P P P P0 P P P P P P P P[0..] P[0..] P[0..] P[0..] STR P0 P P P P P P P K Printer Port PL 0 0 HE0-0 0 0 Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /PU/ File: cpu.sch Title: PU & VI Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /
R K IF LS0 lock Generation XT MHz [0..] 0pF [0..] [0..] I R0 K LS0 0 R0 0 R 0 0 0 LK 0 0 V M0 M M M M M M M MPX HS00 S RS I _RM MP VI_S SROM SYN RE LUE UL_0 UL_ UL_ UL_ UL_ UL_ 0 UL_ UL_ MPX 0 0 [0..] MP VI_S SROM SYN RE LUE UL_[0..] [0..] I LS0 IE 0 LS0 I LS0 UL_ I0a Za Ia UL_0 I0b 0 Zb Ib I UL_ I0c Zc Ic UL_ LS I0d 0 Zd Id MPX S OE UL_ UL_ UL_ UL_ S RS _RM I0a Za Ia I0b Zb Ib I0 I0c Zc Ic LS I0d 0 Zd Id MPX S OE M M0 M M M M M M M[0..] M[0..] Kicad version (c) 0-0 Studio [Manoel Trapier <godzil@-studio.com>] (c) - Tangerine & Oric International Sheet: /UL/ File: ula.sch Title: UL & Memory decoding Size: ate: 0/0/0 Kiad E... eeschema (0-0-0 ZR )-product Rev: Issue Id: /