NTDNR, NVDNR Power MOSFET mps, 5 Volts NChannel DPK Features Planar HDe Process for Fast Switching Performance Low R DS(on) to Minimize Conduction Loss Low C iss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in HighEfficiency DCDC Converters NVD Prefix for utomotive and Other pplications Requiring Unique Site and Control Change Requirements; ECQ Qualified and PPP Capable These Devices are PbFree and are RoHS Compliant MPERES, 5 VOLTS R DS(on) = 7. m (Typ) G NCHNNEL D MXIMUM RTINGS (T J = 5 C unless otherwise specified) Parameter Symbol Value Unit DraintoSource Voltage V DSS 5 Vdc GatetoSource Voltage Continuous V GS ± Vdc Thermal Resistance JunctiontoCase Total Power Dissipation @ T = 5 C Drain Current Continuous @ T = 5 C, Chip Continuous @ T = 5 C, Limited by Package Single Pulse (tp s) Thermal Resistance, Junctiontombient (Note ) Total Power Dissipation @ T = 5 C Drain Current Continuous @ T = 5 C Thermal Resistance, Junctiontombient (Note ) Total Power Dissipation @ T = 5 C Drain Current Continuous @ T = 5 C R JC P D ID I D I D R J P D ID R J P D ID..8. 8 8.5...5 Operating and Storage Temperature Range T J, T stg 55 to 5 C/W W C/W W C/W W C CSE 9C DPK (Surface Mount) STYLE Drain S MRKING DIGRM & PIN SSIGNMENTS CSE 9D DPK (Straight Lead) STYLE Drain Maximum Lead Temperature for Soldering Purposes, /8 from case for seconds T L C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. When surface mounted to an FR board using.5 sq. in pad size.. When surface mounted to an FR board using minimum recommended pad size. Y WW N G YWW T NG Gate Drain Source Gate = Year = Work Week = Device Code = PbFree Package YWW T NG Drain Source ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Semiconductor Components Industries, LLC, February, Rev. 7 Publication Order Number: NTDNR/D
NTDNR, NVDNR ELECTRICL CHRCTERISTICS (T J = 5 C unless otherwise specified) OFF CHRCTERISTICS Characteristics Symbol Min Typ Max Unit DraintoSource Breakdown Voltage (Note ) (V GS = Vdc, I D = 5 dc) Temperature Coefficient (Positive) V(br) DSS 5 8 Vdc mv/ C Zero Gate Voltage Drain Current (V DS = Vdc, V GS = Vdc) (V DS = Vdc, V GS = Vdc, T J = 5 C) I DSS. dc GateBody Leakage Current (V GS = ± Vdc, V DS = Vdc) I GSS ± ndc ON CHRCTERISTICS (Note ) Gate Threshold Voltage (Note ) (V DS = V GS, I D = 5 dc) Threshold Temperature Coefficient (Negative) V GS(th)..5. Vdc mv/ C Static DraintoSource OnResistance (Note ) (V GS =.5 Vdc, I D = 5 dc) (V GS = Vdc, I D = 5 dc) Forward Transconductance (Note ) (V DS = Vdc, I D = 5 dc) DYNMIC CHRCTERISTICS R DS(on) 7 7. 95 g FS 7. m Mhos Input Capacitance C iss 5 pf Output Capacitance (V DS = Vdc, V GS = V, f = MHz) C oss Transfer Capacitance C rss SWITCHING CHRCTERISTICS (Note ) TurnOn Delay Time t d(on).8 ns Rise Time (V GS = Vdc, V DD = Vdc, t r 7 TurnOff Delay Time I D = 5 dc, R G = ) t d(off) 9. Fall Time t f. Gate Charge (V GS = 5 Vdc, I D = 5 dc, V DS = Vdc) (Note ) SOURCEDRIN DIODE CHRCTERISTICS Forward OnVoltage (I S = 5 dc, V GS = Vdc) (Note ) (I S = 5 dc, V GS = Vdc, T J = 5 C) Reverse Recovery Time (I S = 5 dc, V GS = Vdc, di S /dt = / s) (Note ) Q T.8 nc Q.8 Q.7 V SD.9.8. V dc t rr. ns t a.75 t b.88 Reverse Recovery Stored Charge Q RR. C. Pulse Test: Pulse Width s, Duty Cycle %.. Switching characteristics are independent of operating junction temperatures.
NTDNR, NVDNR TYPICL CHRCTERISTICS I D, DRIN CURRENT (MPS) V 8 8 V 7 V V 5 V.5 V V.5 V V V GS =.5 V 8 I D, DRIN CURRENT (MPS) 8 V DS V T J = 5 C T J = 5 C T J = 55 C 5 V DS, DRINTOSOURCE VOLTGE (VOLTS) V GS, GTETOSOURCE VOLTGE (VOLTS) Figure. OnRegion Characteristics Figure. Transfer Characteristics R DS(on), DRINTOSOURCE RESISTNCE ( )....8. V GS = V T J = 5 C T J = 5 C T J = 55 C 8 R DS(on), DRINTOSOURCE RESISTNCE ( )....8. T J = 5 C T J = 5 C T J = 55 C V GS =.5 V 8 I D, DRIN CURRENT (MPS) I D, DRIN CURRENT (MPS) Figure. OnResistance versus Drain Current and Temperature Figure. OnResistance versus Drain Current and Temperature R DS(on), DRINTOSOURCE RESISTNCE (NORMLIZED).8....8 I D = 5 V GS = V. 5 5 5 5 75 5 T J, JUNCTION TEMPERTURE ( C) Figure 5. OnResistance Variation with Temperature 5 I DSS, LEKGE (n) V GS = V T J = 5 C T J = 5 C 5 5 5 V DS, DRINTOSOURCE VOLTGE (VOLTS) Figure. DraintoSource Leakage Current versus Voltage
NTDNR, NVDNR TYPICL CHRCTERISTICS C, CPCITNCE (pf) 8 C iss C rss V DS = V V GS = V T J = 5 C C iss C oss C rss 5 V GS V DS 5 5 GTETOSOURCE OR DRINTOSOURCE VOLTGE (VOLTS) Figure 7. Capacitance Variation V GS, GTETOSOURCE VOLTGE (VOLTS) 8 Q Q T V GS I D = 5 T J = 5 C..8... Q g, TOTL GTE CHRGE (nc) Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge Q t, TIME (ns) V DS = V I D = 5 V GS = V t r t d(off) t d(on) t f T J = 5 C....8. R G, GTE RESISTNCE ( ) Figure 9. Resistive Switching Time Variation versus Gate Resistance I S, SOURCE CURRENT (MPS) 7 5 V GS = V T J = 5 C V SD, SOURCETODRIN VOLTGE (VOLTS) Figure. Diode Forward Voltage versus Current I D, DRIN CURRENT () s s ms ms V < V GS < V Single Pulse. T = 5 C R DS(on) Limit dc Thermal Limit Package Limit.. V DS, DRINTOSOURCE VOLTGE (V) Figure. Maximum Rated Forward Biased Safe Operating rea
NTDNR, NVDNR TYPICL CHRCTERISTICS R(t) ( C/W) D =.5...5... SINGLE PULSE....... t, TIME (s) Figure. Thermal Response ORDERING INFORMTION NTDNRTG Device Package Shipping DPK (PbFree) 5 / Tape & Reel NVDNRTG DPK (PbFree) 5 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. 5
NTDNR, NVDNR PCKGE DIMENSIONS L L b e E b b D B DETIL c.5 (.) M C DPK (SINGLE GUGE) CSE 9C ISSUE D C c H L GUGE PLNE L L DETIL ROTTED 9 CW SOLDERING FOOTPRINT*...58. H..8 C Z SETING PLNE NOTES:. DIMENSIONING ND TOLERNCING PER SME Y.5M, 99.. CONTROLLING DIMENSION: INCHES.. THERML PD CONTOUR OPTIONL WITHIN DI- MENSIONS b, L and Z.. DIMENSIONS D ND E DO NOT INCLUDE MOLD FLSH, PROTRUSIONS, OR BURRS. MOLD FLSH, PROTRUSIONS, OR GTE BURRS SHLL NOT EXCEED. INCHES PER SIDE. 5. DIMENSIONS D ND E RE DETERMINED T THE OUTERMOST EXTREMES OF THE PLSTIC BODY.. DTUMS ND B RE DETERMINED T DTUM PLNE H. INCHES MILLIMETERS DIM MIN MX MIN MX.8.9.8.8..5.. b.5.5..89 b..5.7. b.8.5.57 5. c.8... c.8... D.5.5 5.97. E.5.5.5.7 e.9 BSC.9 BSC H.7. 9.. L.55.7..78 L.8 REF.7 REF L. BSC.5 BSC L.5.5.89.7 L.. Z.55.9 STYLE : PIN. GTE. DRIN. SOURCE. DRIN 5.8.8...7. SCLE : mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
NTDNR, NVDNR PCKGE DIMENSIONS IPK CSE 9D ISSUE C V B R C E NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y.5M, 98.. CONTROLLING DIMENSION: INCH. S T SETING PLNE F G K D PL J. (.5) M T H Z INCHES MILLIMETERS DIM MIN MX MIN MX.5.5 5.97.5 B.5.5.5.7 C.8.9.9.8 D.7.5.9.88 E.8...58 F.7.5.9. G.9 BSC.9 BSC H...87. J.8...58 K.5.8 8.89 9.5 R.8.5.5 5.5 S.5... V.5.5.89.7 Z.55.9 STYLE : PIN. GTE. DRIN. SOURCE. DRIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5, Denver, Colorado 87 US Phone: 7575 or 88 Toll Free US/Canada Fax: 757 or 887 Toll Free US/Canada Email: orderlit@onsemi.com N. merican Technical Support: 889855 Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: 85875 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTDNR/D