Scaling up Chemical Vapor Deposition Graphene to 300 mm Si substrates

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Scaling up Chemical Vapor Deposition Graphene to 300 mm Si substrates

Co- Authors Aixtron Alex Jouvray Simon Buttress Gavin Dodge Ken Teo The work shown here has received partial funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement n FP7-285275

Overview of presentation Aixtron overview Scaling up production of monolayer graphene: 2 to 12 substrates Graphene application: FET on 4 graphene wafer

Aixtron Overview 30yrs / >2500 systems in ALD, AVD, CVD, MOCVD, PECVD, OVPD 776 employees worldwide at end of 2013

Silicon Inorganic Thin films Compound Organic Thin films Aixtron Products OVPD PRODOS PVPD BM Line OLED Displays, OLED Lighting, OPV, OTFTs, polymer thinfilms, Parylene, hydrophobic coatings,. CNT, graphene & 2D films Silicon MOCVD Planetary Reactor MOCVD Close Coupled Showerhead III-V Compound Semiconductors, Power Electronics MOCVD Hotwall Reactor SiC thinfilms QXP-8300 ALD Next Generation ALD Product For Dielectric, Metal and NVM Films

Monolayer Graphene 2-Dimensional properties: High tensile strength of 1TPa Low electrical resistance 10-6 Wcm Thermal conductivity > 3000 W/mK Extremely large current density ~ 10 9 A/cm 2 At the nanoscale (5nm ribbons): Semiconducting Very high mobility (10 3-10 5 m 2 /Vs) Transparent sheets (1-4 layers) Single large graphene flake ~0.5mm

Scaling up: 2-inch to 12-inch 1in to 2in coupons/ wafers 4 6 wafer 12 wafer R&D tool: 2-inch R&D tool: 4-inch/6-inch Production tool: 8-inch/ 12-inch

Features for all Aixtron BM reactors Showerhead - uniform gas distribution Top heater Plasma Temperature control Substrate Pressure control Sub-heater

Monolayer graphene on 4 / 6 6-inch wafer Raman line scan 2D D region G Typical Raman spectrum from 6 inch wafer

Raman mapping on 6 wafer High quality monolayer graphene is achieved over full area of 6 inch wafers In collaboration with UT Austin group of Akinwande and Tao

Scaling up key challenges and fixes Flow uniformity: CFD modelling used design showerhead Heat uniformity: Thermal modelling Multi-zone heater to balance heaters Susceptor design

12 Wafer processing time Cycle time: 26 mins

BM300T Raman on 12 wafer 2D D G Average: 2.57 σ: 0.24

Raman mapping on 12 wafer High quality monolayer graphene is achieved over full area of 12 inch wafers

Application - GFET on 4 wafer 1. CVD Graphene growth on Cu/SiO2/Si wafer 2. Graphene transfer to target substrate SiO2/Si wafer 3. UV photolithography of 26,000 back gated FET 4. Statistical analysis of 550 GFET Work accepted for publication in ACS Nano: Towards 300mm Wafer-Scalable High-Performance Polycrystalline Chemical Vapor Deposited Graphene Transistors, S Rahimi, L Tao, Sk. F Chowdhury, S Park, A Jouvray, S Buttress, N Rupesinghe, K Teo, and D Akinwande

Application - GFET on 4 wafer Step 1 Graphene growth Top surface Si Wafer Typical Wafer Section: 0.5µm Cu on 1µm SiO2 In collaboration with UT Austin group of Akinwande and Tao

Application - GFET on 4 wafer Step 2 / 3 - Transfer & GFET fabrication PMMA/Graphene/Cu Mixed etching DIW Rinse & Dry Graphene patterning Graphene Channel UV photolithography of 26,000 GFET on 100mm wafer In collaboration with UT Austin group of Akinwande and Tao

Application - GFET on 4 wafer Step 4 Results pt1 550 randomly chosen GFET were used for statistical testing Results show: Device yield of 74% a) Average value of the fieldeffect mobility 1 : 2113 cm 2 /V.s 5% of GFETs have field effect mobility above 10,000 cm 2 /V.s b) Average Dirac voltage of 6.2V In collaboration with UT Austin group of Akinwande and Tao

Application - GFET on 4 wafer Step 4 Results Pt2 Results continued: c) Average contact resistance of 2116 Ω.µm comparable to e- beam lithography process d) Average sheet resistance 2600 Ω/sq CMOS-compatible GFET fabrication process enabled Process ready for further scaling up In collaboration with UT Austin group of Akinwande and Tao

Conclusions High quality and uniformity monolayer graphene growth scaled up from 2 to 12 wafers on Aixtron tools Process for producing high yield, high performance Graphene FET devices on 4 wafer developed CMOS-compatible GFET fabrication process enabled and ready to apply to 12 graphene wafers

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