FYSE42 IGITAL ELECTRONICS Lecture 4 [] [2] [3] IGITAL LOGIC CIRCUIT ANALYSIS & ESIGN Nelson, Nagle, Irvin, Carrol ISBN -3-463894-8 IGITAL ESIGN Morris Mano Fourth edition ISBN -3-98924-3 igital esign Principles and Practices Fourth edition Wakerly John F. ISBN -3-86389-4 2
Synchronous Sequential Mealy Model of Finite State Machine (FSM) Block diagram of Mealy type state machine Inputs Net State Eitation equations State Registers Output Outputs Asynchronous outputs Typically flip-flops are used by synthesis tools. Output is a function of both the present state and the input. 3 Synchronous Sequential Mealy Model of Finite State Machine (FSM) Analysis Inputs Net State State Registers Output Outputs Circuit diagram A + B A Present states A( B( Present input ( Net states A(t+) B(t+) Present output y( t t+ t AB AB y Eitation functions Mealy FSM A ( A + B) B y 4
Synchronous Sequential Mealy Model of Finite State Machine (FSM) Analysis Present input/present output Present state (/y( (/y( A(B( A(t+)B(t+) Net state State after the clock cycle State diagram 5 Synchronous Sequential Mealy Model of Finite State Machine (FSM) Analysis t t+ t AB AB y Present input/present output Present state (/y( (/y( Net state A(B( A(t+)B(t+) State after the clock cycle / / / / / / / / Mealy FSM State diagram of Mealy FSM 6
Synchronous Sequential Mealy Model of Finite State Machine (FSM) / / / / / / / / State diagram of Mealy FSM t t+ t AB AB y Mealy FSM AB AB AB Net A Net B Output y K-maps for A, B and output y A ( t + ) = B( ( + A( ( B ( t + ) = A( ( y ( = A( ( + B( ( 7 Synchronous Sequential Moore Model of Finite State Machine Block diagram of Moore type state machine Inputs Net State Eitation equations State Registers Output Outputs Asynchronous outputs Typically flip-flops are used by synthesis tools. Output is only a function of the present state. 8
Synchronous Sequential Moore Model of Finite State Machine Analysis Circuit diagram Output y depens only on the present state AB Input B T A t t+ t AB AB y Eitation functions AB T B y Output 9 Synchronous Sequential Moore Model of Finite State Machine Analysis t t+ t = Present Input Net state AB AB y State/Output / / / / State diagram
Synchronous Sequential Moore Model of Finite State Machine = / / / / t t+ t AB AB y State diagram Synchronous Sequential Moore Model of Finite State Machine t t+ t AB AB y AB ( t + ) = T( + T ( T A = B AB AB T B = y = AB Charasteristic equation of the T Flip-Flop K-maps T A = B T B = y = AB 2
Synchronous Sequential Registered-Output Finite State Machine Typically flip-flops are used by synthesis tools. Inputs Net State Eitation equations State Registers Net output Synchronous outputs Output Registers Reset Output is a function of net output logic. 3 Synchronous Sequential Registered-Output Finite State Machine Present Input Present State/Output y( / To Net State Net Output Y(t+) S/ = S4/ S/ S3/ S2/ / S4 / / S3 / S/_ / Use Flip-Flop eitation tables / / =/ S/_ S2 / State reduction State assignment / State diagram Registered-Output FSM Implementation K-maps 4
Synchronous Sequential eamples of Registered-output FSM and Circuit detects a sequence of three or more consecutive 's in a string of bits. Assumption : Input is synchronized Registered-output FSM = =/ / S / S / S 3 / S 2 / State diagram of S / / S / / / / S 3 / / S 2 / / State diagram of Registered-output FSM 5 Synchronous Sequential eamples of Registered-output FSM and S = = AB S = = AB S 2 = = AB S 3 = = AB Registered-output FSM t t+ t t t+ t+ AB AB y = S / S / S 3 / S 2 / =/ S / / / S / / S 3 / / / / S 2 / / AB AB Y State Table of State Table of Registered-output FSM 6
Synchronous Sequential eamples of Registered-output FSM and B A B A B A A = A + B = A + Y = AB B B AB Registered-output FSM Y = A K-maps AB A = A + B AB B = A + B K-maps 7 Synchronous Sequential eamples of Registered-output FSM and A A C C B B AB C A C y Asynchronous output C Y Synchronous output Circuit diagram of Circuit diagram of Registered-output FSM 8
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