MC74CT86A Quad 2-Input XOR Gate / CMOS ogic evel Shifter with STT Compatible Inputs The MC74CT86A is an advanced high speed CMOS 2 input Exclusive OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TT type input thresholds and the output has a full 5 CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic level translator from CMOS logic to 5.0 CMOS ogic or from.8 CMOS logic to CMOS ogic while operating at the high voltage power supply. The MC74CT86A input structure provides protection when voltages up to 7 are applied, regardless of the supply voltage. This allows it to be used to interface 5 circuits to 3 circuits. The output structures also provide protection when CC = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. igh Speed: t PD = 4.8 ns (Typ) at CC = 5 ow Power Dissipation: I CC = 2 A (Max) at T A = 25 C TT Compatible Inputs: I = ; I = Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 2 to Operating Range ow Noise: OP = (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300 ma ESD Performance: BM > 2000 ; Machine Model > 200 These Devices are Pb Free and are RoS Compliant 4 EAD SOIC D SUFFIX CASE 75A A 4 EAD TSSOP DT SUFFIX CASE 948G PIN CONNECTION AND MARKING DIAGRAM (Top iew) CC B4 A4 Y4 B3 A3 Y3 4 3 2 0 9 8 2 3 4 5 6 7 A B Y A2 B2 Y2 GND For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. FUNCTION TABE Inputs Output B Y A B A2 B2 A3 B3 A4 B4 OGIC DIAGRAM 2 4 5 9 0 2 3 3 Y 6 Y2 Y = A B 8 Y3 Y4 ORDERING INFORMATION Device Package Shipping MC74CT86ADR2G SOIC 4 (Pb Free) MC74CT86ADTR2G TSSOP 4 (Pb Free) 2500 / Tape & Reel 2500 / Tape & Reel Semiconductor Components Industries, C, 204 November, 204 Rev. 3 Publication Order Number: MC74CT86A/D
MC74CT86A MAXIMUM RATINGS Symbol Parameter alue Unit CC DC Supply oltage 0.5 to + 7.0 in DC Input oltage 0.5 to + 7.0 out DC Output oltage CC = 0 igh or ow State 0.5 to + 7.0 0.5 to CC + 0.5 I IK Input Diode Current 20 ma I OK Output Diode Current ( OUT < GND; OUT > CC ) ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, CC and GND Pins ± 50 ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package 500 450 mw This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. T stg Storage Temperature 65 to + 50 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit DC Supply oltage CC DC Input oltage IN 0.0 DC Output oltage CC = 0 igh or ow State OUT 0.0 0.0 CC Operating Temperature Range T A 55 +85 C Input Rise and Fall Time CC = 3.3 ± 0.3 CC = 5.0 ± 0.5 t r, t f 0 0 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 00 20 ns/ NOISE CARACTERISTICS (Input t r = t f = ns, C = 50pF, CC = 5.0, Measured in SOIC Package) T A = 25 C Symbol Characteristic Typ Max Unit OP Quiet Output Maximum Dynamic O 0.3 O Quiet Output Minimum Dynamic O 0.3 ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage.5 2
MC74CT86A DC EECTRICA CARACTERISTICS CC T A = 25 C T A 85 C T A 25 C Symbol Parameter Test Conditions () Min Typ Max Min Max Min Max Unit I I O O I IN I CC I CCT I OPD Minimum igh evel Input oltage Maximum ow evel Input oltage Minimum igh evel Output oltage IN = I or I Maximum ow evel Output oltage IN = I or I Maximum Input eakage Current Maximum Quiescent Supply Current Quiescent Supply Current Output eakage Current IN = I or I I O = 50μA IN = I or I I O = 4mA I O = 8mA IN = I or I I O = 50μA IN = I or I I O = 4mA I O = 8mA IN = or GND 0 to.2 2.9 4.4 2.58 3.94 0.0 0.0 0.53 0.36 0.36.2 2.9 4.4 2.48 3.80 0.53 0.44 0.44.2 2.9 4.4 2.34 3.66 0.53 0.52 0.52 ± ±.0 ±.0 μa IN = CC or GND 20 40 μa Input: IN = 3.4.35.50.65 ma OUT = 0.0 0.5 5.0 0 μa Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC EECTRICA CARACTERISTICS (Input t r = t f = ns) Symbol Parameter Test Conditions t P, t P Propagation Delay, A or B to Y CC = 3.3 ± 0.3 C = 5pF C = 50pF T A = 25 C T A = 40 to 85 C Min Typ Max Min Max 7.0 9.5.0.0.0 6.5 Unit ns CC = 5.0 ± 0.5 C = 5pF C = 50pF 4.8 6.3 6.8 8.8.0.0 8.0 0.0 C in Input Capacitance 4 0 0 pf Typical @ 25 C, CC = 5.0 C PD Power Dissipation Capacitance (Note ) 8 pf. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC / 4 (per gate). C PD is used to determine the no load dynamic power consumption; P D = C PD 2 CC f in + I CC CC. TEST POINT A or B 50% t P t P GND DEICE UNDER TEST OUTPUT C * Y 50% CC O O *Includes all probe and jig capacitance Figure. Switching Waveforms Figure 2. Test Circuit 3
MC74CT86A MARKING DIAGRAMS (Top iew) 4 3 2 0 9 8 CT86AG AWYWW* 2 3 4 5 6 7 4 EAD SOIC D SUFFIX CASE 75A 4 3 2 0 9 8 CT 86A AYW 2 3 4 5 6 7 4 EAD TSSOP DT SUFFIX CASE 948G 4 3 2 0 9 8 74CT86A AYWG* 2 3 4 5 6 7 4 EAD SOEIAJ M SUFFIX CASE 965 A = Assembly ocation W, = Wafer ot Y = Year WW, W = Work Week G or = Pb Free Package *See Applications Note #AND8004/D for date code and traceability information. 4
MC74CT86A PACKAGE DIMENSIONS TSSOP 4 CASE 948G ISSUE B 5 (0.006) T 5 (0.006) T 0 (0.004) T SEATING PANE U U S 2X /2 PIN IDENT. S D C 4 4X K REF 0 (0.004) M T U S S N 8 0.25 (0.00) M B U 7 A G N J J F DETAI E K K ÇÇÇ ÉÉÉ SECTION N N DETAI E W NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, 982. 2. CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS, PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXCEED 5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXCESS OF TE K DIMENSION AT MAXIMUM MATERIA CONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MAX MIN MAX A 4.90 5.0 93 0.200 B 4.30 0 69 77 C.20 0.047 D 0.05 5 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J 0.09 6 0.004 0.006 K 9 0.30 0.007 0.02 K 9 0.25 0.007 0.00 6.40 BSC 0.252 BSC M 0 8 0 8 SODERING FOOTPRINT 7.06 0.65 PITC 4X 0.36 4X.26 DIMENSIONS: MIIMETERS 5
MC74CT86A PACKAGE DIMENSIONS T SEATING PANE G A 4 8 D 4 P 7 B K P 7 P C 0.25 (0.00) M T B S A S SOIC 4 D SUFFIX CASE 75A 03 ISSUE J 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, 982. 2. CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 27 (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. MIIMETERS INCES R X 45 F DIM MIN MAX MIN MAX A 8.55 8.75 0.337 0.344 B 3.80 4.00 50 57 C.35.75 0.054 0.068 D 0.35 0.49 0.04 0.09 M J F 0.40.25 0.06 0.049 G.27 BSC 0.050 BSC J 9 0.25 0.008 0.009 K 0 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.228 0.244 SODERING FOOTPRINT R 0.25 0.50 0.00 0.09 4X 0.58 7X 7.04 4X.52.27 PITC DIMENSIONS: MIIMETERS ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, C (SCIC) or its subsidiaries in the United States and/or other countries. SCIC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCIC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: 303 675 275 or 800 344 3860 Toll Free USA/Canada Fax: 303 675 276 or 800 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 790 290 Japan Customer Focus Center Phone: 8 3 587 050 6 ON Semiconductor Website: www.onsemi.com Order iterature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74CT86A/D
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