DATASHEET DG441, DG442 Monolithic, Quad SPST, MOS Analog Switches The DG441 and DG442 monolithic MOS analog switches are drop-in replacements for the popular DG21A and DG22 series devices. They include four independent single pole single throw (SPST) analog switches, TTL and MOS compatible digital inputs, and a voltage reference for logic thresholds. These switches feature lower analog ON resistance (<85 ) and faster switch time (t ON <25ns) compared to the DG21A and DG22. harge injection has been reduced, simplifying sample and hold applications. The improvements in the DG441 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older MOS technologies. The 44V maximum voltage range permits controlling 4V P-P signals. Power supplies may be single ended from +5V to +34V, symmetrical supplies from ±5V to ±22V or asymmetrical supplies limited to a maximum differential voltage of 44V with a V+ max of 34V or a max of -25V. The four switches are bilateral, equally matched for A or bidirectional signals. The ON resistance variation with analog signals is quite low over a 5V analog input range. The switches in the DG441 and DG442 are identical, differing only in the polarity of the selection logic. Pinout DG441, DG442 (16 LD PDIP, SOI, TSSOP) TOP VIEW Features FN3281 Rev 1. ON Resistance (Max)......................... 85 Low Power onsumption (P D )............... <1.6mW Fast Switching Action - t ON (Max)............................... 25ns - t OFF (Max, DG441)........................ 12ns Low harge Injection Upgrade from DG21A, DG22 TTL, MOS ompatible Single or Split Supply Operation Pb-Free Plus Anneal Available (RoHS ompliant) Applications Audio Switching Battery Operated Systems Data Acquisition Hi-Rel Systems Sample and Hold ircuits ommunication Systems Automatic Test Equipment IN 1 D 1 S 1 S 4 D 4 IN 4 1 2 3 4 5 6 7 8 16 IN 2 15 D 2 14 S 2 13 V+ 12 N 11 S 3 1 D 3 9 IN 3 FN3281 Rev 1. Page 1 of 14
Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( ) PAKAGE PKG. DWG. # DG441DJ DG441DJ -4 to +85 16 Ld PDIP E16.3 DG441DJZ (Note) DG441DJZ -4 to +85 16 Ld PDIP* (Pb-free) E16.3 DG441DY DG441DY -4 to +85 16 Ld SOI M16.15 DG441DY-T DG441DY 16 Ld SOI Tape and Reel M16.15 DG441DYZ (Note) DG441DYZ -4 to +85 16 Ld SOI (Pb-free) M16.15 DG441DYZ-T (Note) DG441DYZ 16 Ld SOI Tape and Reel (Pb-free) M16.15 DG441DYZA (Note) DG441DYZ -4 to +85 16 Ld SOI (Pb-free) M16.15 DG441DYZA-T (Note) DG441DYZ 16 Ld SOI Tape and Reel (Pb-free) M16.15 DG441DVZ (Note) DG441DVZ -4 to +85 16 Ld TSSOP (Pb-free) M16.173 DG441DVZ-T (Note) DG441DVZ -4 to +85 16 Ld TSSOP Tape and Reel (Pb-free) M16.173 DG442DJ DG442DJ -4 to +85 16 Ld PDIP E16.3 DG442DJZ (Note) DG442DJZ -4 to +85 16 Ld PDIP* (Pb-free) E16.3 DG442DY DG442DY -4 to +85 16 Ld SOI M16.15 DG442DY-T DG442DY 16 Ld SOI Tape and Reel M16.15 DG442DYZ (Note) DG442DYZ -4 to +85 16 Ld SOI (Pb-free) M16.15 DG442DYZ-T (Note) DG442DYZ 16 Ld SOI Tape and Reel (Pb-free) M16.15 DG442DVZ (Note) DG442DVZ -4 to +85 16 Ld TSSOP (Pb-free) M16.173 DG442DVZ-T (Note) DG442DVZ 16 Ld TSSOP Tape and Reel (Pb-free) M16.173 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-2. Functional Diagrams DG441 DG442 S 1 S 1 IN 1 IN 1 D 1 S 2 D 1 S 2 IN 2 IN 2 D 2 S 3 D 2 S 3 IN 3 IN 3 D 3 S 4 D 3 S 4 IN 4 IN 4 D 4 D 4 SWITHES SHOWN FOR LOGI 1 INPUT TRUTH TABLE LOGI V IN DG441 DG442.8V ON OFF 1 2.4V OFF ON FN3281 Rev 1. Page 2 of 14
Schematic Diagram (One hannel) V+ S IN X V+ D 1 PER DIE OMMON TO EVERY HANNEL Pin Descriptions PIN SYMBOL DESRIPTION 1 IN 1 Logic ontrol for Switch 1 2 D 1 Drain (Output) Terminal for Switch 1 3 S 1 Source (Input) Terminal for Switch 1 4 Negative Power Supply Terminal 5 Ground Terminal (Logic ommon) 6 S 4 Source (Input) Terminal for Switch 4 7 D 4 Drain (Output) Terminal for Switch 4 8 IN 4 Logic ontrol for Switch 4 9 IN 3 Logic ontrol for Switch 3 1 D 3 Drain (Output) Terminal for Switch 3 11 S 3 Source (Input) Terminal for Switch 3 12 N No Internal onnection 13 V+ Positive Power Supply Terminal (Substrate) 14 S 2 Source (Input) Terminal for Switch 2 15 D 2 Drain (Output) Terminal for Switch 2 16 IN 2 Logic ontrol for Switch 2 FN3281 Rev 1. Page 3 of 14
Absolute Maximum Ratings V+ to.......................................... 44.V to.......................................... -25V to V+.........................................+34V Digital Inputs, V S, V D (Note 1)........ () -2V to (V+) + 2V or 3mA, Whichever Occurs First ontinuous urrent (Any Terminal)..................... 3mA Peak urrent, S or D (Pulsed 1ms, 1% Duty ycle Max).. 1mA Operating onditions Temperature Range..........................-4 to +85 Signal Voltage Range 2V (Max) Input Low Voltage...............................8V (Max) Input High Voltage.............................. 2.4V (Min) Input Rise and Fall Time 2ns Thermal Information Thermal Resistance (Typical, Note 2) JA ( /W) PDIP Package*............................ 9 SOI Package............................. 115 TSSOP Package........................... 15 Maximum Junction Temperature (Plastic Packages)...... +15 Maximum Storage Temperature Range..........-65 to +15 Maximum Lead Temperature (Soldering 1s)........... +3 (SOI and TSSOP- Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on S X, D X or IN X exceeding V+ or will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Dual Supply) Test onditions: V+ = +15V, = -15V, V IN = 2.4V,.8V, V ANALOG = V S, V D, Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) MIN (NOTE 3) TYP MAX UNITS DYNAMI HARATERISTIS Turn-ON Time, t ON R L = 1k, L = 35pF, V S = 1V, (Figure 1) +25-15 25 ns Turn-OFF Time, t OFF DG441 +25-9 12 ns DG442-11 21 ns harge Injection, Q (Figure 2) L = 1nF, V G = V, R G = +25 - -1 - p OFF Isolation (Figure 4) R L = 5, L = 5pF, f = 1MHz +25-6 - db rosstalk (hannel-to-hannel) (Figure 3) +25 - -1 - db Source OFF apacitance, S(OFF) f = 1MHz, V ANALOG = (Figure 5) +25-4 - pf Drain OFF apacitance, D(OFF) +25-4 - pf hannel ON apacitance, D(ON) + S(ON) +25-16 - pf DIGITAL INPUT HARATERISTIS Input urrent V IN Low, I IL V IN Under Test =.8V, All Others = 2.4V Full -.5 -.1.5 A Input urrent V IN High, I IH V IN Under Test = 2.4V, All Others =.8V Full -.5.1.5 A ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full -15-15 V Drain-Source ON Resistance, r DS(ON ) I S = 1mA, V D = 8.5V, V+ = 13.5V, +25-5 85 = -13.5V +85 - - 1 Source OFF Leakage urrent, I S(OFF) V+ = 16.5V, = -16.5V, V D = 15.5V, +25 -.5.1.5 na V S = 15.5V +85-5 - 5 na Drain OFF Leakage urrent, I D(OFF) +25 -.5.1.5 na +85-5 - 5 na hannel ON Leakage urrent, V+ = 16.5V, = -16.5V, V S = V D = 15.5V +25 -.5.8.5 na I D(ON) +I S(ON) +85-1 - 1 na FN3281 Rev 1. Page 4 of 14
Electrical Specifications (Dual Supply) Test onditions: V+ = +15V, = -15V, V IN = 2.4V,.8V, V ANALOG = V S, V D, Unless Otherwise Specified (ontinued) PARAMETER TEST ONDITIONS POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ V+ = 16.5V, = -16.5V, V IN = V or 5V Full - 15 1 A Negative Supply urrent, I- +25-1 -.1 - A Full -5 - - A Ground urrent, I Full -1-15 - A TEMP ( ) MIN (NOTE 3) TYP MAX UNITS Electrical Specifications (Single Supply) Test onditions: V+ = 12V, = V, V IN = 2.4V,.8V, Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) MIN (NOTE 3) TYP MAX UNITS DYNAMI HARATERISTIS Turn-ON Time, t ON R L = 1k, L = 35pF, V S = 8V, (Figure 1) +25-3 45 ns Turn-OFF Time, t OFF +25-6 2 ns harge Injection, Q (Figure 2) L = 1nF, V G = 6V, R G = +25-2 - p ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full - 12 V Drain-Source ON Resistance, I S = 1mA, V D = 3V, 8V V+ = 1.8V +25-1 16 r DS(ON) Full - - 2 POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ V+ = 13.2V, = V, V IN = V or 5V Full - 15 1 A Negative Supply urrent, I- +25-1 -.1 - A Full -1 -.1 - A Ground urrent, I Full -1-15 - A NOTES: 3. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested. FN3281 Rev 1. Page 5 of 14
Test ircuits and Waveforms V O is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. LOGI INPUT 3V V 5% t r < 2ns t f < 2ns SWITH INPUT S 1 V+ D 1 V O t OFF IN 1 SWITH INPUT SWITH OUTPUT V S V V O 8% 8% LOGI INPUT 3V t ON Repeat test for hannels 2, 3 and 4. For load conditions, see Specifications. L includes fixture and stray capacitance. R L NOTE: Logic input waveform is inverted for switches that have the V O = V S ----------------------------------- R L + r DS ON opposite logic sense. FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST IRUIT FIGURE 1. SWITHING TIMES V+ R L L SWITH OUTPUT V O R G D 1 V O IN X OFF ON (DG441) OFF V G L IN X ON (DG442) OFF Q = V O x L OFF FIGURE 2A. MEASUREMENT POINTS FIGURE 2. HARGE INJETION V IN = 3V FIGURE 2B. TEST IRUIT V+ +15V V+ +15V SIGNAL GENERATOR 1dBm V S V D 5 SIGNAL GENERATOR 1dBm V S V, 2.4V IN 1 IN 2 V, 2.4V IN X V, 2.4V ANALYZER V D N ANALYZER V D R L R L -15V -15V FIGURE 3. ROSSTALK TEST IRUIT FIGURE 4. OFF ISOLATION TEST IRUIT FN3281 Rev 1. Page 6 of 14
Test ircuits and Waveforms (ontinued) V+ +15V V S IMPEDANE ANALYZER IN X V, 2.4V V D f = 1MHz -15V FIGURE 5. SOURE/DRAIN APAITANES TEST IRUIT Application Information GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANE. OP AMP OFFSET AND MRR WILL LIMIT AURAY OF IRUIT. V IN FET INPUT OP AMP +15V 13 +15V -15V 7 4 6 3 2 V OUT 2 3 GAIN 1 A V = 1 GAIN 2 A V = 1 GAIN 3 A V = 2 1 15 16 1 9 7 14 11 6 R 1 9k R 2 5k R 3 4k V IN + - +15V 1/4 DG442 S X D X H + - V OUT GAIN 4 A V = 1 8 R 4 1k IN X -15V 4-15V 5 1 = SAMPLE = HOLD V --------------- OUT V IN R 1 + R 2 + R 3 + R 4 = ------------------------------------------------ = 1 with SW R 4 closed 4 FIGURE 6. PREISION WEIGHTED RESISTOR PROGRAMMABLE GAIN AMPLIFIER FIGURE 7. OPEN LOOP SAMPLE AND HOLD FN3281 Rev 1. Page 7 of 14
Typical Performance urves r DS(ON) ( ) 1 8 6 4 5V 8V 1V 12V 15V r DS(ON) ( ) 8 7 6 5 4 3 +125 +85 +25 V+ = +15V = -15V 2 2V 2 1-4 -55-2 2 V D (V) FIGURE 8. r DS(ON) vs V D AND POWER SUPPLY VOLTAGE -15 15 V D (V) FIGURE 9. r DS(ON) vs V D AND TEMPERATURE 14 12 1 +125 +85 V+ = +12V = V 3 25 2 V+ = +5V = V r DS(ON) ( ) 8 6 +25 r DS(ON) ( ) 15 +8V 4 2-4 -55 1 5 +1V +12V +15V +2V 6 12 V D (V) 1 2 V D (V) FIGURE 1. r DS(ON) vs V D AND TEMPERATURE (SINGLE 12V SUPPLY) FIGURE 11. r DS(ON) vs V D AND SINGLE SUPPLY VOLTAGE 1 5 1 5 I IN (pa) 1 4 1 3 1 2 1 1 I+, I-, I (na) 1 4 1 3 1 2 1 1.1.1 I+, I -(I-).1-55 5 1 125 TEMPERATURE ( ) FIGURE 12. INPUT URRENT vs TEMPERATURE.1-55 5 1 125 TEMPERATURE ( ) FIGURE 13. SUPPLY URRENT vs TEMPERATURE FN3281 Rev 1. Page 8 of 14
Typical Performance urves (ontinued) 14 12 1 ROSSTALK 5 4 3 V+ = +15V = -15V SINGLE SUPPLY V+ = +12V = V (-db) 8 6 4 2 V+ = +15V = -15V P GEN = 1dBm OFF ISOLATION 1 1k 1k 1k 1M 1M FREQUENY (Hz) Q (p) 2 1-1 -2 L = 1nF L = 1nF L = 1nF L = 1nF -3-1 -5 5 1 V S (V) FIGURE 14. ROSSTALK AND OFF ISOLATION vs FREQUENY FIGURE 15. HARGE INJETION vs SOURE VOLTAGE 16 14 V+ = +15V = -15V t ON (DG441) 16 14 t ON 12 12 t ON, t OFF (ns) 1 8 6 t ON (DG442) t OFF (DG442) t ON, t OFF (ns) 1 8 6 t OFF 4 t OFF (DG441) 4 2 2 3 4 5 V IN (V) FIGURE 16. SWITHING TIMES vs INPUT VOLTAGE 2 1 12 14 16 18 2 22 SUPPLY VOLTAGE ( V) FIGURE 17. SWITHING TIME vs POWER SUPPLY VOLTAGE (DG441) 2 2.4 I S(OFF), I D(OFF) -2 1.6 I S, I D (pa) -4 I S(ON) + I D(ON) V IN (V) -6.8-8 V+ = +15V = -15V FOR I (OFF), V D = -V S -1-15 -1-5 5 1 15 V S, V D (V) FIGURE 18. LEAKAGE URRENT vs ANALOG VOLTAGE 5 1 15 2 SUPPLY VOLTAGE ( V) FIGURE 19. SWITHING THRESHOLD vs SUPPLY VOLTAGE FN3281 Rev 1. Page 9 of 14
Typical Performance urves (ontinued) 25 V+ = +15V = -15V 2 V+ = +12V = V 2 15 S(ON) + D(ON) S(ON) + D(ON) S, D (pf) 15 1 S, D (pf) 1 5 S(OFF), D(OFF) 5 S(OFF), D(OFF) -15-1 -5 5 1 15 V A (V) FIGURE 2. SOURE/DRAIN APAITANE vs ANALOG VOLTAGE 6 12 V A (V) FIGURE 21. SOURE/DRAIN APAITANE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY) 1 I S(OFF), I D(OFF) 4 3 V+ = +12V = V t ON (DG441) t ON (DG442) I S, I D (pa) -1-2 t ON, t OFF (ns) 2-3 I S(ON) + I D(ON) V+ = +12V = V FOR I D, V S = FOR I S, V D = -4 6 12 V S, V D (V) FIGURE 22. SOURE/DRAIN LEAKAGE URRENTS (SINGLE 12V SUPPLY) 1 t OFF (DG441) 2 3 4 5 V IN (V) FIGURE 23. SWITHING TIME vs INPUT VOLTAGE (SINGLE 12V SUPPLY) t OFF (DG442) 5 = V 4 t ON, t OFF (ns) 3 2 t ON 1 t OFF 8 1 12 14 16 18 2 22 POSITIVE SUPPLY (V) FIGURE 24. SWITHING TIME vs SINGLE SUPPLY VOLTAGE (DG441) FN3281 Rev 1. Page 1 of 14
Die haracteristics DIE DIMENSIONS: 216 m x 176 m x 485 m METALLIZATION: Type: SiAl Thickness: 12kÅ 1kÅ Metallization Mask Layout DG441, DG442 PASSIVATION: Type: Nitride Thickness: 8kÅ 1kÅ WORST ASE URRENT DENSITY: 9.1 x 1 4 A/cm 2 D 1 (2) IN 1 (1) IN 2 (16) (15) D 2 S 1 (3) (14) S 2 (4) (13) V+ SUBSTRATE (5) (12) N S 4 (6) (11) S 3 (7) (8) (9) (1) D 4 IN 4 IN 3 D 3 FN3281 Rev 1. Page 11 of 14
Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D1 B1 -- -A- N 1 2 3 N/2 B D e D1 E1 NOTES: 1. ontrolling Dimensions: INH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DE seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum --. 7. e B and e are measured at the lead tips with the leads unconstrained. e must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed.1 inch (.25mm). 9. N is the maximum number of terminal positions. 1. orner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of.3 -.45 inch (.76-1.14mm). -B- A1.1 (.25) M A A2 L B S A e E L e A e B E16.3 (JEDE MS-1-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -.21-5.33 4 A1.15 -.39-4 A2.115.195 2.93 4.95 - B.14.22.356.558 - B1.45.7 1.15 1.77 8, 1.8.14.24.355 - D.735.775 18.66 19.68 5 D1.5 -.13-5 E.3.325 7.62 8.25 6 E1.24.28 6.1 7.11 5 e.1 BS 2.54 BS - e A.3 BS 7.62 BS 6 e B -.43-1.92 7 L.115.15 2.93 3.81 4 N 16 16 9 Rev. 12/93 FN3281 Rev 1. Page 12 of 14
Small Outline Plastic Packages (SOI) N INDEX AREA 1 2 3 e D B.25(.1) M A M E -B- -A- -- SEATING PLANE A B S H.25(.1) M B A1.1(.4) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.14 inch) or greater above the seating plane, shall not exceed a maximum value of.61mm (.24 inch). 1. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. L M h x 45 M16.15 (JEDE MS-12-A ISSUE ) 16 LEAD NARROW BODY SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.532.688 1.35 1.75 - A1.4.98.1.25 - B.13.2.33.51 9.75.98.19.25 - D.3859.3937 9.8 1. 3 E.1497.1574 3.8 4. 4 e.5 BS 1.27 BS - H.2284.244 5.8 6.2 - h.99.196.25.5 5 L.16.5.4 1.27 6 N 16 16 7 8 8 - Rev. 1 6/5 FN3281 Rev 1. Page 13 of 14
Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA 1 2 3.5(.2) e D.1(.4) M A M E1 -B- -Ab -- SEATING PLANE A B S E.25(.1) M B A1 NOTES: 1. These package dimensions are within allowable dimensions of JEDE MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.15mm (.6 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch). 1. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. (Angles in degrees) GAUGE PLANE.1(.4).25.1 A2 M L c M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -.43-1.1 - A1.2.6.5.15 - A2.33.37.85.95 - b.75.12.19.3 9 c.35.8.9.2 - D.193.21 4.9 5.1 3 E1.169.177 4.3 4.5 4 e.26 BS.65 BS - E.246.256 6.25 6.5 - L.2.28.5.7 6 N 16 16 7 o 8 o o 8 o - Rev. 1 2/2 opyright Intersil Americas LL 1999-26. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see www.intersil.com FN3281 Rev 1. Page 14 of 14