Ultimately Scaled CMOS: DG FinFETs? Jerry G. Fossum SOI Group Department of Electrical and Computer Engineering University of Florida Gainesville, FL 32611-6130 J. G. Fossum / 1
Outline Introduction - CMOS Scaling Thin-BOX FD/SOI MOSFETs Pragmatic Nanoscale FinFETs Conclusions J. G. Fossum / 2
Projected HP CMOS Gate-Length Scaling* [Intel: bulk-si MOSFETs] 7nm [6nm in 2020!] *2003 SIA ITRS J. G. Fossum / 3
Contemporary Bulk-Silicon MOSFET N B (x,y) Substrate/Well Body Has been scaled a la Moore s (and now, More than Moore ) Law, but with increasingly complex boosters and body/channel doping density N B, which can no longer (i.e., for L g < ~30nm) be adequately controlled. J. G. Fossum / 4
Continued Scaling to L g < 10nm: Undoped UTBs/Channels FD/SOI (n)mosfet w/ thin BOX and GP? (n)finfet on SOI? STI Gf n + BOX STI p - p + GP n + Gate Si Substrate NO. Complex processing/layout. Selective GPs, w/ biasing. Tuned dual-metal gate work functions. High inherent V t : V tlong ( ) = ( 1 + r)φ c 0.6V. n+ n+ Source Drain YES. Quasi-planar. Conventional processing, w/o N B. Two gates: good SCE control. Can be pragmatic. BOX J. G. Fossum / 5
2-D Numerical Simulations: Projected Scaling Limits Taurus-predicted LP and HP scaling limits (L eff, which, with G-S/D underlap, can be 5-10nm longer than L g ), defined by t Si = 5nm, for thin-box/gp nmosfets and DG nfinfets. The devices have been designed for I off ~ 10pA/µm and ~100nA/µm for LP and HP applications, respectively, with DIBL 100mV/V. The 18nm limit for the HP thin-box/gp device with V GP is questionable due to the very large Φ Gf (gate work-function tuning below midgap) needed; the scaling limit of 25nm without V GP is more realistic. Thin-BOX/GP Thin-BOX/GP LP DG FinFET w/o V GP w/ V GP L eff (nm) 28 18 25/15 Φ Gf (mv) 0 450 0/-450 Thin-BOX/GP Thin-BOX/GP HP DG FinFET w/o V GP w/ V GP L eff (nm) 25 18? 15 Φ Gf (mv) 0 850 0 Pragmatic FinFET-CMOS can be scaled to the end of the SIA ITRS. J. G. Fossum / 6
Nanoscale Pragmatic-FinFET CMOS On SOI (no isolation, S-D leakage complexities). Undoped fin-utb/channel (no RDF effects). DG, not TG (a top gate is virtually ineffective). One ~midgap metal gate (for nmos and pmos). No channel strain (mobilities are high without it). No high-k dielectric (relatively thick SiON is OK). G-S/D underlap (L eff(weak) > L g, L eff(strong) L g ). S/D processing for V t control (and underlap). J. G. Fossum / 7
The optimal number of gates is 2! Davinci (3-D): Undoped L eff = 28nm TG fin size for SCE control; t ox = 1.1nm 2.0 1.5 S = 80mV DIBL = 100mV/V h Si /L eff 1.0 DG h Si = w Si = L eff h Si = w Si ( easier fin) 1/5 ~ h Si(FD) /L eff 0.5 0.0 Design Space FD/SOI 0.0 0.5 1.0 1.5 2.0 w Si /L eff w Si(DG) /L eff ~ 1/2 Two gates (DG) give good control of electrostatics (i.e., SCEs) with thicker UTB than that needed for one-gate (FD/SOI) device. J. G. Fossum / 8
A third (top) gate is not very beneficial... 60 Davinci (w/o QM): L eff = 25nm, w Si = 13nm, t ox = 1.2nm 100 50 TG FinFET DG FinFET 80 I DS (µa) 40 30 20 10 R f h Si /w Si = 3 V DS =1.0V I on /I on(dg) (%) 60 40 20 W eff -implied [w Si /(2h Si )] 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V GS (V) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 R f (Note that the effective width (per fin) W eff =2h Si +w Si is not appropriate.) J. G. Fossum / 9
... due to strong bulk inversion in the undoped fin-utb/channel. n (cm -3 ) 10 19 DG FinFET TG FinFET DG FinFET w/o top gate stack R f = 39nm/13nm = 3 Gate SiO 2 z 10 18 V GS =V DS =1.0V 0 5 10 15 20 25 30 35 z (nm) Buried SiO 2 Si Substrate The predicted electron density in the bulk of the undoped fin-utb shows substantial (strong) inversion, irrespective of the top-surface condition. Activating the third gate is not beneficial nor practical. J. G. Fossum / 10
The bulk inversion also underlies the use of thick SiON. * Bulk (a.k.a. volume) inversion is not good, but is unavoidable. * For strong inversion, it reduces the effective gate capacitance C G : Q i = 2 C ox ---------------------- ( ε 1 ox x V V ) GS t + ------------- i ε Si t ox (via integration of Poisson s equation) where x i is the average depth(s) of the inversion carriers, which is increased by bulk inversion. The deeper x i reflects lower inversion-layer capacitance, and yields lower C G and Q i. * The quantization effect further increases x i and reduces C G. * Because of the deeper x i, increasing t ox is not so detrimental to C G (which is less than C ox = ε ox /t ox ), and hence to Q i and current. * Further, the thicker SiON (t ox ) reduces the parasitic G-S/D (fringe) capacitance, which improves speed performance significantly. J. G. Fossum / 11
The underlap is effected by engineering of the lateral doping-density profile in the S/D fin-extension. N SD (y) [cm -3 ] 10 21 10 20 10 19 10 18 10 17 10 16 10 15 10 14 10 13 10 12 10 11 10 10 L ext L g L ext 1nm 10nm 15nm σ L =5nm L eff(weak) 20 30 40 50 60 70 80 90 100 y [nm] L eff(strong) L g N SD ( y) 10 20 exp ------ y 2 σ L [nm] DIBL [mv/v] σ L Medici: L g =18nm, L ext =30nm, w Si =12nm S [mv] 1 (abrupt) 180 94 5 35 62 10 46 66 15 79 71 Straggle defines L eff(weak) > L g. Optimal straggle and extension length define best SCE (I off ) vs. R S/D (I on ) tradeoff; further, V t can be adjusted for different applications via controlled S/D dopants in channel, with reasonable sensitivity to process variations. J. G. Fossum / 12
Very high mobilities can be achieved in undoped FinFETs. Low transverse electric field ( Q i /2) yields high carrier mobilities: µ n(eff) [cm 2 /V-s] 450.0 400.0 350.0 300.0 250.0 200.0 150.0 nmosfets electron mobilities x2 100.0 0.5 1.0 1.5 2.0 N inv [10 13 cm -2 ] UFDG calibrations to long-l g FinFETs µ 0 = 565cm 2 /V-s θ = 0.20 (w Si = 26nm) {110} DG nfinfet - UFDG {100} DG nmosfet - measured {100} bulk nmosfet - measured µ p(eff) [cm 2 /V-s] 250.0 200.0 150.0 100.0 50.0 pmosfets hole mobilities 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 N inv [10 13 cm -2 ] {110} DG pfinfet - UFDG {110} DG pfinfet - measured {100} DG pmosfet - measured {100} bulk pmosfet - measured {110} bulk pmosfet - measured (low N B ) x3 µ 0 = 250cm 2 /V-s θ = 0.10 (w Si = 30nm) J. G. Fossum / 13
But... UFDG calibrations to nfinfets with varying L g 330 L g =1µm: UO=585, Θ=0.32 L g =75nm: UO=400, Θ=0.2 L g =32nm: UO=125, Θ=0.2 280 µ n(eff) (cm 2 /V-s) 230 180 130 80 5.0e+12 1.0e+13 1.5e+13 2.0e+13 2.5e+13 N inv (cm -2 ) Scaling L g degrades µ eff, which implies excessive scattering centers near the source/drain, or perhaps significant remote S/D Coulomb scattering. Recent work suggests that this problem can be resolved via optimal S/D engineering. J. G. Fossum / 14
UFDG/Spice3: Pragmatic nanoscale DG-FinFET CMOS can give good speed performance (with very low I off ). 8.0 7.0 L g = 18nm DG CMOS unloaded RO delays Abrupt N SD (y) w/ G-S/D overlap (0.1L g ) G-S/D underlap (3.4nm); t ox = 1.0nm G-S/D underlap (3.4nm); t ox = 1.5nm Delay/Stage [ps] 6.0 5.0 4.0 3.0 2.0 0.7 0.8 0.9 1.0 1.1 V DD [V] 32% speed improvement with pragmatic FinFET design* *The underlap and the thicker t ox reduce the parasitic G-S/D fringe capacitance, which is very significant in nanoscale CMOS devices. J. G. Fossum / 15
Conclusions Pragmatic nanoscale DG-FinFET CMOS is viable, and is potentially scalable to the end of the SIA ITRS (where L g < 10nm). Source/drain engineering for G-S/D underlap, V t adjustment, and high carrier mobilities must be optimized; and tall, thin fins must be controlled. Further, SOI enables embedded FBC (e.g., 1T) DRAM, which can be viable. J. G. Fossum / 16
UFDG: A Process/Physics-Based Predictive Compact Model Applicable to Generic UTB DG MOSFETs W g Gf S Φ Gf n + L p n + eff t Si D Gf = Gb Gb Φ Gb UFDG is applicable to SG FD/ SOI MOSFETs, as well as symmetrical-, asymmetrical-, and independent-gate DG MOSFETs, including FinFETs. W g = h Si n+ Source L g t Si = w Si Gate n+ Drain J. G. Fossum / 17
Short-Channel Effects Modeling in UFDG (or, how two gates give good control of the electrostatics) 2-D Poisson equation (for weak inversion), y Gf 2 φ -------- x 2 2 φ + -------- y qn B ---------- is solved in (rectangular) body/channel (UTB) region, defined by t Si and L eff L g, by assuming ε Si, x S Φ Gf UTB t oxf t Si L eff D φ( x, y) α 0 ( y) + α 1 ( y)x + α 2 ( y)x 2 Φ Gb t oxb in Poisson, and applying the (four) boundary conditions (including surface-state charge at both interfaces). The derived potential (with QM shift) defines the integrated (in x-y, over t Si ) inversion charge (Q i ) and an effective channel length (L e < L eff averaged over t Si ) for predominant diffusion current (in y), and thus accounts for: Gb * S/D charge (impurity and/or carrier) sharing [V t (L eff ) & S(L eff )], * DIBL (throughout UTB) [ V t (V DS )]. J. G. Fossum / 18
Quantization Effects Modeling in UFDG UFDG is actually a compact Poisson-Schrödinger solver: Classical PE (charge coupling, inversion-charge distribution) potentials, electric fields (classical Q i & I ch ) SWE (eigenfunctions, eigenvalues, 2-D DOS, F-D) updated potentials, electric fields in UTB/channel QM Q i & I ch Eigenfunction Ψ 0 (10 4 m -1/2 ) 2.0 1.5 1.0 0.5 0.0 Model SCHRED t Si = 20nm 0.6V 1.0V V GS = 1.5V SDG n + nmosfets: poly gates t ox =1.5nm N B =10 17 cm -3 1.5V t Si = 5nm 0.0 0.2 0.4 0.6 0.8 1.0 Normalized Position x/t Si 1-D SWE analytical solution is derived using a variational approach, then coupled to PE and Q i (V GfS, V GbS ) via Newton-Raphson iteration, all with dependence on t Si and Si orientation, as well as E x. The QM modeling is also the basis for a physical mobility model for the UTB carrier transport. J. G. Fossum / 19