Switched Capacitor Circuits II Dr. Paul Hasler Georgia Institute of Technology
Basic Switch-Cap Integrator = [n-1] - ( / ) H(jω) = - ( / ) 1 1 - e -jωt ~ - ( / ) / jωt (z) - z -1 1 (z) = H(z) = - ( / ) 1 assumes ωt << 1; therefore we need to sample much higher (factor of 10 to 20) over frequencies of interest.
Switch-Cap Implementation
Switch-Cap Implementation Transistor switches result in: Parasitic capacitances Charge / clock feedthrough
Switch-Cap Implementation Now adding Parasitic capacitors: C p4 C p5 C p2 C p0 C p1 C p3
Switch-Cap Implementation C p4 C p5 C p2 C p0 C p1 C p3 Fortunately, many of these capacitors have minimal effect on the circuit Parasitic capacitances to a voltage source can be neglected Parasitic capacitances to a virtual AC can be neglected (the effect of the capacitance is divided by the open-loop gain)
Switch-Cap Implementation C p1 C p2 We still have parasitic capacitances effecting our result We can either make large to swamp out parasitic capacitors, or use a stray insensitive design
Switch-Cap Integrator V 2 We will step through all four phases, to get the proper result.
Switch-Cap Integrator (4), [n-1] cycle [n-1] Q = - [n-1] Voltage = 0V [n-1] (Voltage remains held) V 2 [n-1] This case is important to understand our starting point charge is stored on a capacitor ; therefore we need to know the initial state
Switch-Cap Integrator (1), cycle: Q = - [n-1] [n-1] (Output unchanged) V 2 Charge up the capacitor with voltage
Switch-Cap Integrator (2), cycle Q 1 = Q = - [n-1] [n-1] (Output unchanged) V 2 Q 1 = - We remove the capacitor from the first voltage. The voltage is stored across the capacitor
Switch-Cap Integrator (3), cycle: Q = - [n-1] + - V 2 [n-1] + ( / ) (V 2 - ) V 2 We connect the capacitor to the charge summing node The charge initially stored on the capacitor as well as the resulting charge from the second input (V 2 ) contributes to the total charge
Switch-Cap Integrator (4), cycle Q = - [n-1] + ( -V 2 ) = [n-1] + ( / ) (V 2 - ) (Output unchanged) V 2 We disconnect the capacitor from the charge summing node, and return to our initial case = [n-1] + ( / ) (V 2 - )
Switch-Cap Integrator C A A V 2 V 2 By switching which input is first, we can digitally invert the signal
Differential Switch-Cap Circuit V in + + - V in - Why?
Differential Switch-Cap Circuit V in + + - V in - Why? Higher PSRR, lower harmonic Distortion, lower noise Cost?
Differential Switch-Cap Circuit V in + + - V in - V in = V in + - V in - = + - - (assume balanced output) Why? Higher PSRR, lower harmonic Distortion, lower noise Cost? Larger Op-Amp, more power
Differential Switch-Cap Circuit (4), [n-1] cycle Voltage = 0V Q = - [n-1]/2 V in + [n-1] + [n-1] - [n-1] V in - [n-1] Q = [n-1]/2 (Voltage remains held) This case is important to understand our starting point charge is stored on a capacitor ; therefore we need to know the initial state
Differential Switch-Cap Circuit (1), cycle: Q = - [n-1]/2 V in + V in + [n-1] - [n-1] V in - (Output unchanged) Q = [n-1]/2 Charge up the capacitor with voltage V in
Differential Switch-Cap Circuit (2), cycle Q 1 = V in Q = - [n-1]/2 V in + V in + [n-1] - [n-1] V in - (Output unchanged) Q 1 = - V in Q = [n-1]/2 We remove the capacitor from the first voltage. The voltage is stored across the capacitor
Differential Switch-Cap Circuit (3), cycle: Q = - [n-1]/2 + V in V in + V in - Q = [n-1]/2 - V in + - = [n-1] + -2( / ) (V in ) We connect the capacitor to the charge summing node
Differential Switch-Cap Circuit (4), cycle V in + ~0 + - V in - (Output unchanged) We disconnect the capacitor from the charge summing node, and return to our initial case = [n-1] 2 ( / ) V in
Stray Insensitive Circuits Discussed issue of stray insensitive circuits Discussed two typically used circuits, one single ended and one differential ended