Oxidation Reading Assignments: Plummer, Chap 6.1~6.4, 6.5.1, 6.5.3, 6.5.4, 6.5.5, 6.5.13 1
Why SiO 2? The extraordinary properties of SiO 2 are the basis of the success of MOS-technology Non-crystalline insulator Very high energy gap Φ M Easy to grow on Si Easy to integrate in a process E M Excellent interface between Si substrate Stable and insensitive to following process-steps Excellent scaling possibilities no real candidates for replacement E 0 1.0eV χ ox 9.0eV 3.0eV 4.9eV Φ S χ si E C E V 2
Properties of SiO 2 Si-Si : 3.12 Å, Si-O: 1.62 Å, O-O: 2.27 Å 10 nm : 40-50 atomic layers 1.2 nm : only about 4 atomic layers Bonding angle : 110~180 ( 144 ) Dielectric constant: 3.9 Energy gap : 9 ev Density : 2.20 g/cm 3 Refractive Index : ~1.462 Dielectric strength 10-15 MV/cm Tetrahedra structure θ Bridging Oxygen Oxygen Silicon 3
Application of Thermal Oxides 4
Transistor Process Flow (1970s) Al Si nmos Cross-section PSG poly n + n + p-si SiN Clean p-si p-si Field Oxidation Oxide Etch p-si p-si Gate Oxidation Poly Dep. p-si poly p-si poly Poly Etch P + Ion Implant p-si poly n + poly p-si n + Annealing 5
Masking Oxide Much lower B and P diffusion rates in SiO 2 than that in Si SiO 2 can be used as diffusion mask Dopant SiO 2 SiO 2 Si 6
Pad Oxide Relieve strong tensile stress of the nitride Prevent stress induced silicon defects Silicon nitride Pad Oxide Silicon Substrate 7
Blanket Field Oxide Isolation Silicon Wafer Clean Silicon Dioxide Silicon Activation Area Field Oxidation Field Oxide Silicon Oxide Etch 8
Gate Oxide Thickness of oxide (T ox ) must closely match the specification of the MOSFET design T ox must be sufficiently uniform across the entire wafer, and from wafer to wafer, and from run-to-run Extremely low Q f and D it (Good Si/SiO 2 interfacial properties) E BD > 8MV/cm, pinhole free and negligible defects Sufficient long lifetime under normal operating High resistance to hot-carrier damage Resistance to boron penetration Refer to Dr. Hong Xiao V G V D > 0 Poly Si Gate Thin oxide n + Source Electrons p-si n + Drain Si Substrate Source: Dr. PT Liu 9
Growth Mechanism Native oxide: Si surface has a high affinity for oxygen formed in the air or chemical cleaning process quality is bad and should be eliminated 10-20 Å Thermal oxidation: Dry Oxidation Si( solid) + O SiO ( solid) 2 2 Wet Oxidation (steam oxide) Si( solid) + H O SiO ( solid) + 2H 2 2 2 10
1000 o C Si + O 2 SiO 2 Dry Oxidation Original Silicon Surface O 2 Silicon Dioxide O 2 O 2 (SiO 2 ) O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 55% O 2 45% Silicon wafer (Si) Thickness of silicon = 0.45 x (thickness of SiO 2 ) 1 1 1 1 Si substrate 1.3 1.3 1.3 1 1 1.2 1 1 Si substrate Oxidizing species diffuse through SiO 2 to Si/SiO 2 Source: Dr. PT Liu 11
Silicon nitride LOCOS Process Pad Oxide P-type substrate Pad oxidation, nitride deposition and patterning Silicon nitride SiO 2 p + P-type substrate p + Isolation Doping p + LOCOS oxidation SiO 2 p + P-type substrate p + Isolation Doping p + Nitride and pad oxide strip Bird s Beak 12
Typical LOCOS and Bird s Beak Deposited Polysilicon Volume Expansion SiO 2 Original Si Surface Location of Si 3 N 4 Mask Si Substrate 13
LOCOS Compare with blanket field oxide Better isolation Lower step height Less steep sidewall Disadvantage rough surface topography Bird s beak Replacing by shallow trench isolation (STI) 14
Stress Mismatch between different materials Two kinds of stresses, intrinsic and extrinsic Intrinsic stress develops during the film nucleation and growth process. The extrinsic stress results from differences in the coefficients of thermal expansion Tensile stress: cracking film if too high Compressive stress: hillock if too strong 15
Film Stress Bare Wafer After Thin Film Deposition Substrate Substrate Compressive Stress (tend to expand) Negative curvature Substrate Tensile Stress (tend to contract) Positive curvature 16
Illustration of Thermal Stress SiO 2 Si At 400 C L SiO 2 Si Under compressive stress At Room Temperature ΔL = α ΔT L ΔL 17
Coefficients of Thermal Expansion α(sio 2 ) = 0.5 10 6 C 1 α(si) = 2.5 10 6 C 1 α(si 3 N 4 ) = 2.8 10 6 C 1 α(w) = 4.5 10 6 C 1 α(al) = 23.2 10 6 C 1 18
Interfacial Structure Dangling bond Si Si Si Si surface SiO 2 Si Si Si Si Si Si Interfacial trap Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si impurity Oxygen vacancy Stretched bond 19
Interfacial Structure bulk-oxide count TEM boundary total Oxygen count sub-oxide count t ox D. Muller, et. al, Nature, 399, 758(1999) 20
Oxide Traps and Defects Mobile Ionic Charge K + Na + Oxide Trapped Charge + + + ++++++ Fixed Oxide Charge Interface Trapped Charge (Deal, 1980) Fixed Charge (Q f, N f ) (Positive): structural defects due to incomplete oxidation and stress, within 2.5 nm from Si/SiO 2 not electrically communicate with interface states Mobile Oxide Charge (Q m, N m ): Na +, Li +,K +,H + Oxide Trapped Charge (Q ot,n ot ): positive or negative due to hole or electron traps in borken Si-O bonds radiation, charge injection in high field Interface Trapped Charge (Q it,n it, D it ): structural defects due to incomplete oxidation at Si/SiO 2 donor or acceptor-like surface-potential dependent 21
SiO 2 /Si Interface Interface states: imperfect bonds Electrically interacted with channel carriers Assuming each dangling bond give rise to one interface state Impact on device characteristics threshold voltage ( V t ) carrier mobility ( G m ) reliability, oxide integrity and HCI( hot-carrier-injection) degradation Hydrogen annealing at 300-500 o C is effective to passivate Q it at the very end step of process. 22
Deal-Grove Triangle Q f decreases with increasing oxidation temperature Dry O 2 Post oxidation annealing in N 2 or Argon ambient is needed to minimize Q f However, annealing should be kept within specific time period without causing Dry N 2 or Argon increase of Q f 600 900 1200 Fixed Charge, Q f 23
Oxide Growth: Deal-Grove Model Deal-Grove Relation (linear-parabolic growth law): Linear Growth (Reaction-Limited) Regime B Oxide Thickness X = t A Diffusion-limited Regime X = B t t ox t Si 0.44 t ox Top oxide surface Original silicon surface Oxidation Time Silicon Oxide-silicon surface 24
<100> Silicon Dry Oxidation Oxide Thickness (micron) 1.2 1.0 0.8 0.6 0.4 0.2 0 <100> Silicon Dry Oxidation 1200 C 1150 C 1100 C 1050 C 1000 C 950 C 900 C 2 4 6 8 10 12 14 16 18 20 Oxidation Time (hours) 25
Deal-Grove Model-1 Oxidants must be transported from the bulk of the gas to the oxide surface. F = h ( C 1 g g s C g : oxidant concentration in bulk of gas C s : oxidant concentration right next to the oxide surface h g : gas phase mass-transfer coefficient Henry s law C ) In equilibrium, the concentration of a species within a solid is proportional to the partial pressure of that species in the surrounding gas. Gas Oxide Silicon C=Hp, where H is the Henry s law constant and p is the gas pressure C d G Cs C* = H p g (equilibrium concentration in bulk SiO 2 ) C o C o = H p s (equilibrium concentration at bulk gas/sio 2 interface) For ideal gas C = p/kt C i * F1 = h( C Co ), where h = hg / HkT x F 1 F 2 F 3 26
Deal-Grove Model-2 Oxidants must diffuse across the oxide layer already present. F 2 C = D o C x o D is the diffusivity of oxidant in bulk oxide C i is the oxidant concentration in bulk oxide at the oxide/silicon interface x o is the thickness of oxide layer already present Oxidants must react at the oxide/silicon interface F = k C 3 s i i k s is the chemical surface-reaction rate constant C g Gas phase O 2 F 1 SiO 2 Si O 2 Concentration C 0 O 2 F 2 X 0 C* C i O 2 +Si F 3 SiO 2 27
Deal-Grove Model-3 Reaction control Steady state : F=F 1 =F 2 =F 3 * * C C Ci = k k x k x 1+ + 1+ h D D kx s o * 1+ C D * Co = C ks ksxo 1+ + h D kx s o As 0 Ci Co D kx s o As Ci 0 D s s o s o and C g Gas phase C g Gas phase O 2 F 1 SiO 2 Si O 2 Concentration C 0 O 2 F 2 X 0 C* C i Diffusion control SiO 2 Si O 2 F 2 O 2 +Si C* F 3 C 0 SiO 2 C i O 2 +Si F 3 SiO 2 O 2 Concentration X 0 28
Deal-Grove Model-4 There are 2.2 10 22 SiO 2 atoms in one cubic centimeter: N I N * dx k C dx B o s o = F = = I 3 dt k k x s s o dt 2x + A o 1+ + h * 2 1 1 2DC x + Ax i i A= 2 D[ + ] B= τ = k h N B s D A, B : temperature, ambient composition, pressure and crystalline orientation τ is related to the initial oxide thickness I Applying the boundary condition: x o =x i at t=0, the solution of above equation is as expressed in the next slice 29
Growth Mechanism Deal-Grove Relation (linear-parabolic growth law): 2 ox T + AT = B( t+ τ ) 2 Tox ox for t >> τ, t >> A 2 /4B = for (t+ τ) << A 2 /4B T ox Bt Diffusion-controlled B = ( t+τ ) A Reaction-controlled t ox A, B : temperature, ambient composition, pressure and crystalline orientation τ is related to the initial oxide thickness t Si 0.44 t ox Top oxide surface Silicon Original silicon surface Oxide-silicon surface 30
Effect of Temperature exponentially Oxygen diffusivity ~1.17eV Water diffusivity ~0.80eV near to Si-Si bond breaking ~ 1.83eV VLSI Technology S.M. Sze 31
Effect of Pressure The concentration of oxidant just inside the oxide at the gas/sio 2 interface C * is proportional to p g, then both B and B/A are proportional to p g. 32
Effect of Crystal Orientation Effect of crystal orientation is explained by the differences in the surface density of silicon atoms on the various crystal faces. 33
Orientation Dependence <100> <110> <111> Orientation Area of unit cell (cm 2 ) Si atoms in area Si bonds in area Bonds available Bonds Available 10 14 cm -2 bonds 10 14 cm -2 N relative to <110> <110> 2a 2 4 8 4 19.18 9.59 1.000 <111> 1/2 3a 2 2 4 3 15.68 11.76 1.227 <100> a 2 2 4 2 13.55 6.77 0.707 34
Thin Oxide Growth Massoud s empirical model: dxo B = + C exp dt 2xo + A E A C = C oexp kt 8 C 3.6 10 μm / hr, E o A xo L 2.35eV, and L 7nm Apply to either (111) or (100) oriented Si. The first term is the Deal-Grove Model. The second term represents an additional oxidation mechanism. The actual mechanism is still not clear. 35
Conventional Furnace Equipment 36
Thermal Process Hardware Control System Gas Delivery System Loading System Exhaust System Process Tube 37
MFC Furnace System MFC MFC MFC Process Tube Control Valve Scrubber Regulator HCl O 2 N 2 吹除淨化氮氣 Exhaust Control System 在氧化製程中, 總是把氮氣當作鈍氣應用在系統閒置時 晶圓裝載 溫度提昇 溫度穩定和晶圓卸載等步驟中 乾式氧化步驟中也使用氯化氫,HCl or TCA (trichloroethane), 來減少氧化物中的移動離子, 使其成為不可移動的氯化物化合物, 並將界面電荷 (Interface state charge) 降至最低!! 38
Furnace Configuration Horizontal Tube Vertical Tube Center Zone Heating Coils Heaters Gas Flow Quartz Tube T 1 /sec ± 0.5 Flat Zone Tower several hundred wafers Distance 39
Rapid Thermal Process (RTP) External Chamber Ramp Up Ramp Down Process Gas Temperature Quartz Chamber Tungsten-Halogen Lamp IR Pyrometer Time >100 o C/sec >50 o C/sec 40
RTP Tool Bottom Lamps Top Lamps Wafer 41
Dry Oxide Process Sequence Idle with purge N 2 flow Idle with process N 2 flow Wafer boat push in with process N 2 / O 2 flow Temperature ramp-up with process N 2 / O 2 flow Temperature stabilization with process N 2 / O 2 flow Oxidation with O 2, HCl; stop N 2 flow Oxide annealing; stop O 2 ; start process N 2 flow Temperature cool-down with process N 2 flow Wafer boat pull out with process N 2 flow Idle with process N 2 flow Repeat process with next boat 42
Oxidation Recipe 43
Wet Oxidation Faster, higher throughput (H 2 O, HO species) Thick oxide, such as LOCOS Dry oxide has better quality Process Temperature Thickness Oxidation Time Dry oxidation 1000 C 1000 Å ~ 2 hr Wet oxidation 1000 C 1000 Å ~ 12 min Source: Dr. PT Liu 44
Effect of Oxidation Ambient Wet oxidation rate is much higher than dry oxidation rate because HO - or H 2 O diffuses much faster than O 2 in SiO 2. 45
Pyrogenic Steam System Hydrogen Flame, 2 H 2 + O 2 2 H 2 O O 2 H 2 To Exhaust Thermal Couple Process Tube Paddle Wafer Boat Typical H 2 :O 2 ratio is between 1.8:1 to 1.9:1. 46
Outside Torch System (OTS) 47
Pyrogenic Wet Oxidation System MFC Process Tube MFC MFC MFC Wafers Burn Box Control Valves H 2 Process N 2 O 2 Purge N 2 Regulator Scrubbier Exhaust 48
Pyrogenic Oxide Process Sequence Idle with purge N 2 flow Idle with process N 2 flow Ramp O 2 with process N 2 Wafer boat push in with O 2 and process N 2 flows Temperature ramp-up with O 2 and process N 2 flows Temperature stabilization with O 2 and process N 2 flows Ramp O 2 turn off N 2 flow Stabilize O 2 flow Turn on H 2 flow, ignition, and H 2 flow stabilization 49
Pyrogenic Oxide Process Sequence (Cont.) Steam oxidation with O 2 and H 2 flows Hydrogen termination; turn off H 2 while keeping O 2 flow Oxygen termination; turn off O 2, start process N 2 flow Temperature ramp-down with process N 2 flow Wafer boat pull out with process N 2 flow Idle with process N 2 flow Repeat process with next boat Idle with purge N 2 flow 50
Oxide Measurement Thickness Uniformity SEM, TEM, Profilermeter Color chart Spectrophotometry (Reflectometry) Ellipsometry C-V I-V, breakdown voltage C-V, oxide charge 51
Spectrophotometry (Reflectometry) Incident light 1 Interference 2 Human eye or photodetector t Dielectric film, n( λ) Substrate 52
Interference in Thin Films 180 o phase change λ 0 n 0 sinφ= n 1 sinβ λ 1 = λ 0 /n 1 n 2 > n 1 > n 0 =1 λ 2nx cosβ 2x cosβ = m λ = n m 0 1 0 0 0 1 m = 1,2,3 : constructive interference m = 1/ 2,3 / 2,5 / 2 : distructive interference 53
Color Chart 54
Spectroreflectometry System Substrate Film Detectors UV lamp Reflectance (%) 50 45 40 35 30 25 20 15 10 5 0 Constructive interference Destructive interference λ 1 λ 2 λ 3 358 417 476 535 594 653 712 771 Wavelength (nm) 55
Capacitance Measurement of MOS-C Small-signal capacitance MOS capacitance is defined as small signal capacitance and is measured by applying a small ac voltage on the top of a dc bias Impedance is measured by an precision impedance meter The imaginary part of the measured impedance is converted to capacitance. Superimposed AC signal 56
Charge Response in LFCV, HFCV and DD Accumulation ρ ac charge response dc charge response Depletion ρ Deep Depletion LFCV HFCV ρ ρ ρ Inversion W C W depl = 1 Cox = = 1 1 ε ox W + 1 + C C ε t 2 qn ox si si ox ε siε0 ψ s A W dm = 2ε siε0 qn 2ψ The DC V G is swept very fast (<0.01s), the inverted minority carriers do not have time to be thermally generated. A F W dm W dm W dm 57
MOS CV: LFCV, HFCV and DD v ss V G Metal Oxide Si LFCV Minority carrier can follow V G and v ss Inv. C/C ox 1 Flat band will have a little smaller C depending on the size of v ss HFCV Dep. Acc. V G (quiescent point) C ox C si C si = Inverted minority carrier can follow V G but not v ss dqs dψ s deep depletion V th Minority carrier cannot follow either V G or V ss V G 58
Substrate Type N-type substrate (PMOS): invers. depl. 0 accumul. P-type substrate (NMOS): accumul. 0 depl. invers. V G V G C/C ox C/C ox n-type bulk (PMOS) p-type bulk (NMOS) V G V G V G V G 59
Oxide Thickness Determination Oxide Thickness ( T ox ) C ox is high frequency capacitance with the device biased in strong accumulation strong accumulation C H High-Frequency p-sub t ox = Aε C ox ox where A=gate area ( cm 2 ) ε ox = permittivity of oxide material ( F/cm ) C ox = oxide capacitance ( pf ) V G T ox estimated from the CV method may be slightly larger than the thickness measured by the optical method because the additonal QM correction in the accumulation layer. 60
Effect of Oxide Charges Flat-band voltage (V fb ) and threshold voltage (V th ) V fb Definition: The gate voltage at which the energy band in Si substrate is flat, i.e. zero field in Si. V V T ot it f fb = φms Cox Cox Cox C 0 ox th = V fb Q Q C Si ox Positive oxide charge Q + 2φ F Q 1 C/C ox ox x T ox ρ m ( x) dx K + Na + Oxide Trapped Charge + + + ++++++ Mobile Ionic Charge Fixed Oxide Charge Interface Trapped Charge 61
Interface Traps at One Energy Level We will first examine an ideal case: a midgap trap with donor-like behavior: when the Fermi level is above the trap level, the trap is filled and exhibits no charge (trap filled with electron); when the Fermi level is below the trap level, the trap is empty and exhibits a positive charge state (trap empty). 0 filled pmos E C E F E V + 0 partially filled E C E F E V + empty accumulation depletion inversion HFCV distorted by midgap donor-like trap pmos C/C ox midgap depletion point E C E F E V ideal HFCV 62
Passivation of Interface Traps If we have instead a distribution of trap levels across the band gap, then the resulting influence of HFCV will be a distortion of the ideal CV curve. Notice that how different trap types can distort CV in different ways. donor-like traps acceptorlike traps pmos E C E F E V affected by donor-like traps C/C ox affected by acceptor-like traps ideal HFCV 63
High-Low Frequency CV HF must be high enough so that the charge/discharge of traps cannot follow. HF must be low enough so that the charge/discharge of traps can follow. 64