MC74CT00A Quad 2-Input NAND Gate The MC74CT00A is an advanced high speed CMOS 2 input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TT type input thresholds and the output has a full 5 CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic level translator from CMOS logic to 5.0 CMOS ogic or from.8 CMOS logic to CMOS ogic while operating at the high voltage power supply. The MC74CT00A input structure provides protection when voltages up to 7 are applied, regardless of the supply voltage. This allows the MC74CT00A to be used to interface 5 circuits to 3 circuits. The output structures also provide protection when CC = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. igh Speed: t PD = 5.0 ns (Typ) at CC = 5 ow Power Dissipation: I CC = 2 μa (Max) at T A = 25 C TT Compatible Inputs: I = ; I = Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for to 5.5 Operating Range ow Noise: OP = (Max) Pin and Function Compatible with Other Standard ogic Families Chip Complexity: 48 FETs or 2 Equivalent Gates N Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable These Devices are Pb Free and are RoS Compliant 4 SOIC 4 D SUFFIX CASE 75A 4 TSSOP 4 DT SUFFIX CASE 948G MARKING DIAGRAMS 4 CT00AG AWYWW A = Assembly ocation W, = Wafer ot YY, Y = Year WW, W = Work Week G or = Pb Free Package 4 CT 00A AYW (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the dimensions section on page 6 of this data sheet. Semiconductor Components Industries, C, 204 October, 204 Rev. 6 Publication Order Number: MC74CT00A/D
MC74CT00A CC B4 A4 Y4 B3 A3 Y3 4 3 2 0 9 8 A B A2 B2 A3 B3 2 4 5 9 0 3 Y 6 Y2 8 Y3 Y = AB 2 3 4 5 6 7 A B Y A2 B2 Y2 GND A4 B4 2 3 Y4 Figure. Pin Assignment (Top iew) Figure 2. ogic Diagram FUNCTION TABE PIN ASSIGNMENT Inputs Output IN A 2 IN B 3 OUT Y 4 IN A2 5 IN B2 A B Y 6 OUT Y2 7 8 GND OUT Y3 9 IN A3 0 IN B3 OUT Y4 2 IN A4 3 IN B4 4 CC A B A2 B2 A3 B3 A4 B4 2 4 5 9 0 2 3 & 3 6 8 Y Y2 Y3 Y4 Figure 3. IEC OGIC DIAGRAM 2
MC74CT00A MAXIMUM RATINGS Symbol Characteristics alue Unit CC DC Supply oltage 0.5 to +7.0 IN DC Input oltage 0.5 to +7.0 OUT DC Output oltage CC = 0 igh or ow State 0.5 to 7.0 0.5 to CC + 0.5 I IK Input Diode Current 20 ma I OK Output Diode Current OUT < GND; OUT > CC +20 ma I OUT DC Output Current, per Pin +25 ma I CC DC Supply Current, CC and GND +50 ma P D Î Power Dissipation in Still Air, SOIC Package (Note ÎÎ ) 500 ÎÎÎ mw TSSOP Package (Note ) T ead temperature, mm from case for 0 s 260 C T stg Storage temperature 65 to +50 C ESD ESD Withstand oltage uman Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) I atch Up atch Up Performance Above CC and Below GND at 25 C (Note 5) 450 > 2000 > 200 > 3000 ±300 ma Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Derating SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C 2. Tested to EIA/JESD22 A4 A 3. Tested to EIA/JESD22 A5 A 4. Tested to JESD22 C0 A 5. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. Symbol Characteristics Min Max Unit CC DC Supply oltage 5.5 IN DC Input oltage 0.0 5.5 OUT DC Output oltage CC = 0 igh or ow State 0.0 0.0 5.5 CC T A Operating Temperature Range 55 +25 C t r, t f Input Rise and Fall Time CC = 3.3 ± 0.3 CC = 5.0 ± 0.5 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 0 0 00 20 ns/ 3
MC74CT00A The JA of the package is equal to /Derating. igher junction temperatures may affect the expected lifetime of the device per the table and figure below. DEICE JUNCTION TEMPERATURE ERSUS TIME TO 0.% BOND FAIURES Junction Temperature C Time, ours Time, Years 80,032,200 7.8 90 49,300 47.9 00 78,700 20.4 0 79,600 9.4 20 37,000 4.2 30 7,800 40 8,900.0 NORMAIZED FAIURE RATE FAIURE RATE OF PASTIC = CERAMIC UNTI INTERMETAICS OCCUR TJ = 30 C TJ = 20 C TJ = 0 C TJ = 00 C TJ = 90 C TJ = 80 C 0 00 000 TIME, YEARS Figure 4. Failure Rate vs. Time Junction Temperature DC EECTRICA CARACTERISTICS CC T A = 25 C T A 85 C T A 25 C Symbol Parameter Test Conditions () Min Typ Max Min Max Min Max Unit I Minimum igh evel Input oltage 5.5.4.4.4 I Maximum ow evel Input oltage 5.5 0.53 0.53 0.53 O Minimum igh evel Output oltage IN = I or I IN = I or I I O = 50 μa IN = I or I I O = 4 ma I O = 8 ma 2.9 4.4 2.58 3.94 2.9 4.4 2.48 3.80 2.9 4.4 2.34 3.66 O Maximum ow evel Output oltage IN = I or I IN = I or I I O = 50 μa IN = I or I I O = 4 ma I O = 8 ma 0.0 0.0 0. 0. 0.36 0.36 0. 0. 0.44 0.44 0. 0. 0.52 0.52 I IN Maximum Input eakage Current IN = 5.5 or GND 0 to 5.5 ±0. ±.0 ±.0 μa I CC I CCT Maximum Quiescent Supply Current Quiescent Supply Current IN = CC or GND 5.5 20 40 μa Input: IN = 3.4 5.5.35.50.65 ma I OPD Output eakage Current OUT = 5.5 0.0 0.5 5.0 0 μa Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4
MC74CT00A Î AC EECTRICA CARACTERISTICS C load = 50 pf, Input t r = t f = ns T A = 25 C Î T A 85 C Î T A 25 C ÎÎ SymbolÎÎ Parameter ÎÎÎ Test Conditions MinÎÎÎ TypÎÎÎ MaxÎÎÎ MinÎÎÎ Max ÎÎÎ Min ÎÎÎ Max ÎÎ Unit t P, ÎÎ Maximum ÎÎÎ CC = 3.3 ± 0.3 C = 5 pf t P Propogation Delay, C = 50 pf 4. ÎÎÎ 5.5ÎÎÎ 0.0 ÎÎÎ ÎÎÎ.0 ÎÎÎ ÎÎÎ ÎÎ 3.5 5.0 7.5 ÎÎÎ ÎÎÎ ÎÎÎ ns Input A or B to Y ÎÎÎ CC = 5.0 ± 0.5 C = 5 pf 3.ÎÎÎ 6.9Î 8.0 Î 9.5 ÎÎ C = 50 pf 3.6 7.9 9.0 0.5 ÎÎ C IN Maximum Input ÎÎ Capacitance ÎÎ 5.5ÎÎÎ ÎÎÎ 0ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 0 ÎÎÎ pf Typical @ 25 C, CC = 5.0 C PD Power Dissipation Capacitance (Note 6) 7 pf 6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD 2 CC f in + I CC CC. NOISE CARACTERISTICS (Input t r = t f = ns, C = 50pF, CC = 5.0, Measured in SO Package) Symbol Characteristic Typ T A = 25 C OP Quiet Output Maximum Dynamic O 0.4 O Quiet Output Minimum Dynamic O 0.4 ID Minimum igh evel Dynamic Input oltage ID Maximum ow evel Dynamic Input oltage Max Unit TEST POINT A or B 50% t P GND t P DEICE UNDER TEST OUTPUT C * Y 50% CC O O *Includes all probe and jig capacitance Figure 5. Switching Waveforms Figure 6. Test Circuit INPUT OUTPUT * *Parastic Diode Figure 7. Input Equivalent Circuit Figure 8. Output Equivalent Circuit 5
MC74CT00A ORDERING INFORMATION MC74CT00ADR2G MC74CT00ADTR2G N74CT00ADTR2G* Device Package Shipping SOIC 4 (Pb Free) TSSOP 4 (Pb Free) 2500 / Tape & Reel 2000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD80/D. *N Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable. 6
MC74CT00A PACKAGE DIMENSIONS T SEATING PANE G A 4 8 D 4 P 7 B K P 7 P C 0.25 (0.00) M T B S A S SOIC 4 D SUFFIX CASE 75A 03 ISSUE J 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, 982. 2. CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.27 (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. MIIMETERS INCES R X 45 F DIM MIN MAX MIN MAX A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.50 0.57 C.35.75 0.054 0.068 D 0.35 0.49 0.04 0.09 M J F 0.40.25 0.06 0.049 G.27 BSC 0.050 BSC J 0.9 0.25 0.008 0.009 K 0.0 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.00 0.09 SODERING FOOTPRINT 4X 0.58 7X 7.04 4X.52.27 PITC DIMENSIONS: MIIMETERS 7
MC74CT00A PACKAGE DIMENSIONS TSSOP 4 DT SUFFIX CASE 948G ISSUE B 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PANE U U S 2X /2 PIN IDENT. S D C 4 G 4X K REF A 0.0 (0.004) M T U S S 8 7 B U N N J J F DETAI E DETAI E 0.25 (0.00) K K M ÇÇÇ ÉÉÉ SECTION N N NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, 982. 2. CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS, PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXCESS OF TE K DIMENSION AT MAXIMUM MATERIA CONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MAX MIN MAX A 4.90 5.0 0.93 0.200 B 4.30 0 0.69 0.77 C.20 0.047 D 0.05 0.5 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J 0.09 0.6 0.004 0.006 W K 0.9 0.30 0.007 0.02 K 0.9 0.25 0.007 0.00 6.40 BSC 0.252 BSC M 0 8 0 8 SODERING FOOTPRINT 7.06 0.65 PITC 4X 0.36 4X.26 DIMENSIONS: MIIMETERS ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, C (SCIC) or its subsidiaries in the United States and/or other countries. SCIC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCIC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: 303 675 275 or 800 344 3860 Toll Free USA/Canada Fax: 303 675 276 or 800 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 790 290 Japan Customer Focus Center Phone: 8 3 587 050 8 ON Semiconductor Website: www.onsemi.com Order iterature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74CT00A/D