18-: Intrductin t Telecmmunicatin Netwrks Lectures : Physical Layer Peter Steenkiste Spring 01 www.cs.cmu.edu/~prs/nets-ece Physical Layer: Outline Digital Representatin f Infrmatin Characterizatin f Cmmunicatin Channels Fundamental Limits in Digital Transmissin Line Cding Mdems and Digital Mdulatin Prperties f Media and Digital Transmissin Systems Errr Detectin and Crrectin 1 Errr Cntrl Channels intrduce errrs in digital cmmunicatins Applicatins require certain reliability level Data applicatins require errr-free transfer Vice & vide applicatins tlerate sme errrs Errr cntrl may be needed t meet applicatin requirement Errr cntrl ensures a data stream is transmitted t a certain level f accuracy despite errrs Tw basic appraches: Errr detectin & retransmissin (ARQ) Frward errr crrectin (FEC) Key Idea All transmitted data blcks ( cdewrds ) are chsen s that they satisfy a pattern If received blck desn t satisfy pattern, it is in errr Redundancy: Only a subset f all pssible blcks can be valid cdewrds Undetectable Errr: When channel transfrms a cdewrd int anther valid cdewrd User infrmatin All inputs t channel satisfy pattern r cnditin Encder Channel Channel utput Pattern checking Deliver user infrmatin r set errr alarm 1
Single Parity Check Eample f Single Parity Cde Append an parity bit t k infrmatin bits Inf Bits: b 1, b, b,, b k Check Bit: b k+1 = b 1 + b + b + + b k mdul Cdewrd: (b 1, b, b,, b k,, b k+1 ) All cdewrds have even # f 1s Receiver checks t see if # f 1s is even All errr patterns that create an dd # f 1 bits are detectable All even-numbered errr patterns are undetectable ASCII cde is precisely such as cde (+1 bits) Infrmatin ( bits): (0, 1, 0, 1, 1, 0, 0) Parity Bit: b 8 = 0 + 1 +0 + 1 +1 + 0 = 1 Cdewrd (8 bits): (0, 1, 0, 1, 1, 0, 0, 1) If single errr in bit : (0, 1, 1, 1, 1, 0, 0, 1) # f 1 s =, dd Errr detected If errrs in bits and : (0, 1, 1, 1, 0, 0, 0, 1) # f 1 s =, even Errr nt detected Parity Checkbits & Errr Detectin Infrmatin bits Calculate check bits k bits Sent check bits n k bits Channel Received check bits Received infrmatin bits Recalculate check bits Cmpare Infrmatin accepted if check bits match Hw gd is the single parity check cde? Redundancy: Single parity check cde adds 1 redundant bit per k infrmatin bits: verhead = 1/(k+1) Cverage: all errr patterns with dd # f errrs can be detected An errr pattern is a binary (k+1)-tuple with 1 s where errrs ccur and 0 s elsewhere Of k+1 binary (k+1)-tuples, ½ are dd, s 0% f errr patterns can be detected Is it pssible t detect mre errrs if we add mre check bits? Yes, with the right cdes 8
What if bit errrs are randm? Many transmissin channels intrduce bit errrs at randm, independently f each ther, and with prbability p Sme errr patterns are mre prbable than thers: 8 p P[10000000 ] p(1 p) (1 p) ( ) and 1 p P[11000000 ] p 8 p (1 p) (1 p) ( ) 1 p In any wrthwhile channel p<0., and s (p/(1-p))<1 It fllws that patterns with 1 errr are mre likely than patterns with errrs and s frth What is the prbability that an undetectable errr pattern ccurs? 9 Single parity check cde with randm bit errrs Undetectable errr pattern if even # f bit errrs: P[errr detectin failure] P[undetectable errr pattern] P[errr patterns with even number f 1s] n p (1 p) n p n n (1 p)... Eample: Evaluate abve fr n=, p=10 - P[undetectable errr] (10 ) (1 10 ) 0-9 (10 ) 90(10 (10 ) (1 10 ) 1 ).9(10 Fr this eample, rughly 1 in 000 transmissins will result in an undetectable errr ) 8 10 What is a gd cde? Mst channels will have relatively few bit errrs Errneus cdewrds transmitted ver thse channels will map t nearby n-tuples If valid cdewrds are clse t each ther, then detectin failures may ccur Gd cdes shuld maimize separatin between valid cdewrds = valid cdewrds = nn-cdewrds Pr distance prperties Gd distance prperties 11 Tw-Dimensinal Parity Check Mre parity bits t imprve cverage Arrange infrmatin as clumns Add single parity bit t each clumn Add a final parity clumn Used in early errr cntrl systems 0 1 0 0 0 1 1 1 0 1 1 0 Bttm rw cnsists f check bit fr each clumn Last clumn cnsists f check bits fr each rw 1
Errr-detecting capability 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 One errr Three errrs 0 0 0 0 0 1 Tw errrs 1 0 0 1 1 0 0 0 0 1 0 1 Fur errrs 1 0 0 0 1 0 1,, r errrs can always be detected; Nt all patterns > errrs can be detected Other Errr Detectin Cdes Many applicatins require very lw errr rate Need cdes that detect mre number f errrs Single parity check cdes d nt detect enugh errrs Tw-dimensinal cdes require t many check bits The fllwing errr detecting cdes are widely used in practice: Internet Check Sums CRC Plynmial Cdes Arrws indicate failed check bits 1 1 Internet Checksum Several Internet prtcls (e.g. IP, TCP, UDP) use check bits t detect errrs in the header A checksum is calculated fr header cntents and included in a special field. Checksum is ptentially recalculated at every ruter, s algrithm selected fr ease f implementatin in sftware Let header cnsist f L, 1-bit wrds, b 0, b 1, b,..., b L-1 The algrithm appends a 1-bit checksum b L Checksum Calculatin The checksum b L is calculated as fllws: Treating each 1-bit wrd as an integer, find = b 0 + b 1 + b +...+ b L-1 mdul 1-1 The checksum is then given by: b L = - mdul 1-1 Thus, the headers must satisfy the fllwing pattern at the receiver: 0 = b 0 + b 1 + b +...+ b L-1 + b L mdul 1-1 The checksum calculatin is carried ut in sftware using ne s cmplement arithmetic 1 1
Internet Checksum Eample Use Mdul Arithmetic Assume -bit wrds Use md -1 (= 1) arithmetic b 0 =1100 = 1 b 1 =1010 = 10 b 0 +b 1 =1+10= md1 b = - = 8 md1 Therefre b =1000 Use Binary Arithmetic Nte 1 =1 md1 S: 10000 = 0001 md1 leading bit wraps arund b 0 + b 1 = 1100+1010 =10110 =10000+0110 =0001+0110 =0111 = Take 1 s cmplement Plynmial Cdes Plynmials instead f vectrs fr cdewrds Plynmial arithmetic instead f check sums Implemented using shift-register circuits Als called cyclic redundancy check (CRC) Mst data cmmunicatins standards use plynmial cdes fr errr detectin Have very simple hardware implementatins Plynmial cdes als basis fr pwerful errr-crrectin methds b = -0111 =1000 1 18 Additin: Binary Plynmial Arithmetic Binary vectrs map t plynmials k 1 k 1 ( ik 1, ik,..., i, i1, i0 ) ik 1 ik... i i1 i0 ( 1) ( Multiplicatin: ( 1)( ) (1 1) 1) ( 1 ( 1 1 1 since 1 1 0 md 1) 1( ) ( 1) 1) 19 Binary Plynmial Divisin Divisin with Decimal Numbers divisr ) 1 10 1 10 Plynmial Divisin divisr qutient dividend remainder Nte: Degree f r() is less than degree f divisr dividend = qutient divisr + remainder + + + 1 ) + 1 = + + + + + + + + + + + = q() qutient dividend = r() remainder 0
i Plynmial Cding k infrmatin bits define plynmial f degree k-1 k 1 k ( ) ik 1 ik... i i1 i0 Cde has binary generating plynmial f degree n-k nk nk 1 g( ) g nk 1... g g1 1 Find remainder plynmial f at mst degree n-k-1 q() g() ) n-k i() n-k i() = q()g() + r() r() Define the cdewrd plynmial f degree n-1 b() = n-k i() + r() n bits k bits n-k bits 1 Plynmial eample: k=, n-k= Generatr plynmial: g()= + + 1 Infrmatin: (1,1,0,0) i() = + Encding: i() = + + + + + 1 ) + + + + + + + + + + 1110 1011 ) 1100000 1011 1110 1011 1010 1011 Transmitted cdewrd: b() = + + b = (1,1,0,0,0,1,0) 010 The Pattern in Plynmial Cding All cdewrds satisfy the fllwing pattern: b() = n-k i() + r() = q()g() + r() + r() = q()g() All cdewrds are a multiple f g()! Receiver shuld divide received n-tuple by g() and check if remainder is zer If remainder is nn-zer, then received n-tuple is nt a cdewrd Shift-Register Implementatin 1. Accept infrmatin bits i k-1,i k-,,i,i 1,i 0. Append n-k zers t infrmatin bits. Feed sequence t shift-register circuit that perfrms plynmial divisin. After n shifts, the shift register cntains the remainder
Feedback-Shift Register Circuit Undetectable errr patterns + Encder fr g ( ) 1 g 0 1 Reg 0 + g 1 1 0,0,0,i 0,i 1,i,i g = 0 Reg 1 Reg Clck Input Reg 0 Reg 1 Reg 0-0 0 0 1 1 = i 1 0 0 1 = i 1 1 0 0 = i 1 0 1 1 0 = i 0 1 1 1 0 1 0 1 0 1 0 0 0 0 1 0 Check bits: r 0 = 0 r 1 = 1 r = 0 r() = g 1 (Transmitter) b() (Channel) + e() (Receiver) Errr plynmial R()=b()+e() e() has 1 s in errr lcatins & 0 s elsewhere Receiver divides the received plynmial R() by g() Undetectable errr: If e() is a multiple f g(), that is, e() is a nn-zer cdewrd, then R() = b() + e() = q()g() + q ()g() The set f undetectable errr plynmials is the set f nnzer cde plynmials Chse the generatr plynmial s that selected errr patterns can be detected. Designing gd plynmial cdes Select generatr plynmial s that likely errr patterns are nt multiples f g() Detecting Single Errrs e() = i fr errr in lcatin i+1 If g() has mre than 1 term, it cannt divide i Detecting Duble Errrs e() = i + j = i ( j-i +1) where j>i If g() has mre than 1 term, it cannt divide i If g() is a primitive plynmial, it cannt divide m +1 fr all m< n-k -1 (Need t keep cdewrd length less than n-k -1) Primitive plynmials can be fund by cnsulting cding thery bks Standard Generatr Plynmials CRC-8: CRC-1: CCITT-1: CCITT-: CRC = cyclic redundancy check 8 1 ATM 1 1 1 ( 1)( 1 1) Bisync 1 1 1 HDLC, XMODEM, V.1 IEEE 80, DD, V. 1 1 11 10 8 1 8
Hamming Cdes Class f errr-crrecting cdes Capable f crrecting all single-errr patterns Fr each m >, there is a Hamming cde f length n= m -1 with n-k=m parity check bits m n= m -1 k=n-m m/n / 1 11 /1 1 /1 / Redundancy 9 m= Hamming Cde Infrmatin bits are b 1, b, b, b Equatins fr parity checks b, b, b b b b b1 + b b 1 b b b b b b There are =1 cdewrds (0,0,0,0,0,0,0) is a cdewrd 0 Hamming (,) cde Infrmatin Cdewrd Weight b 1 b b b b 1 b b b b b b w(b) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Minimum distance f any Hamming Cde = Set f n- tuples within distance 1 f b 1 b 1 b Distance Set f n- tuples within distance 1 f b Spheres f distance 1 arund each cdewrd d nt verlap If a single errr ccurs, the resulting n-tuple will be in a unique sphere arund the riginal cdewrd Thus, receiver can crrect errneus receptin back t riginal cdewrd 8
Physical Layer: Summary Digital Representatin f Infrmatin Characterizatin f Cmmunicatin Channels Fundamental Limits in Digital Transmissin Line Cding Mdems and Digital Mdulatin Prperties f Media and Digital Transmissin Systems Errr Detectin and Crrectin 9