An Area Efficient (31, 16) BCH Decoder for Three Errors

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1 An Area Efficient (31, 16) BCH Decder fr Three Errrs M. Prashanthi 1, P. Samundiswary 2 1 M. Tech, Department f Electrnics Engineering, Pndicherry University, Pndicherry, India 2 Assistant Prfessr, Department f Electrnics Engineering, Pndicherry University, Pndicherry, India Abstract Bse, Ray- Chaudhuri, Hcquenghem (BCH) cdes are ne f the efficient errr-crrecting cdes used t crrect errrs ccurred during the transmissin f the data in the unreliable cmmunicatin mediums. This paper presents a lwcmplexity and area efficient errr-crrecting BCH decder architecture fr detecting and crrecting three errrs. The advanced Petersn errr lcatr cmputatin algrithm, which significantly reduces cmputatinal cmplexity, is prpsed fr the IBM blck in the (31,6) BCH decder. In additin, a mdified syndrme calculatr and chien search are prpsed t reduce hardware cmplexity. The design methdlgies f the prpsed BCH decder mdels have cnsiderably less hardware cmplexity and latency than thse using cnventinal algrithms. The prpsed (31, 16) BCH decder ver GF (5), leads t a reductin in cmplexity cmpared t that f cnventinal BCH decder. The enhanced BCH decder is designed using hardware descriptin language called Verilg and synthesized in Xilinx ISE Keywrds BCH decder, Petersn s algrithm, chien Search, VLSI design. I. INTRODUCTION BCH cdes are large class f multiple errr-crrecting cdes. The binary BCH cdes were discvered in 1959 by Hcquenghem and independently in 1960 by Bse and Ray- Chaudhuri. Later, Grenstein and Zierler generalized them t all finite fields. In practice, the binary BCH and Reed-Slmn cdes are the mst cmmnly used variants f BCH cdes. They have applicatins in a variety f cmmunicatin systems: digital subscriber lps, wireless systems, netwrking cmmunicatins, and magnetic and data strage systems. Cntinuus demand fr ever higher data rates and strage capacity prvide an incentive t devise very high-speed and space-efficient VLSI implementatins f BCH decders. The first decding algrithm fr binary BCH cdes was devised by Petersn in BCH cdes are generally develped in Galis Field (GF).The Galis field was invented by Everest Galis. GF has finite number f elements in it. The thery f Finite field intrduced arund 18 th century, while its imprtance and the widespread applicatins widely recgnized in recent years. The GF is widely used in number thery, cding thery and cryptgraphy. The mathematical prperties within which BCH cdes are defined, als represents Galis field[6]. The mathematical peratins like additins, subtractins, multiplicatins and divisins are perfrmed using Finite field thery. The mst basic axims f the finite field are: a) All the elements in the field frms an Abelian grup with additinal peratr +. b) The nn-zer elements in the field frms grup with multiplicatin peratr.. c) Multiplicatins by any nn zer elements is an autmrphism f the Additive grup. There exists a Galis field, als knwn as the finite fields, ver the set GF(p) fr every prime number p. The finite fields are having p elements with special elements 0 and 1 as the additive and multiplicative identities respectively. The extended field, dented as GF(p m ), are cmprised f the plynmials f degree m 1 ver the field Zp. These plynmials are expressed as a m 1 x m a 1 x 1 +a 0 x 0 where the cefficients a i take n values in the set {0, 1,..., p 1}.When this extended field is used in cding applicatins p is cmmnly 2 and thus the cefficients {a 0,..., a m 1 } are taken frm the binary digits {0, 1}. The variable t is defined as an errr detecting BCH cde f length n ver GF (p m ) as the set f all sequences. The cde length n is equal t p m 1.The BCH cde with m=1 is called the Reed Slemn cde. BCH cdes are widely used in errr-cding techniques, cncatenated either with cnvlutin cdes r with ther blck cdes such as Lw-density parity check (LDPC) cdes. Secnd generatin Digital Vide Bradcast (DVB) standards are adpting BCH cdes as part f their cncatenated cded strategy [7]. BCH cdes architecture use field thery as well as plynmial ver finite filed. T detect any errr has ccurred during transmissin, a check plynmial is cnstructed. The BCH cde with distance δ ver the finite field GF (p m ) is cnstructed by finding plynmial ver GF (p), whse rts include δ cnsecutive pwer f y. T crrect t number f errrs, a BCH cde is implemented in rdered frm. In this frm, a BCH cde is btained by dividing the message plynmial with the generatr plynmial and then appending the remainder with the message t frm the cdewrd plynmial. The generatr plynmial is frmed by taking the ISSN: Page 616

2 Least-Cmmn Multiple (LCM) f all the minimal plynmials crrespnding t the rts. The divisin is implemented using LFSR architecture. The bjective f this wrk is t reduce the number f cmpnents used fr designing the triple errr crrectin fr a BCH decder by incrprating mdified structures f varius blcks which is described in this paper. The Petersn s algrithm reduces the cmplexity alng with size f the Lk Up Tables (LUT) fr the IBM blck and new factrizatin methd f the chien search blck reduces the number f lgic gates used t find the errr lcatin. This paper is rganized as fllws; Sectin II explains the existing mdel f the BCH decder and sectin III explains the mdified BCH decder and detailed structure f syndrme, IBM and Chien search respectively. Results are analysed in the sectin IV. Sectin V is drawn with the cnclusin. II. EXISTING BCH DECODER ARCHITECTURE The BCH decder nrmally cnsists f fur mdules namely: Syndrme Calculatr Inversin less Berlekamp Algrithm Chien Search Errr Crrectin A. Syndrme Calculatr The syndrme calculatr is the first mdule f the BCH decder. The input t this mdule is the crrupted cdewrd. The equatins fr the cdewrd, received bits and the errr bits are given as belw. Cdewrd equatin c(x) = c 0 + c 1 x + c 2 x c n-1 x n-1 (1) syndrmes is that it depends nly n errr lcatin nt n transmitted infrmatin [5]. The equatin f the syndrmes is given as fllws which define the syndrmes 4S j as S j n1 ri i0 i j fr (1 j 2t). B. Inversin less Berlekamp Massey (IBM) (5) The secnd stage in the decding prcess is t find the cefficient f the errr lcatin plynmial using the generated syndrmes in the previus stage. The errr lcatin plynmial is given as: (x) = x t x t. The relatin between the syndrmes and the errr lcatin plynmial is given as belw [1]: t S t i j j 0 0 (i= 1,..., t) (6) j There are varius algrithms used t slve the key equatin slver. In this prject Inversin less Berlekamp Massey algrithm is used t slve the key equatin [2]. Berlekamp Massey Algrithm: The steps f Berlekamp Massey algrithm is given as belw: 1. First step is t calculate errr syndrmes Sj. 2. Initialize the k = 0, Λ (0) (x) = 1, L = 0 and T(x) = x 3. Assign k = k + 1 and then the discrepancy Δ (k) is then calculated as fllws: (7) Received bits equatin r(x) = r 0 + r 1 x + r 2 x r n-1 x n-1 Errr bits equatin e (x) = e 0 + e 1 x + e 2 x e n-1 x n-1 (2) (3) 4. If the value f Δ (k), 2L equals 0, then g-t step Calculate the Λ (k) (x) = Λ (k-1) (x) - Δ (k) T(x) 6. Set the value f L = k L and T(x) is calculated as T(x) = Λ (k-1) (x) / Δ (k) Set T(x) = x.t(x). Thus, the final transmitted data plynmial equatin is given as belw: 7. If the value f k< 2t, then g-t step 3 Cntinue fr i = 2t 1 and then End. r (x) = c(x) + e(x) (4) C. Chien Search The 1 st step at the decdin prcess is t stre the transmitted data plynmial in the buffer register and then t calculate the syndrmes S j. The imprtant characteristic f the Chien Search blck is the third step f decding prcess, which is used t calculate the errr lcatin [4]. ISSN: Page 617

3 syndrmes are reduced. The internal structure f mdified syndrme blck is shwn in Figure 2. B. IBM The rts f the three errr plynmial are cmputed directly by transfrming the errr plynmial int a Petersn errr lcatr cmputatin algrithm. Thus, the mre efficient and lw cmplexity Petersn errr lcatr cmputatin algrithm is used fr t=3, where is cmputed directly. The degree f ( ) is equal t the number f errrs happened. Fr t=3, the matrix (A) given as Figure 1: Internal Structure f Existing Chien Search T lcate the rts f the plynmial, chien search blck is implemented in the hardware fr the BCH decder. The chien search blck has a prperty that the rts are ging t be a pwer f α, which reduces the evlutin f the plynmial fr every rt[3]. S, the chien search blck is used t prvide the cmputatinal benefits f this step, Λ i (j) = Λ i (j-1) α i (1.7) This prperty makes the chien search methd mre superir than ther methds III. MODIFIED BCH DECODER ARCHITECTURE A. Syndrme Calculatr The mdified syndrme used in this paper is easy t cmpute and prvide a simple and scalable apprach. There will be 2t syndrmes which can be crrected by the decder. =( (1.8) If the abve matrix is nn-singular then det(a)= + If nly single errr has ccurred. When mre than tw errrs has ccurred. By slving the abve matrix we get: =0001 = = + =( )+ C. Chien Search The errr psitin is calculated by using the belw equatin: = (8) where, is the errr lcatr plynmial. Fr the cdewrd (n, k), the errr psitin is calculated as,. (9) If the expressin reduces t zer, then that value is the rt and it identifies the errr psitin else the psitin des nt cntain any errr. The internal structure f mdified chien search blck is shwn in Figure 2. Figure 2: Internal Structure f mdified Syndrme Blck Thus, 2t syndrmes are cmputed instead f t syndrmes by using the abve equatin. As the result, area is reduced since the number f cmpnents required t calculate the Factrizatin Methd In this methd, anther frm f chien search circuit is designed that minimizes large number f the lgic gates used in the circuit, by factrizing the errr lcatr plynmial ) such that it is nt depicted in its expressin. ISSN: Page 618

4 Figure3: Internal Structure f Mdified Chien Search IV. SIMULATION RESULTS & ANALYSIS The enhanced (31,6) BCH decder is designed using Verilg. Then the advanced decder is simulated and synthesized in Xilinx ISE Figure 6: RTL View f BCH Decder Figure 4: Tp View f (31,16) BCH Decder Figure 4 illustrates the tp view f (31, 16) BCH decder where data f 31bits is the crrupted cdewrd given as the input t the decder and the utput rigdata is the recvered 31 bit uncrrupted data. Internal structure f BCH decder shwn in figure 5 is the integratin f syndrme, IBM, chien search and errr crrectin blcks. Figure 7: Timing Wavefrm f BCH Decder Table 1: Cmparsin f Existing and Prpsed (31.16) BCH Decder Blck N f Slices 4 Input LUT Delay(ns) Existing Prps ed Existin g Prps ed Existin g Prpse d BCH Decder Syndrme IBM Figure 5: Internal Structure f BCH Decder Chien Search The belw figure 6 shws the Register Transfer Lgic (RTL) View f the BCH decder which cnsists f lgical gates required fr all the internals blcks. The timing wavefrm f BCH decder is illustrated in figure 7. Frm the abve Table 1 it is infered that the existing mdel ccupies mre area than the prpsed mdel since it has less n f slices and 4 input Lk Up Tables(LUTs) cmpared t that f existing mdel ISSN: Page 619

5 V. CONCLUSION An Area Efficient (31, 16) BCH Decder fr three errrs has been designed and simulated in Xilinx ISE Frm the simulatin results, it is bserved that the prpsed BCH decder mdel is area and speed efficient, since the number f slices and delay f the prpsed mdel is lesser than the existing mdel. Thus area efficiency f 35% is btained using the prpsed BCH decder structures. REFERENCES 1. Xinmia Zhang and Zhngfeng Wang, A Lw-Cmplexity Three-Errr-Crrecting BCH Decder fr Optical Transprt Netwrk, IEEE transactins n circuits and systems II: express briefs, vl. 59, pp. 10, Oct Nahmadi and MH Sirjuddiin, An Optimal Architecture f BCH Decder, Prceedings f IEEE Cnference Asian n Infrmatin Thery, Indnesia,pp.65-72,Nv Hans Kristian, Hernand Wahyn, Kiki Rizki and Tri Adin, Ultra-Fast-scalable BCH Decder with Efficient- Extended Fast Chien Search, Prceedings f IEEE Internatinal Mideast Sympsium Circuits and System,china, pp , May Hlu Lamari, EL habti EL idrissi Anas and Elguri Rachid, A Lw Pwer Errr Detectin in the Chien Search Blck fr Reed-Slmn Cde,IEEE Transactins n Infrmatin Thery, vl IT-15, pp , Feb R. Huynh, G. Ning, and Y.Huazhung, A Lw Pwer Errr detectin in the syndrme calculatr Blck fr Reed- Slmn cdes RS: (248, 1881), Prceedings f IEEE n J. Tsinghua Science and Technlgy, vl. 14, pp , August Hans Kristian, Hernand Wahyn, Kiki Rizki and Tri Adin, Ultra-Fast-scalable BCH Decder with Efficient- Extended Fast Chien Search, Prceedings f IEEE Internatinal Mideast Sympsium Circuits and System, pp , May Hung-Yuan Tsai, Chi-Heng Yang, and Hsie-Chia Chang, An Efficient BCH Decder with 124-bit Crrect ability fr Multi- Channel SSD Applicatins, Prceedings f IEEE Asian Cnferences n Slid-State Circuits,Japan,pp.65-72, Nvember,2012. ISSN: Page 620