Questions Preparation of Examination Questions and Exercises: Solutions. -bit Subtraction: DIF = B - BI B BI BO DIF 2 DIF: B BI 4 6 BI 5 BO: BI BI 4 5 7 3 2 6 7 3 B B B B B DIF = B BI ; B = ( B) BI ( B), shared term ( B) 2. 4 to Multiplexer Chapter., page : The multiplexer will be enabled with ( E) =, so that EN =. The Boolean expression with 4 minterms will contain ( E) as enable signal. 3. Decoder Compare chapter.2, page : here only one enable input, 2 input lines and 4 high active outputs. 4. Priority Encoder Compare chapter.3, page : NY = I I I2 I3 5. Bus Implementation Compare with black board writing concerning end of chapter 2.2 (figure 2., 2.2). If a decoder output is selected (Di = ) then the connected tristate driver (BUFT) will be enabled and Ii is connected directly to the bus Y. ll other tristate drivers are disabled and there outputs are set to the high impedance state (third state). Therefore no conflict will arise between Ii sources. This behaviour can be modelled with VHDL by assigning the value Z to a signal which now may have several drivers but only one is active. This value is available by use of type std_logic/std_logic_vector. If you work with schematic entry you will have to check whether the available tristate driver elements are enabled with an high or low active control input T. S S Y I I I2 I3 E-P
6. Latch: RS-NND I I Y + Y + State Y Y Irregular Reset Set Hold 7. D-latch and D-flip-flop Compare chapter 5. /5.3 During the high level of a clock cycle the gate of a D-latch is enabled. This state of transparency means that input signal changes will be propagated directly to the output. D-flip-flop is edge sensitive so that no state of transparency will occur. The sampling interval t samp and especially the hold time t h is more than ten times smaller than the propagation delay t p from clock edge to D-flip-flop output (t h << t p ). If an output change appears the clock gate is closed for a long time in comparison to the hold time t h and the signal feed back itself will have no influence on its own cause. Therefore oscillating behaviour will be avoided. 8. Moore Finite state machine model block diagram. Compare chapter 4.4. With a Moore FSM the external inputs have no direct effect on the output signals. 9. Simple 2-bit down counter: modulo-4 Q Q Q + Q + RCO Next State Forming Logic Present State Feedback Q + Present State Register CLK Q preset Output Forming Logic RCO State RCO preset 3 2 E-P 2
. D-flip-flop VHDL template Compare chapter 5.3 D_FF: process(clk, PRE) -- asynchronous inputs are dominant over clock begin if PRE ='' then -- asynchronous set, dominant Q <= '' after ns; elsif (CLK'event and CLK ='') then-- rising edge tiggering if EN = '' then Q <= DT after ns; end if;-- else branch is not necessary because of D-FF behaviour end if; end process D_FF;. 2-bit modulo-3 counter VHDL code Compare chapter 5. signal QINT: BIT_VECTOR( downto ); begin SYN_COUNT:process (CLK) -- signals with priority begin if CLK='' and CLK'event then case QINT is -- state/next state representation when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when others => QINT <= "" after ns;-- save counter end case; end if; end process SYN_COUNT; QOUT <= QINT; Exercises. Code converter Compare chapters 2.4 and.4. The left hand side is a copy of table 2.2 with two s complement: C(z) = (z4, z3, z2, z). The second half of the right hand side is calculated with z * = (R m ) C(z) + and z * = (S, a3, a2, a). a = z (LSB) a2 = (z2 z4) ( z z2) (z z2 z4) a3 = (z3 z4) ( z3 z4) ( z z2 z3) S = z4 (MSB) Dec z4 z3 z2 z S a3 a2 a No. 2 2 3 3 4 4 5 5 6 6 7 7 5-4 -2 3-3 2-4 -5-6 9-7 8 X X X X -8 E-P 3
2. Controlled adder/subtractor S = : addition ( + B + CI) ; S = subtraction (B CI) S/D = CI B f(s) C/B = (( CI) ( S B)) (CI ) C/B: B B 2 S B 4 5 8 2 4 6 3 5 7 S 9 3 CI CI CI Func. Dec B CI S C/B S/D dd. Sub. dd. 2 Sub 3 dd. 4 Sub. 5 dd. 6 Sub. 7 dd. 8 Sub. 9 dd. Sub. dd. 2 Sub. 3 dd. 4 Sub. 5 3. Multiplexer design Y = (S S2) (S S2) (S S S3) Y: S3 S3 2 S2 S S3 4 5 8 2 4 6 S2 3 5 7 S 9 3 S2 S S CI Dec S3 S2 S S Y Data path No selection I 2 I 3 I & I (5 lines) 4 I2 5 I2 & I (6 lines) 6 I2 & I (7 lines) 7 I2 & I & I ( 9 lines) 8 I3 9 I3 & I (3 lines) I3 & I (4 lines) I3 & I & I (6 lines) 2 I3 & I2 (5 lines) 3 I3 & I2 & I ( 7 lines) 4 I3 & I2 & I (8 lines) 5 I3 & I2 & I & I ( lines) E-P 4
4. Modulo-6 counter State reset 2 Dec C B + + C B + 2 3 4 5 6 X X X 7 X X X 5 4 Next state forming logic: + = B + = ( B) ( B C) C + = ( C) ( B) 3 If the counter will be disturbed and a state transition to a pseudo state has taken place then following transitions from pseudo states will occur: Dec C B + + C B + 6 7 Starting from pseudo state 7 the counter will reach state 4 with the next clock edge. fter one clock cycle the counter will return to the correct counting sequence. Starting from pseudo state 6 the counter will step to pseudo state 7 and then will reach the correct counting sequence. Two clock cycles are necessary to return. 5. Modulo-8 counter with minimum bit change sequence: Dec No. Q3 Q2 Q Q Q3 + Q2 + Q + Q + 3 2 7 3 5 4 4 5 2 6 8 7 rest ----- X X X X State/next state table Pseudo states have following decimal equivalent (minterm index): 2, 4, 5, 6, 9,,, 3. They are used as don t care entries (X) to the K-map minimisation for the next state forming logic. Next state forming logic for four D-FF inputs Di of a Johnson counter: Q + = D = Q3 + ; Q + = D = Q; Q2 + = D2 = Q; Q3 + = D3 = Q2 E-P 5
ccording to the next state forming logic equations the D-FF outputs are connected to the inputs of the D-FFs which represent the next higher weight. This counter is also called ring counter because of Q3 feedback to D. This basic structure of a directly coupled D-FF chain is called shift register. The stored bits are shifted from one position to the next when a positive clock edge triggers the D-FFs. The main condition for a successful stepwise shifting is provided by the fact that propagation delay t p is much larger than the sampling interval t samp. The timing waveform shows that a new output value Qi will be stored by following D-FF stage when the next clock edge appears. If D-latches would be applied then data would cycle within a closed loop because of transparency during a clock high level. t plh Transitions from pseudo states of a Johnson counter will always generate next states which don t belong to the proper counting sequence. In order to perform a return to the required counting sequence an additional self-correction circuit has to be connected to a ring counter (compare J. Wakerly: Digital Design. Page 727). Dec No. Q3 Q2 Q Q Q3 + Q2 + Q + Q + 2 --- 5 --- 9 --- E-P 6
6. Controlled modulo-3/modulo-6 counter Dec. No. Q2 Q Q S Q2 + Q + Q +, X 2, 3 X 4 2 5 2 6, 7 3 X 8, 9 4 X, 5 X 2, 3, 4, 5 6, 7 X X X X X State/next state table with a control input S. Three bits are necessary to perform 6 counting states. State S reset X X 2 X X 5 X 4 3 Next state forming logic for three D-FF inputs: Q + = D = (S Q) ( Q Q) ; Q + = D = (S Q Q) (Q Q Q2); Q2 + = D2 = (Q2 Q) (Q Q) Dec. No. Q2 Q Q S Q2 + Q + Q + 2 6 3 6 4 7 5 7 Transitions from pseudo states. The counter will return to the required counting cycle within two clock cycles if pseudo state no. 6 has occured and control bit S is high. In all other cases it takes only one clock cycle to return. The VHDL-code describes a design with a save transition from all pseudo states to the initial state: -- Synchronous 3-bit counter; synchronous reset RESET entity MODULO_3_6 is port (RESET, S,CLK : in BIT; Q: out BIT_VECTOR(2 downto )); end MODULO_3_6 ; architecture COUNTER of MODULO_3_6 is signal QINT: BIT_VECTOR(2 downto ); begin SYN_COUNT:process (CLK, RESET) -- signals with priority begin if RESET = '' then QINT <= "" after ns; elsif CLK='' and CLK'event then case QINT is -- next state forming logic when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when "" => if S = '' then - branch on control bit S QINT <= "" after ns; else QINT <= "" after ns; E-P 7
end if; when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when others => QINT <= "" after ns;-- save counter end case; end if; end process SYN_COUNT; Q <= QINT; end COUNTER; 7. Moore state machine timing With synchronisation D-FFs the probability of metastable states of present state registers will be reduced (compare J. Wakerly: Digital Design. Pages 529 and 764). With the timing waveform it becomes clear that input signals E_VECT may change its value at any time. But after synchronisation signals ESYN always change with clock edge (afer t p ). With each following clock edge the prepared next state will be stored as present state. Therefore the response of state transitions on input signal changes will be delayed by one clock cycle. Present State Feedback Next State Forming Logic S + Present State Register S Output Forming Logic CLK E-P 8
8. Memory element timing a) Give the proper names of both memory elements. b) Which type can be used in FSMs? c) ccomplish the timing diagram with output waveforms. pply qualitative signal delays. E-P 9
9. Modulo-n counter fter a reset the modulo- counter counts up to 9 and RCO becomes high and the load input is low. With the next clock edge a load with (6 dec.) will be performed. fter 3 clock edges a load will be prepared again. Therefore the counter has a periodical sequence of 6 7 8 9 6: Modulo-4 counter. n = number of states input value at IN E-P