DATASHEET EL77 0MHz Non-Inverting Quad CMOS Driver FN788 Rev.00 The EL77 is a high speed, non-inverting, quad CMOS driver. It is capable of running at clock rates up to 0MHz and features A peak drive capability and a nominal on-resistance of just 3. The EL77 is ideal for driving highly capacitive loads, such as storage and vertical clocks in CCD applications. It is also well suited to ATE pin driving, level-shifting, and clock-driving applications. The EL77 is capable of running from single or dual power supplies while using ground referenced inputs. Each output can be switched to either the high (V H ) or low (V L ) supply pins, depending on the related input pin. The inputs are compatible with both 3V and V CMOS and TTL logic. The output enable (OE) pin can be used to put the outputs into a high-impedance state. This is especially useful in CCD applications, where the driver should be disabled during power down. The EL77 also features very fast rise and fall times which are matched to within ns. The propagation delay is also matched between rising and falling edges to within ns. The EL77 is available in -pin QSOP, -pin SO (0.0"), and -pin QFN packages. All are specified for operation over the full -0 C to +8 C temperature range. Pinouts EL77 [-PIN SO (0.0 ), QSOP (0.0 )] TOP VIEW 3 INA OE INB VL VS+ OUTA OUTB NC 3 INB VL VL EL77 [-PIN QFN (XMM)] TOP VIEW 3 OE INA VS+ THERMAL PAD* OUTA 3 OUTB VH 0 VH Features Clocking speeds up to 0MHz channels ns t R /t F at 000pF C LOAD ns rise and fall time match.ns prop delay match Low quiescent current - <ma Fast output enable function - ns Wide output voltage range 8V V L -V -V V H.V A peak drive 3 on resistance Input level shifters TTL/CMOS input-compatible Pb-free (RoHS compliant) Applications CCD drivers Digital cameras Pin drivers Clock/line drivers Ultrasound transducer drivers Ultrasonic and RF generators Level shifting GND VH GND 9 OUTC NC OUTC 7 8 7 INC OUTD 0 INC IND VS- OUTD 8 IND VS- 9 * THERMAL PAD CONNECTED TO PIN 7 (V S -) FN788 Rev.00 Page of
Ordering Information PART NUMBER (Notes, 3) PART MARKING TEMP. RANGE ( C) PACKAGE (Pb-free) PKG. DWG. # EL77CUZ 77CUZ -0 C to +8 C Ld QSOP (0.0 ) MDP000 EL77CUZ-T3 (Note ) 77CUZ -0 C to +8 C Ld QSOP (0.0 ) MDP000 EL77CUZ-T7 (Note ) 77CUZ -0 C to +8 C Ld QSOP (0.0 ) MDP000 EL77CUZ-T7A (Note ) 77CUZ -0 C to +8 C Ld QSOP (0.0 ) MDP000 EL77CSZ EL77CSZ -0 C to +8 C Ld SO (0.0 ) MDP007 EL77CSZ-T3 (Note ) EL77CSZ -0 C to +8 C Ld SO (0.0 ) MDP007 EL77CSZ-T7 (Note ) EL77CSZ -0 C to +8 C Ld SO (0.0 ) MDP007 EL77CSZ-T7A (Note ) EL77CSZ -0 C to +8 C Ld SO (0.0 ) MDP007 EL77CLZ 77CLZ -0 C to +8 C Ld QFN (xmm) L.XH EL77CLZ-T3 (Note ) 77CLZ -0 C to +8 C Ld QFN (xmm) L.XH EL77CLZ-T7 (Note ) 77CLZ -0 C to +8 C Ld QFN (xmm) L.XH EL77CLZ-T7A (Note ) 77CLZ -0 C to +8 C Ld QFN (xmm) L.XH NOTES:. Please refer to TB37 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 00% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-00. 3. For Moisture Sensitivity Level (MSL), please see device information page for EL77. For more information on MSL please see tech brief TB33. FN788 Rev.00 Page of
Absolute Maximum Ratings (T A = C) Supply Voltage (V S + to V S -)...........................+8V Input Voltage..........................V S - -0.3V, V S + +0.3V Continuous Output Current.......................... 00mA Storage Temperature Range..................- C to +0 C Thermal Information Thermal Resistance JA ( C/W) JC ( C/W) Ld QFN (Notes, )............ 3 Ld SOIC (Notes, 7)............ 73 Ld QSOP (Note ).............. N/A Ambient Operating Temperature................-0 C to +8 C Maximum Die Temperature.......................... + C Power Dissipation............................. See Curves Pb-Free Reflow Profile.........................see link below http://www.intersil.com/pbfree/pb-freereflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES:. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB379.. For JC, the case temp location is the center of the exposed metal pad on the package underside.. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the case temp location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +V, V S - = -V, V H = +V, V L = -V, T A = C, unless otherwise specified. PARAMETER DESCRIPTION CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT INPUT V IH Logic Input Voltage.0 V I IH Logic Input Current V IH = V 0. 0 µa V IL Logic 0 Input Voltage 0.8 V I IL Logic 0 Input Current V IL = 0V 0. 0 µa C IN Input Capacitance 3. pf R IN Input Resistance 0 M OUTPUT R OH ON Resistance V H to OUTx I OUT = -00mA. R OL ON Resistance V L to OUTx I OUT = +00mA I LEAK Output Leakage Current V H = V S +, V L = V S - 0. 0 µa I PK Peak Output Current Source.0 A Sink.0 A POWER SUPPLY I S Power Supply Current Inputs = V S + 0.. ma SWITCHING CHARACTERISTICS t R Rise Time C L = 000pF 3. ns t F Fall Time C L = 000pF 3 ns t RF t R, t F Mismatch C L = 000pF 0. ns t D + Turn-Off Delay Time C L = 000pF. ns t D - Turn-On Delay Time C L = 000pF. ns t DD t D- - t D- Mismatch C L = 000pF ns t ENABLE Enable Delay Time ns FN788 Rev.00 Page 3 of
Electrical Specifications V S + = +V, V S - = -V, V H = +V, V L = -V, T A = C, unless otherwise specified. PARAMETER DESCRIPTION CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT t DISABLE Disable Delay Time ns Electrical Specifications V S + = +V, V S - = 0V, V H = +V, V L = 0V, T A = C, unless otherwise specified PARAMETER DESCRIPTION CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT INPUT V IH Logic Input Voltage. V I IH Logic Input Current V IH = V 0. 0 µa V IL Logic 0 Input Voltage 0.8 V I IL Logic 0 Input Current V IL = 0V 0. 0 µa C IN Input Capacitance 3. pf R IN Input Resistance 0 M OUTPUT R OH ON Resistance V H to OUT I OUT = -00mA 3. R OL ON Resistance V L to OUT I OUT = +00mA 3 I LEAK Output Leakage Current V H = V S +, V L = V S - 0. 0 µa I PK Peak Output Current Source.0 A Sink.0 A POWER SUPPLY I S Power Supply Current Inputs = V S + 0.8 ma SWITCHING CHARACTERISTICS t R Rise Time C L = 000pF ns t F Fall Time C L = 000pF ns t RF t R, t F Mismatch C L = 000pF ns t D + Turn-Off Delay Time C L = 000pF. ns t D - Turn-On Delay Time C L = 000pF 3 ns t DD t D- - t D- Mismatch C L = 000pF. ns t ENABLE Enable Delay Time ns t DISABLE Disable Delay Time ns NOTE: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN788 Rev.00 Page of
Typical Performance Curves.8 T= C HIGH LIMIT=.V T= C INPUT VOLTAGE (V)... HYSTERESIS SUPPLY CURRENT (V).. 0.8 0. ALL INPUTS=0 ALL INPUTS=V S + LOW LIMIT=0.8V 7 0 0 7 0 SUPPLY VOLTAGE (V) FIGURE. SWITCH THRESHOLD vs SUPPLY VOLTAGE SUPPLY VOLTAGE (V) FIGURE. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 9 8 I OUT =00mA T= C ON RESISTANCE ( ) 7 V L TO OUT V H TO OUT RISE/FALL TIME (ns) 0 0 t R t F 3 7 0 C L =000pF T= C 7 0 SUPPLY VOLTAGE (V) FIGURE 3. ON RESISTANCE vs SUPPLY VOLTAGE SUPPLY VOLTAGE (V) FIGURE. RISE/FALL TIME vs SUPPLY VOLTAGE RISE/FALL TIME (ns) 0 8 C L =000pF V S +=V t R t F DELAY TIME (ns) 0 0 C L =000pF t D t D -0-0 0 7 00 TEMPERATURE ( C) FIGURE. RISE/FALL TIME vs TEMPERATURE 7 0 SUPPLY VOLTAGE (V) FIGURE. PROPAGATION DELAY vs SUPPLY VOLTAGE FN788 Rev.00 Page of
Typical Performance Curves (Continued) 8 C L =000pF V S +=V 0 0 V S +=V DELAY TIME (ns) 0 8 t D t D RISE/FALL TIME (ns) 00 80 0 0 0 t F t R -0-0 0 7 00 TEMPERATURE ( C) FIGURE 7. PROPAGATION DELAY vs TEMPERATURE 0 00 70 K.K.7K 0K LOAD CAPACITANCE (pf) FIGURE 8. RISE/FALL TIME vs LOAD SUPPLY CURRENT (ma) 0 8 V S +=V H =0V V S -=V L =0V f=00khz 0 00 K 0K LOAD CAPACITANCE (pf) FIGURE 9. SUPPLY CURRENT PER CHANNEL vs CAPACITIVE LOAD FN788 Rev.00 Page of
TABLE. NOMINAL OPERATING VOLTAGE RANGE PIN MIN MAX V S + to V S - V.V V S - to GND -V 0V V H V S - +.V V S + V L V S - V S + V H to V L 0V.V Timing Diagram V INPUT.V 0 OUTPUT 90% 0% V L to V S - 0V 8V t D + t R t D - t F Standard Test Configuration (CS/CU) VS+ 0.µF.7µF VS+ 0k INA EN 000pF OUTA INB VL.7µF 0.µF 3 3 000pF 0.µF OUTB VH.7µF INC 7 0 000pF OUTC IND 8 9 000pF OUTD 0.µF.7µF VS- FN788 Rev.00 Page 7 of
Pin Descriptions -PIN QSOP (0.0 ), SO (0.0 ) -PIN QFN (xmm) NAME FUNCTION EQUIVALENT CIRCUIT INA Input channel A V S + V S + INPUT V S - V S - CIRCUIT OE Output Enable (Reference Circuit ) 3 INB Input channel B (Reference Circuit ), 3 VL Low voltage input pin GND Input logic ground, 3 NC No connection 7 INC Input channel C (Reference Circuit ) 8 IND Input channel D (Reference Circuit ) 9 7 VS- Negative supply voltage 0 8 OUTD Output channel D V H V S + OUTPUT V S - V S - CIRCUIT V L 9 OUTC Output channel C (Reference Circuit ) 0, VH High voltage input pin OUTB Output channel B (Reference Circuit ) 3 OUTA Output channel A (Reference Circuit ) VS+ Positive supply voltage FN788 Rev.00 Page 8 of
Block Diagram OE V H V S + INPUT GND LEVEL SHIFTER 3-STATE CONTROL OUTPUT V S - V L Applications Information Product Description The EL77 is a high performance 0MHz high speed quad driver. Each channel of the EL77 consists of a single P-channel high side driver and a single N-channel low side driver. These 3 devices will pull the output (OUT X ) to either the high or low voltage, on V H and V L respectively, depending on the input logic signal (IN X ). It should be noted that there is only one set of high and low voltage pins. A common output enable (OE) pin is available on the EL77. This pin, when pulled low will put all outputs in to the high impedance state. The EL77 is available in -pin SO (0.0"), -pin QSOP, and ultra-small -pin QFN packages. The relevant package should be chosen depending on the calculated power dissipation. Supply Voltage Range and Input Compatibility The EL77 is designed for operation on supplies from V to V with 0% tolerance (i.e..v to 8V). The table on page shows the specifications for the relationship between the V S +, V S -, V H, V L, and GND pins. The EL77 does not contain a true analog switch and therefore V L should always be less than V H. All input pins are compatible with both 3V and V CMOS signals With a positive supply (V S +) of V, the EL77 is also compatible with TTL inputs. Power Supply Bypassing When using the EL77, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL77 necessitate the use of a bypass capacitor on both the positive and negative supplies. It is recommended that a.7µf tantalum capacitor be used in parallel with a 0.µF low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the V H and V L pins have some level of bypassing, especially if the EL77 is driving highly capacitive loads. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL77 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below T JMAX ( C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated: PD = V S I S + C INT V S f + C L V OUT f (EQ. ) where: V S is the total power supply to the EL77 (from V S + to V S -) V OUT is the swing on the output (V H - V L ) C L is the load capacitance C INT is the internal load capacitance (80pF max) I S is the quiescent supply current (3mA max) f is frequency Having obtained the application s power dissipation, the maximum junction temperature can be calculated: where: T JMAX = T MAX + JA PD (EQ. ) T JMAX is the maximum junction temperature ( C) T MAX is the maximum ambient operating temperature PD is the power dissipation calculated above JA is the thermal resistance, junction to ambient, of the application (package + PCB combination). Refer to the Package Power Dissipation curves on page. FN788 Rev.00 Page 9 of
Quarter Size Outline Plastic Packages Family (QSOP) A N D (N/)+ MDP000 QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP QSOP QSOP8 TOLERANCE NOTES E E PIN # I.D. MARK A 0.08 0.08 0.08 Max. - A 0.00 0.00 0.00 ±0.00 - A 0.0 0.0 0.0 ±0.00 - b 0.00 0.00 0.00 ±0.00 - B 0.00 C A B (N/) c 0.008 0.008 0.008 ±0.00 - D 0.93 0.3 0.390 ±0.00, 3 E 0.3 0.3 0.3 ±0.008 - C SEATING PLANE 0.00 C e 0.007 C A B b H E 0. 0. 0. ±0.00, 3 e 0.0 0.0 0.0 Basic - L 0.0 0.0 0.0 ±0.009 - L 0.0 0.0 0.0 Basic - N 8 Reference - c L SEE DETAIL "X" A Rev. F /07 NOTES:. Plastic or metal protrusions of 0.00 maximum per side are not included.. Plastic interlead protrusions of 0.00 maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M-99. A GAUGE PLANE 0.00 A DETAIL X L ± Copyright Intersil Americas LLC 00-0. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN788 Rev.00 Page 0 of
Small Outline Package Family (SO) A D h X N (N/)+ E E PIN # I.D. MARK c A SEE DETAIL X B 0.00 M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE 0.00 0.00 C 0.00 M C A B b A DETAIL X L ± MDP007 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO SO (0.300 ) SO0 SO SO8 SYMBOL SO-8 SO- (0.0 ) (SOL-) (SOL-0) (SOL-) (SOL-8) TOLERANCE NOTES A 0.08 0.08 0.08 0.0 0.0 0.0 0.0 MAX - A 0.00 0.00 0.00 0.007 0.007 0.007 0.007 0.003 - A 0.07 0.07 0.07 0.09 0.09 0.09 0.09 0.00 - b 0.07 0.07 0.07 0.07 0.07 0.07 0.07 0.003 - c 0.009 0.009 0.009 0.0 0.0 0.0 0.0 0.00 - D 0.93 0.3 0.390 0.0 0.0 0.0 0.70 0.00, 3 E 0.3 0.3 0.3 0.0 0.0 0.0 0.0 0.008 - E 0. 0. 0. 0.9 0.9 0.9 0.9 0.00, 3 e 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Basic - L 0.0 0.0 0.0 0.030 0.030 0.030 0.030 0.009 - L 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Basic - h 0.03 0.03 0.03 0.00 0.00 0.00 0.00 Reference - N 8 0 8 Reference - Rev. M /07 NOTES:. Plastic or metal protrusions of 0.00 maximum per side are not included.. Plastic interlead protrusions of 0.00 maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M-99 FN788 Rev.00 Page of
Package Outline Drawing L.xH LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, /.0 X.9 PIN INDEX AREA.00 A B 3 X 0. PIN # INDEX AREA.00.0 9 (X) 0. TOP VIEW x 0.0±0.0 8 BOTTOM VIEW 0.0 M C 0.30 ±0.0 AB 0.90±0.0 SEE DETAIL "X" 0.0 C C BASE PLANE ( 3. TYP ) SIDE VIEW SEATING PLANE (.0) (x0.) TYPICAL RECOMMENDED LAND PATTERN (x0.30) (x0.7) C 0. 0 REF +0.03/-0.0 DETAIL "X" NOTES:.. 3.... Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y.m-99. Unless otherwise specified, tolerance : Decimal ± 0.0 Dimension applies to the metallized terminal and is measured between 0.mm and 0.30mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. FN788 Rev.00 Page of