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Principles Of Digital Design Sequential logic and design Analysis State-based (Moore) Input-based (Mealy) FSM definition Synthesis State minimization Encoding Optimization and timing Copyright 20-20by Daniel D. Gajski

Analysis of sequential logic Excitation equations are Boolean expressions of the flip-flop inputs. Next-state equations are Boolean expressions representing the next value of the flip- flop outputs. Next-state table ( similar to next-state equations ) gives the next value of flip-flop outputs for each input value and state of flip-flops. Analysis of a sequential circuit is a procedure that produces the nextstate table, state diagram and timing diagram from the logic schematic of the circuit. The analysis gives the answer to the following questions: (a) What is the next state? (b) What is the output? (c) What is the function of the schematic? Copyright 20-20by Daniel D. Gajski 2

Analysis of a sequential circuit Example: Modulo-4 counter Problem: Derive the state table & state diagram for the circuit given below. Cnt Logic schematic State diagram State table D 0 Q 0 Q 0 Q 0 = Q 0 = PRESENT STATE Q 0 NEXT STATE (next) Q 0 (next) D 1 Q 0 = Q 0 = Clock cycle 1 Clock cycle 2 Clock cycle 3 Clock cycle 4 D 0 = Cnt Q 0 = Cnt Q 0 + Cnt Q 0 D 1 = Cnt + Cnt Q 0 + Cnt Q 0 Cnt Excitation equation Q 0 (next) = D 0 = Cnt Q 0 + Cnt Q 0 Q 0 (next) = D 1 = Cnt + Cnt Q 0 + Cnt Q 0 Next-state equation t 0 t 1 t 2 t 3 t 4 t 5 Timing diagram Copyright 20-20by Daniel D. Gajski 3

Analysis of a modulo-4 counter Example: Modulo-4 counter (state-based, Moore-type) Problem: Derive the state, output tables and the state diagram for the circuit below. Cnt D 0 Q 0 Q 0 D 0 = Cnt Q 0 = Cnt Q 0 + Cnt Q 0 D 1 = Cnt + Cnt Q 0 + Cnt Q 0 Excitation equation D 1 Logic schematic Q 0 (next) = D 0 = Cnt Q 0 + Cnt Q 0 (next) = D 1 = Cnt + Cnt Q 0 + Cnt Q 0 = Q 0 PRESENT STATE Q 0 NEXT STATE (next) Q 0 (next) OUTPUTS Next-state and output equation 0 0 0 1 State and output table Copyright 20-20by Daniel D. Gajski 4

Analysis of a modulo-4 counter Example: Modulo-4 counter (state-based, Moore-type) Problem: Derive the state, output tables and the state diagram for the circuit below. Cnt Logic schematic State diagram D 0 Q 0 Q 0 = =0 Q 0 = =0 Q 0 D 1 Q 0 = =1 Q 0 = =0 PRESENT STATE NEXT STATE OUTPUTS Cnt Q 0 (next) Q 0 (next) 0 0 Q 0 0 1 State and output table Copyright 20-20by Daniel D. Gajski 5 t 0 t 1 t 2 t 3 t 4 t 5 Timing diagram

Analysis of a modulo-4 counter Example: Modulo-4 counter (input-based, Mealy-type) Problem: Derive the state/output table and the state diagram for the circuit below. Cnt D 0 Q 0 Q 0 D 0 = Cnt Q 0 = Cnt Q 0 + Cnt Q 0 D 1 = Cnt + Cnt Q 0 + Cnt Q 0 Excitation equation D 1 Logic schematic Q 0 (next) = D 0 = Cnt Q 0 + Cnt Q 0 (next) = D 1 = Cnt + Cnt Q 0 + Cnt Q 0 PRESENT STATE Q 0 NEXT STATE /OUTPUTS (next) Q 0 (next)/ / 0 / 0 / 0 / 0 / 0 / 0 / 0 / 1 = Cnt Q 0 Next-state and output equation State and output table Copyright 20-20by Daniel D. Gajski 6

Analysis of a modulo-4 counter Example: Modulo-4 counter (input-based, Mealy-type) Problem: Derive the state/output table and the state diagram for the circuit below. Cnt D 0 Q 0 /=0 /=0 /=0 Q 0 = Q 0 = Q 0 /=1 /=0 /=0 /=0 Q 0 = /=0 Q 0 = D 1 State diagram Logic schematic Cnt Clock cycle 1 Clock cycle 2 Clock cycle 3 Clock cycle 4 PRESENT STATE Q 0 NEXT STATE /OUTPUTS (next) Q 0 (next)/ / 0 / 0 / 0 / 0 State and output table Copyright 20-20by Daniel D. Gajski / 0 / 0 / 0 / 1 7 Q 0 t 0 t 1 t 2 t 3 t 4 t 5 Timing diagram

Analysis procedure for sequential circuits Logic schematic Derive excitation equations 1 Derive next-state and output equations 2 Generate next-state and output tables 3 Generate FSM diagram 4 Develop timing diagram 5 Simulate logic schematic 6 Copyright 20-20by Daniel D. Gajski 8

Finite-state machine model I A 1 Q 0,, Q m 1 O A k n The FSM can be defined abstractly as the quintuple < S, I, O, f, h> where S, I, and O represent a set of states, set of inputs and a set of outputs, respectively, and f and h represent the next-state and the output functions, that is f : S x I S h : S x I O ( Mealy-type ) S O ( Moore-type ) where S = x Q 2 x x Q m, I = A 1 x A 2 x x A k, O = 1 x 2 x x n, Copyright 20-20by Daniel D. Gajski 9

FSM definition of modulo-4 counter Example: Modulo-4 counter (state-based, Moore-type) Problem: Derive the state, output tables and the FSM diagram for the circuit below. Cnt Logic schematic Stay FSM diagram Stay D 0 Q 0 S 0 Up S 1 Q 0 = Q 0 = Q 0 Up No No Up Stay Stay D 1 S 3 Q 0 = Up S 2 Q 0 = es No S = {S 0, S 1, S 2, S 3 } I = {Up, Stay} O = {es, No} PRESENT STATE Q 0 NEXT STATE (next) Q 0 (next) OUTPUTS 0 0 0 1 PRESENT STATE S 0 S 1 S 2 S 3 NEXT STATE ( SxI S ) Stay S 0 S 1 Up S 1 S 2 S 2 S 3 S 3 S 0 OUTPUTS (S O) No No No es State and output table FSM table Copyright 20-20by Daniel D. Gajski

FSM definition of modulo-4 counter Example: Modulo-4 counter (input-based, Mealy-type) Problem: Derive the state/output table and the FSM diagram for the circuit below. Cnt Logic schematic FSM diagram Stay/No Stay/No S 0 Up/No S 1 D 0 Q 0 Q 0 = Q 0 = Q 0 Up/es Up/No Stay/No S 3 Up/No S 2 Stay/No D 1 Q 0 = Q 0 = S = {S 0, S 1, S 2, S 3 } I = {Up, Stay} O = {es,no} PRESENT STATE Q 0 NEXT STATE /OUTPUTS (next) Q 0 (next)/ / 0 / 0 / 0 / 0 / 0 / 0 / 0 / 1 PRESENT STATE S 0 S 1 S 2 S 3 NEXT STATE(SxI S)/ OUTPUT(SxI O) Stay S 0 /No S 1 /No S 2 /No S 3 /No Up S 1 /No S 2 /No S 3 /No S 0 /es State and output table Copyright 20-20by Daniel D. Gajski FSM table

Finite-state-machine implementations Input signals A 1 A 2 A k... Input signals A 1 A 2 A k...... FF 1 FF 1 FF 2 f : SxI S h : S O Q 2. State. register.... 1 2 Output signals n FF 2 f : SxI S h : SxI O Q 2. State. register. Q m... 1 2 Output signals n Comb. logic FF m Q m Comb logic Comb. logic FF m Comb. logic State signals State-based (Moore) Input-based (Mealy) Copyright 20-20by Daniel D. Gajski 12

Synthesis procedure for sequential logic Design description Develop FSM diagram Generate next-state and output tables Minimize states Encode inputs, states, outputs Derive next-state and output equations Choose memory elements Derive excitation equations Optimize logic implementation Derive schematic and timing diagrams Simulate logic schematic Verify functionality and timing Copyright 20-20by Daniel D. Gajski 13

State diagram for a modulo-3 up/down counter Example: Modulo-3 up-down counter Problem: Derive the FSM diagram for an up-down, modulo-3 counter. The counter has two inputs: count enable (C) and count direction (D). When C=1, the counter will count in the direction specified by D, and it will stop counting when C=0. the counter will count up when D=0 and down when D=1. The counter has one output which will be asserted when the counter reaches 2 while counting up, or when it reaches 0 while counting down. CD= Counter symbol D C Modulo-3 up/down counter CD= CD= u 0 u 1 u 2 CD= CD= d 0 d 1 d 2 Partial state diagram (up and down counting) CD= CD= CD= CD=0X CD=0X CD=0X Partial state diagram (changing direction) CD= u 0 u 1 u 2 CD= CD= CD= CD= CD= CD= CD= CD= CD= d 0 d 1 d 2 CD= CD= u 0 u 1 u 2 CD= CD= CD= CD= CD= CD= CD= CD= d 0 d 1 d 2 Final state diagram CD=0X CD=0X CD=0X Copyright 20-20by Daniel D. Gajski CD= 14 CD=

State minimization State minimization reduces the number of states, and therefore, number of flip-flops needed to implemented the circuit. State minimization is based on the concept of behavioral equivalence which states that two states are equivalent if they produce the same sequence of output symbols for every sequence of input symbols. More formally, two states, s j and s k in an FSM are said to be equivalent, s j s k, iff the following two conditions are true. Condition 1: Both states s j and s k produce the same output symbol for every input symbol i: that is, h (s j, i ) = h (s k, i ); Condition 2: Both states have equivalent next sates for every input symbol i : that is, f (s j, i ) = f (s k, i ); Minimization procedure: 1. partition states into equivalence classes 2. construct new FSM with one state for each equivalence class Copyright 20-20by Daniel D. Gajski 15

State reduction for modulo-3 counter Example: State reduction Problem: Derive the minimal-state FSM for the modulo-3 counter. PRESENT NEXT STATE / OUTPUT STATE CD=0X CD= CD= u 0 u 0 / 0 u 1 / 0 d 2 / 1 u 1 u 1 / 0 u 2 / 0 d 0 / 0 u 2 u 2 / 0 u 0 / 1 d 1 / 0 d 0 d 0 / 0 u 1 / 0 d 2 / 1 d 1 d 1 / 0 u 2 / 0 d 0 / 0 d 2 / 0 u 0 / 1 d 1 / 0 d 2 Initial next-state/output table CD= CD=0X CD=0X CD=0X Partition into arrays with the same output Partition into arrays with the same next state ( u 0, u 1, u 2, d 0, d 1, d 2 ) CD = 0X 1 1 1 1 CD = 0X 1 G 0 = (u 0, d 0 ) G 1 = (u 1, d 1 ) G 2 = (u 2, d 2 ) G 0 G 0 G 1 G 1 G 2 G 2 G 1 G 1 G 2 G 2 G 0 G 0 G 2 G 2 G 0 G 0 G 1 G 1 Partitioning into equivalence classes Output values Next states CD= u 0 u 1 u 2 CD= CD= CD= CD= CD= CD= CD= CD= CD= d 0 d 1 d 2 PRESENT STATE G 0 G 1 G 2 NEXT STATE / OUTPUT CD=0X CD= CD= G 0 / 0 G 1 / 0 G 2 / 1 G 1 / 0 G 2 / 0 G 0 / 0 G 2 / 0 G 0 / 1 G 1 / 0 CD=0X CD=0X CD=0X Copyright 20-20by Daniel D. Gajski CD= 16 Final next-state/output table

State reduction with implication table Example: State reductions with implication table. Problem: Find the minimal number of states for the FSM specified by the table below. s 1 s 2 s 3 s 4 s 5 s 6 Step 1: Step2: Step3: Step4: <s 3,s 4 > <s 2,s 6 > <s 0,s 4 > s 0 s 1 s 2 s 3 s 4 s 5 Implication table Enter x for any pair of states that differ in output values Enter implied equivalent states for every pair of states Enter x for the non equivalent next-state pair Form equivalence classes using transitivity : s 1 s 2 & s 2 s 3 => s 1 s 3 PRESENT NEXT STATE STATE CD=0X CD= CD= u 0 u 0 / 0 u 1 / 0 d 2 / 1 u 1 u 0 / 0 u 2 / 0 d 0 / 0 u 2 u 2 / 0 u 0 / 1 d 1 / 0 d 0 d 0 / 0 u 1 / 0 d 2 / 1 d 1 d 2 / 0 u 2 / 0 d 0 / 0 d 2 / 0 u 0 / 1 d 1 / 0 d 2 Equivalence classes: <u 0, d 0 > <u 1 > <d 1 > <u 2, d 2 > u 1 u 2 d 0 d 1 d 2 Next-state and output table u 0 <u 0,d 2 > u 1 u 2 d 0 d 1 Implication table for the table above Copyright 20-20by Daniel D. Gajski 17

State encoding ENCODING NUMBER 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20 21 22 23 24 s 0 s 1 s 2 s 3 The cost and delay of FSM implementation depends on encoding of symbolic states. For example, four states can be encoded in 4!=24 different ways. There are more than n! different encodings for n states. Exploration of all encodings is impossible Thus, we use different heuristics such as minimum-bit change prioritized adjacency one-hot encoding others Copyright 20-20by Daniel D. Gajski 24 encodings of four states 18

Minimum-bit change Minimum-bit change strategy assigns codes to states so that the total number of bit changes for all state transitions is minimized. In other words, if every arc in the state diagram has a weight that is equal to the number of bits by which the source and destination encodings differ, then the optimal encoding would be the one that minimizes the sum of all these weights. Example: Two different encodings for modulo-4 binary counter. 1 1 2 2 1 1 1 1 s0 s0 Straightforward encoding Minimum-bit-change encoding Copyright 20-20by Daniel D. Gajski 19

Encoding example Example: Comparison of state encodings for modulo-3 counter. Encoding A = Minimum-bit change Encoding B = Simplified output logic Encoding C = Hot-one encoding Problem: For the modulo-3 counter find the encoding that minimizes the cost and delay. PRESENT STATE s 0 s 1 s 2 NEXT STATE / OUTPUT CD=0X CD= CD= s 0 / 0 s 1 / 0 s 2 / 0 s 1 / 0 s 2 / 0 s 0 / 1 Final next-state/output table s 2 / 1 s 0 / 0 s 1 / 0 STATE s 0 s 1 s 2 ENCODING A ENCODING B ENCODING C Q 0 Q 0 Q 2 Q 0 1 0 1 Possible state encodings for modulo-3 counter DELAS & COST C,D to to C,D to Copyright 20-20by Daniel D. Gajski ENCODING A ENCODING B ENCODING C 8.0 9.6 7.6 8.0 9.2 7.2 7.6 9.2 7.2 to.0.0 9.6 Cost 92 90 2 20 (next) = C +Q 0 CD + Q 0 CD Q 0 (next) = Q 0 C + CD+ Q 0 CD = CD + Q 0 CD (next) = C +Q 0 CD+ Q 0 C D Q 0 (next) = Q 0 C + CD + Q 0 CD = CD+ CD Q 2 (next) = Q 2 C +Q 0 CD+ CD (next) = C +Q 2 CD+Q 0 CD Q 0 (next) = Q 0 C +Q 2 CD + CD = Q 0 CD+Q 2 CD

C D Optimization and timing Logic schematic 1.4 D 1 2.2 4.0 Input-output delays Delay table 1.4 2.2 1.4 C, D to to C,D to to 6.0 7.6 5.6 8.0 D 0 Q 0 C D 2.2 4.0 Q 0 Q 0 4.0 4.0 4.0 4.0 4.0 4.0 7.6 7.6 5.6 7.6 t 0 t 1 t 2 t 3 t 4 t 5 t 6 Timing diagram 21 Copyright 20-20by Daniel D. Gajski

C D Optimization and timing 1.4 2.2 D 1 4.0 2.2 1.4 Input-output delays C, D to 6.0 to 7.6 C,D to 5.6 to 8.0 Delay table 1.4 2.2 D 0 Q 0 4.0 Q 0 D 1.4 D 1 Input-output delays C, D to to C,D to Z to Delay table 6.0 7.6.2 13.6 2.2 1.4 2.2 4.0 D 0 Q 0 4.0 Q 0 2.2 1.4 Z Copyright 20-20by Daniel D. Gajski 22

Summary We described procedures for sequential logic Analysis Synthesis with FSM capture state minimization state encoding optimization and timing We defined the FSM model and synthesis from FSM Copyright 20-20by Daniel D. Gajski 23

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