Logic-Leve Gate Drive dvanced Process Technoogy Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fuy vaanche Rated Description Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve the owest possibe on-resistance per siicon area This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient device for use in a wide variety of appications G PD - 9357C IRLZ24N HEXFET Power MOSFET D S V DSS = 55V R DS(on) = 0 06Ω I D = 8 The TO-220 package is universay preferred for a commercia-industria appications at power dissipation eves to approximatey 50 watts The ow therma resistance TO-220B and ow package cost of the TO-220 contribute to its wide acceptance throughout the industry bsoute Maximum Ratings Parameter Max Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 8 I D @ T C = 00 C Continuous Drain Current, V GS @ 0V 3 I DM Pused Drain Current 72 P D @T C = 25 C Power Dissipation 45 W Linear Derating Factor 0 30 W/ C V GS Gate-to-Source Votage ±6 V E S Singe Puse vaanche Energy 68 mj I R vaanche Current E R Repetitive vaanche Energy 4 5 mj dv/dt Peak Diode Recovery dv/dt ƒ 5 0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Sodering Temperature, for 0 seconds 300 ( 6mm from case) Mounting torque, 6-32 or M3 screw 0 bf in ( N m) Therma Resistance Parameter Min Typ Max Units R θjc Junction-to-Case 3 3 R θcs Case-to-Sink, Fat, Greased Surface 0 50 C/W R θj Junction-to-mbient 62 07/2/02
Eectrica Characteristics @ T J = 25 C (uness otherwise specified) Parameter Min Typ Max Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 55 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Votage Temp Coefficient 0 06 V/ C Reference to 25 C, I D = m 0 060 V GS = 0V, I D = R DS(on) Static Drain-to-Source On-Resistance 0 075 Ω V GS = 5 0V, I D = 0 05 V GS = 4 0V, I D = 9 0 V GS(th) Gate Threshod Votage 0 2 0 V V DS = V GS, I D = 250µ g fs Forward Transconductance 8 3 S V DS = 25V, I D = I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 00 V GS = 6V n Gate-to-Source Reverse Leakage -00 V GS = -6V Q g Tota Gate Charge 5 I D = Q gs Gate-to-Source Charge 3 7 nc V DS = 44V Q gd Gate-to-Drain ("Mier") Charge 8 5 V GS = 5 0V, See Fig 6 and 3 t d(on) Turn-On Deay Time 7 V DD = 28V t r Rise Time 74 I D = ns t d(off) Turn-Off Deay Time 20 R G = 2Ω, V GS = 5 0V t f Fa Time 29 R D = 2 4Ω, See Fig 0 Between ead, L D Interna Drain Inductance 4 5 6mm (0 25in ) nh from package L S Interna Source Inductance 7 5 and center of die contact C iss Input Capacitance 480 V GS = 0V C oss Output Capacitance 30 pf V DS = 25V C rss Reverse Transfer Capacitance 6 ƒ = 0MHz, See Fig 5 G D S Source-Drain Ratings and Characteristics Parameter Min Typ Max Units Conditions I S Continuous Source Current MOSFET symbo 8 (Body Diode) showing the G I SM Pused Source Current integra reverse 72 (Body Diode) p-n junction diode V SD Diode Forward Votage 3 V T J = 25 C, I S =, V GS = 0V t rr Reverse Recovery Time 60 90 ns T J = 25 C, I F = Q rr Reverse RecoveryCharge 30 200 nc di/dt = 00/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) D S Notes: Repetitive rating; puse width imited by max junction temperature ( See fig ) V DD = 25V, starting T J = 25 C, L = 790µH R G = 25Ω, I S = (See Figure 2) ƒ I SD, di/dt 290/µs, V DD V (BR)DSS, T J 75 C Puse width 300µs; duty cyce 2%
I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V 0V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH 0. T J = 25 C 0. 0 00 V DS, Drain-to-Source Votage (V) I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V 0V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH 0. T J = 75 C 0. 0 00 V DS, Drain-to-Source Votage (V) Fig Typica Output Characteristics Fig 2 Typica Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J T = 75 C J V DS= 5V 20µs PULSE WIDTH 0. 2 3 4 5 6 7 8 9 0 V GS, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) 3.0 2.5 2.0.5.0 0.5 I D = 8 V GS = 0V 0.0-60 -40-20 0 20 40 60 80 00 20 40 60 80 T J, Junction Temperature ( C) Fig 3 Typica Transfer Characteristics Fig 4 Normaized On-Resistance Vs Temperature
C, Capacitance (pf) 800 600 400 200 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd C oss = C ds Cgd C iss C oss C rss V GS, Gate-to-Source Votage (V) 5 2 9 6 3 I D = V DS = 44V V DS = 28V 0 0 00 V DS, Drain-to-Source Votage (V) 0 FOR TEST CIRCUIT SEE FIGURE 3 0 4 8 2 6 20 Q, Tota Gate Charge (nc) G Fig 5 Typica Capacitance Vs Drain-to-Source Votage Fig 6 Typica Gate Charge Vs Gate-to-Source Votage I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J V GS = 0V 0.4 0.8.2.6 2.0 V SD, Source-to-Drain Votage (V) I D, Drain Current () 000 OPERTION IN THIS RE LIMITED BY RDS(on) 00 0µs 0 00µs T C = 25 C ms T J = 75 C Singe Puse 0ms 0 00 V DS, Drain-to-Source Votage (V) Fig 7 Typica Source-Drain Diode Forward Votage Fig 8 Maximum Safe Operating rea
20 V DS R D I D, Drain Current (mps) 6 2 8 4 0 25 50 75 00 25 50 75 T C, Case Temperature ( C) 0 Fig 9 Maximum Drain Current Vs Case Temperature Fig 0a Switching Time Test Circuit V DS 90% R G V GS 5 0V Puse Width µs Duty Factor 0. % D U T 0% V GS t d(on) t r t d(off) t f Fig 0b Switching Time Waveforms - V DD Therma Response (Z thjc ) 0. D = 0.50 0.20 0.0 0.05 0.02 0.0 SINGLE PULSE (THERML RESPONSE) 2. Peak T J = P DMx Z thjc T C 0.0 0.0000 0.000 0.00 0.0 0. t, Rectanguar Puse Duration (sec) Notes:. Duty factor D = t / t 2 P DM t t 2 Fig Maximum Effective Transient Therma Impedance, Junction-to-Case
L V DS D.U.T. R G V - DD 5 0 V I S t p 0.0Ω Fig 2a Uncamped Inductive Test Circuit V (BR)DSS t p E S, Singe Puse vaanche Energy (mj) 40 20 00 80 60 40 20 I D TOP 4.5 7.8 BOTTOM V DD = 25V 0 25 50 75 00 25 50 75 Starting T J, Junction Temperature ( C) V DS V DD Fig 2c Maximum vaanche Energy Vs Drain Current I S Fig 2b Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF 5 0 V Q GS Q GD D.U.T. V - DS V GS V G 3m Charge I G I D Current Samping Resistors Fig 3a Basic Gate Charge Waveform Fig 3b Gate Charge Test Circuit
Peak Diode Recovery dv/dt Test Circuit D U T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D U T I SD controed by Duty Factor "D" D U T - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-ppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4 For N-Channe HEXFETS
Package Outine TO-220B Outine Dimensions are shown in miimeters (inches) 2.87 (.3) 2.62 (.03) 0.54 (.45) 0.29 (.405) 3.78 (.49) 3.54 (.39) - - 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4 6.47 (.255) 6.0 (.240) 2 3.5 (.045) MIN LED SSIGNMENTS - GTE 2 - DRIN 3 - SOURCE 4 - DRIN 4.09 (.555) 3.47 (.530) 4.06 (.60) 3.55 (.40) 3X.40 (.055).5 (.045) 2.54 (.00) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.04) DIMENSIONING & TOLERNCING PER NSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220-B. 2 CONTROLLING DIMENSION : INCH 4 HETSINK & LED MESUREMENTS DO NOT INCLUDE BURRS. Part Marking Information TO-220B EXMPLE : THIS IS N IRF00 WITH SSEMBLY LOT CODE 9BM INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRF00 9246 9B M PRT NUMBER DTE CODE (YYWW) YY = YER WW = WEEK Data and specifications subject to change without notice. IR WORLD HEDQURTERS: 233 Kansas St., E Segundo, Caifornia 90245, US Te: (30) 252-705 TC Fax: (30) 252-7903 Visit us at www.irf.com for saes contact information. 07/02
Note: For the most current drawings pease refer to the IR website at: http://www.irf.com/package/