DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 1/22 Modeling All-MOS Log-Domain Σ A/D Converters X.Redondo 1, J.Pallarès 2 and F.Serra-Graells 1 1 Institut de Microelectrònica de Barcelona (CNM - CSIC) 2 Barcelona International R&D Core (Epson Europe Electronics GmbH - CNM) 25th November 2004
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 2/22 1 Introduction 2 Low-Voltage All-MOS Circuits 3 Modeling Circuit Non-Idealities 4 Design Example 5 Conclusions
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 3/22 1 Introduction 2 Low-Voltage All-MOS Circuits 3 Modeling Circuit Non-Idealities 4 Design Example 5 Conclusions
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 4/22 Σ Modulator Architecture CMOS Log Domain y source Limiter Antialiasing Filter y lim y in Analog Modulator Quantizer H DAC b out Digital Decimator Very low-voltage Low-power MOS-only I in + 1 1 1 s I 1 + 1 1 + 1 1 s s k I k L I dac di k dt = 1 τ k (I k 1 I dac ) I L M DAC Quantizer N=1 I high I low b out Simulation Issues High-accuracy Continuous-time Oversampling Pseudo-periodic... need for high-level (but device-based) analytical modeling!
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 5/22 1 Introduction 2 Low-Voltage All-MOS Circuits 3 Modeling Circuit Non-Idealities 4 Design Example 5 Conclusions
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 6/22 CMOS Log-Domain Processing Input Compressor I in + 1 1 1 s I 1 I k + 1 1 + 1 1 k s L s Quantizer I L b out M DAC I dac N=1 I high I in K 1 I ref I ref K I low V ref V in I in F V in + 1 G 1 s V 1 1 + 1 G C k 1 s V k 1 + 1 G C L k s V L 1 C L b out V dac F I high F I low I = F (V ) = I ref e V V ref nu t I > 0 Weak inversion and forward saturation: I D = I S e V GB V T O nu t e V SB U t I S = 2nβ ( ) W L U 2 t IC = I D IS Class-A operation: I in < I ref ( ) Iin V in = V ref + nu t ln + 1 I ref
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 7/22 Differential Integrator Quantizer and Built-in DAC di k dt = 1 τ k (I k 1 I dac ) b clk b clk b clk D b Q out dv k dt dq k dt }{{} C k dv k dt = nu t e Vk 1 Vk nu t τ k nu t e Vdac Vk nu t τ k ( ) = I } tunk e V k nu t e V k 1 nu t e V dac nu t {{} nu t C k τ k V L V ref { 1 VL > V b out = ref 0 V L V ref b out 1 K high K low I tunk I tunk V k-1 V k I capk V k-1 V k V ref C k V dac I capk C k ( ) Ihigh b V dac = V ref + nu t ln out+i low b out I ref
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 8/22 1 Introduction 2 Low-Voltage All-MOS Circuits 3 Modeling Circuit Non-Idealities 4 Design Example 5 Conclusions
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 9/22 Thermal Noise Block contributions: PSD in Class-A: di 2 Dn df = 4KT g ms 2 2qI D Input compressor: dv 2 inn df 4q (nu t) 2 I ref Integrator+DAC: di 2 capkn df 2q(2+K low +b out K high )I tunk SNR +3dB/oct(I ref ) K low = I low I tunk K high = I high I low I tunk I full I tunk
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 10/22 Moderate Inversion Inversion coefficient dependence: Degradation of the e x : ( ) I D = I S ln 2 1 + e V GB V T O 2nU t e V SB 2U t Input compressor: r V in = V ref +nu t ln e e I in +I ref r I ref I S 1 I S 1 Integrator+DAC: I capk = I S ln 2 [ 1 + e V k 1 V k 2nU t (eq Itunk 2 )] I S 1 )] I S ln 2 [ 1 + e V dac V k 2nU t (eq Itunk I S 1 SDR IC = I D I S
C k / C oxk DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 11/22 MOS Capacitors Strong inversion asymptote: Non-linear capacitors: dq k dt = ( C k + dc ) k dvk V k dv k dt NMOS capacitance: ) U t C k C oxk (1 V k V T O Integrator ODE: dv k dt = I tunk C oxk V k e nu t 1 + V T OU t (V k V T O ) 2 1 0.8 0.6 0.4 0.2 weak inversion 0-20 -15-10 -5 0 5 10 15 20 ( ) e V k 1 nu t e V dac nu t EKV moderate inversion ( Vk - VTO)/ Ut strong inversion C k V k SDR V ref V T O
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 12/22 MOS Capacitors OP dependence (V T ON 0.5V): Non-linear capacitors: dq k dt = ( C k + dc ) k dvk V k dv k dt NMOS capacitance: ) U t C k C oxk (1 V k V T O Integrator ODE: dv k dt = I tunk C oxk V k e nu t 1 + V T OU t (V k V T O ) 2 ( ) e V k 1 nu t e V dac nu t SDR V ref V T O
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 13/22 DAC Waveform Asymmetry I high I low I high I rtz I low I off +I amp I off I off -I amp 1 0 1 0 1 1 0 0 WA signal dependencies In-band noise injection! Return-tozero (I rtz ) techniques Equivalent model: input offset (I off ) + full-scale reduction (I amp )
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 14/22 Block Models (e.g. Simulink) Vnoise Iref Class-A Iin 1/Is -1 F (u) n*ut Vin Input compressor Voffset Technology mismatching Vcap S/H Quantizer (sgn(u-vref)+1)/2 Quantizer bout bout Vinp Vinn Inoise for bout=1 transconductance Vinp Vinn Icap Vcap bout=0 integration 1 s MOS cap Qcap Vcap Vdac Switch1 n*ut bout -1 F (u) 1/Is Iamp Ioff Cmos(Vcap) n*ut -1 F (u) 1/Is Integrator DAC (common to optimize simulation speed)
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 15/22 1 Introduction 2 Low-Voltage All-MOS Circuits 3 Modeling Circuit Non-Idealities 4 Design Example 5 Conclusions
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 16/22 Architecture A 4th-order 64 1bit single-loop Σ modulator: compressor integrator1 Iin Vin Vinp integrator2 Ain, fin Vin Vcap Vinp integrator3 bout Vinn Vcap bout Vinp Vinn Vcap integrator4 Vinp quantizer bout Vinn Vcap Vcap bout bout bout DAC RTZ Specifications Input full-scale Bandwidth Sampling frequency RTZ period Biasing Tuning Supply Technology Vdac bout 6µA pp 100Hz-8KHz 1.024MHz 10%-50% programmable I ref =7µA and V ref =0.7V I tunk ={7,1,1,1}µA and C oxk ={210,30,12,12} 5pF V DD =1.2V and P D 160µW 0.35µm CMOS digital V T ON + V T OP 1.2V
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 17/22 Design Process Functional vs Electrical fast high-level model optimal circuit parameters SPICE validation
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 18/22 Performance Estimations Simulation: electrical 18 weeks functional 1 hour DR=74dB(12b) and SNDR max =62dB at -4dBµA rms 3000!
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 19/22 Final Design 100¹ m Total area: 650µm 1130µm=0.73mm 2... to be integrated soon!
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 20/22 Final Design Reference Quantizer+S/H Switching NMOS capacitor array 100¹ m Dummies Biasing Translinear loops DACs Total area: 650µm 1130µm=0.73mm 2... to be integrated soon!
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 21/22 1 Introduction 2 Low-Voltage All-MOS Circuits 3 Modeling Circuit Non-Idealities 4 Design Example 5 Conclusions
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 22/22 Main Results Accurate high-level modeling of log-domain CMOS Σ ADCs. Analytical circuit study + advanced MOSFET models. Simulation speed improved by more than 1000 times. Independent evaluation of each non-ideality or block effect. ADC complete performance estimations can be iterated. Example for a 4th-order 64 1bit single-loop Σ modulator.