Lecture 17: Designing Sequential Systems Using Flip Flops

Similar documents
Lecture 14: State Tables, Diagrams, Latches, and Flip Flop

Digital Circuits and Systems

Sequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science

Chapter 5 Synchronous Sequential Logic

Sequential Circuit Analysis

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Sequential Logic Circuits

Synchronous Sequential Logic

Chapter 4. Sequential Logic Circuits

The Design Procedure. Output Equation Determination - Derive output equations from the state table

Lecture (08) Synchronous Sequential Logic

ELCT201: DIGITAL LOGIC DESIGN

Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Different encodings generate different circuits

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

ELCT201: DIGITAL LOGIC DESIGN

Week-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

Finite State Machine. By : Ali Mustafa

Philadelphia University Student Name: Student Number:

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

10/12/2016. An FSM with No Inputs Moves from State to State. ECE 120: Introduction to Computing. Eventually, the States Form a Loop

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

COE 202: Digital Logic Design Sequential Circuits Part 3. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

ELE2120 Digital Circuits and Systems. Tutorial Note 9

CprE 281: Digital Logic

Latches. October 13, 2003 Latches 1

Analysis and Design of Sequential Circuits: Examples

Lecture 10: Synchronous Sequential Circuits Design

Unit 7 Sequential Circuits (Flip Flop, Registers)

PAST EXAM PAPER & MEMO N3 ABOUT THE QUESTION PAPERS:

15.1 Elimination of Redundant States

Lecture 8: Sequential Networks and Finite State Machines

Shift Register Counters

Sample Test Paper - I

Sequential Circuits Sequential circuits combinational circuits state gate delay

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

COE 202: Digital Logic Design Sequential Circuits Part 3. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

Lecture 13: Sequential Circuits, FSM

Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

6 Synchronous State Machine Design

Digital Circuits ECS 371

Gates and Flip-Flops

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

Problem Set 9 Solutions

Chapter 7 Sequential Logic

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Lecture 7: Karnaugh Map, Don t Cares

Chapter 14 Sequential logic, Latches and Flip-Flops

Sequential Synchronous Circuit Analysis

CPE100: Digital Logic Design I

Sequential vs. Combinational

ELE2120 Digital Circuits and Systems. Tutorial Note 10

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs

CSCI 2150 Intro to State Machines

Roger L. Tokheim. Chapter 8 Counters Glencoe/McGraw-Hill

Computers also need devices capable of Storing data and information Performing mathematical operations on such data

Philadelphia University Student Name: Student Number:

Synchronous Sequential Logic. Chapter 5

Time Allowed 3:00 hrs. April, pages

CHW 261: Logic Design

Clocked Sequential Circuits UNIT 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS. Analysis of Clocked Sequential Circuits. Signal Tracing and Timing Charts

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Simplify the following Boolean expressions and minimize the number of literals:

Written reexam with solutions for IE1204/5 Digital Design Monday 14/

Counters. We ll look at different kinds of counters and discuss how to build them

11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output of

I. Motivation & Examples

EGR224 F 18 Assignment #4

Fundamentals of Digital Design

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.

Lecture 13: Sequential Circuits

14.1. Unit 14. State Machine Design

COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

Clocked Synchronous State-machine Analysis

Logic Design II (17.342) Spring Lecture Outline

Synchronous Sequential Logic Part I. BME208 Logic Circuits Yalçın İŞLER

Synchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1

Lecture 13: Sequential Circuits, FSM

Chapter 3 Digital Logic Structures

Digital Circuits. 1. Inputs & Outputs are quantized at two levels. 2. Binary arithmetic, only digits are 0 & 1. Position indicates power of 2.

Computer Science Final Examination Friday December 14 th 2001

Digital Logic Design - Chapter 4

or 0101 Machine

Lecture 9: Digital Electronics

LOGIC CIRCUITS. Basic Experiment and Design of Electronics

Combinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #13

Synchronous Sequential Circuit Design. Digital Computer Design

COMBINATIONAL LOGIC FUNCTIONS

ECE 341. Lecture # 3

Decoding A Counter. svbitec.wordpress.com 1

Exam for Physics 4051, October 31, 2008

Transcription:

EE210: Switching Systems Lecture 17: Designing Sequential Systems Using Flip Flops Prof. YingLi Tian April 11, 2019 Department of Electrical Engineering The City College of New York The City University of New York (CUNY) 1

Designing Sequential Systems Goal: Given a problem statement a verbal description of the intended behavior of the system, design a block diagram of the system using the available components and meeting the design objectives and constraints. 2

Steps of Designing Sequential Systems -- 1 Step 1: From a word description, determine what needs to be stored in memory, that is, what are the possible states. Step 2: If necessary, code the inputs and outputs in binary. Step 3: Derive a state table to describe the behavior of the system. Step 4: Use state reduction techniques to find a state table that produces the same input/output behavior, but has fewer states. 3

Steps of Designing Sequential Systems -- 2 Step 5: Choose a state assignment, that is, code the states in binary. Step 6: Choose a flip flop type and derive the flip flop input maps or tables. Step 7: Produce the logic equation and draw a block diagram (as in the case of combinational systems). 4

Design Example 1 A system with one input x and one output z such that z=1 if and only if x has been 1 for at least three consecutive clock time. Step 1 3: create state table 5

Design Example 1: state assignments q has 4 states: A, B, C, D. Need two 1-bit memories q 1 and q 2 to represent all the states. 6

Design Example 1: Truth table 7

Design Example 1: output map and equations q 1 * = xq 2 + xq 1 q 2 * = xq 2 + xq 1 q 1 * q 2 * z = q 1 q 2 Conclusion: need 4 two-input AND gates, 2 two-input OR gates. q 1 * and q 2 * share one gate: xq 1 8

Designing Systems Using Flip Flops Method 1: truth table-based method Method 2: map-based method Method 3: quick method (only works for JK flip flops). We use previous example: A system with one input x and one output z such that z=1 if and only if x has been 1 for at least three consecutive clock time. 9

Designing based on Truth Table D Flip Flops D Flip Flop: q* = D From Slide 8: D 1 = x q 2 + x q 1 D 2 = x q 2 + x q 1 q 1 * = xq 2 + xq 1 q 2 * = xq 2 + xq 1 z = q 1 q 2 10

D Flip Flops The output depends only on the input. The D flip flop behavior table: 11

Designing based on Truth Table D Flip Flops D 1 = q 1 * = xq 2 + xq 1 D 2 = q 2 * = xq 2 + xq 1 z = q 1 q 2 12

JK Flip Flop JK flip flop is a combination of the SR and T flip flops. It behaves like a SR flip flop (J as S, K as R). However, if J=K=1, it behaves like a T flip flop. q* = Jq + K q 13

Designing by JK Flip Flops q* = Jq + K q From Slide 8: q 1 * = xq 2 + xq 1 q 2 * = xq 2 + xq 1 z = q 1 q 2 14

Designing by JK Flip Flops J 1 = xq 2 K 1 = x z = q 1 q 2 J 2 = x K 2 = x + q 1 Conclusion: need 2 two-input AND gates, 1 two-input OR gate, and a NOT gate for x. A volunteer to draw the circuit diagram!! 15

SR Flip Flop hold reset set q* = S + R q S and R cannot be 1 at the same time. 16

Designing by SR Flip Flops q* = S + R q 17

Designing by SR Flip Flops S 1 = xq 2 R 1 = x z = q 1 q 2 S 2 = xq 2 R 2 = x + q 1q 2 Conclusion: need 4 two-input AND gates, 1 two-input OR gate, and a NOT gate for x. 18

Designing by T Flip Flops 19

Designing by T Flip Flops T 1 = x q 1 + xq 1q 2 T 2 = x q 2 + xq 2 + xq 1q 2 z = q 1 q 2 Conclusion: need 4 two-input AND gates, 1 three-input AND gate, 1 two-input and 1 three-input OR gate, and a NOT gate for x. 20

Quick method of implementation by using JK Flip Flops Using SR flip flop q* = S + R q Using JK flip flop with more Xs than SR. q* = Jq + K q 21

Quick method of implementation by using JK Flip Flops q* = Jq + K q If q = 0, we have q* =J If q = 1, we have q* =K 22

Quick method of implementation by using JK Flip Flops Computation of J1 and K1 J 1 = xq 2 K 1 = x both J 1 and K 1 do not depend on q 1. 23

Quick method of implementation by using JK Flip Flops 11 J 2 = x, K 2 = x + q 1, both J 2 and K 2 do not depend on q 2. 24

Quick method of implementation by using JK Flip Flops J 1 = xq 2, K 1 = x or K 1 = x J 1 = xq 2 K 1 = x J 2 = x K 2 = x + q 1 z = q 1 q 2 25

Quick method of implementation by using JK Flip Flops J 2 = x, K 2 = x + q 1 q* = Jq + K q J 1 = xq 2 K 1 = x J 2 = x K 2 = x + q 1 z = q 1 q 2 If q = 0, we have q* =J; If q = 1, we have q* =K 26

Practice 1: A system with one input x and one output z such that z=1 if and only if x has been 1 for at least three consecutive clock time. Step 1 3: create state table 27

Use a different state assignment q has 4 states: A, B, C, D. Need two memories q 1 and q 2 to represent all the states. 28

Designing by Using JK Flip Flops q* = Jq + K q Using quick method 29

Practice 2: A system with one input x and one output z such that z=1 if and only if x = 1 and has been 1 for at least two consecutive clock time. Step 1 3: create state table 30

Announcement HW7 is due on 4/18/2019 Practice: P430 Example 7.4 Read Chapter 7.1 Designing Sequential Systems using Flip Flops Next Class (Chapter 7.2 and 7.3) Design of Counters 31