CMSC 33 Lecture 8 Midterm Exam returned ssign Homework 3 Circuits for ddition Digital Logic Components Programmable Logic rrays UMC, CMSC33, Richard Chang <chang@umbc.edu>
Half dder Inputs: and Outputs: S = lower bit of +, c out = carry bit S c out Using Sum-of-Products: S = +, c out =. lternatively, we could use XOR: S =.
dder Inputs:, and c in Outputs: S = lower bit of +, c out = carry bit c in S c out S = C + C + C + C = C. c out =MJ3= + C + C. 2
3-6 Ripple Carry dder Chapter 3: rithmetic Two binary numbers and are added from right to left, creating a sum and a carry at the outputs of each full for each bit position. b 3 a 3 c 3 b 2 a 2 c 2 b a c b a c c 4 s 3 s 2 s s
3-7 Constructing Larger dders Chapter 3: rithmetic 6-bit can be made up of a cascade of four 4-bit ripplecarry s. a 5 a 4 a 3 a 2 b 5 b 4 b 3 b 2 b 3 a 3 b 2 a 2 b a b a c 6 4-it dder #3 c 2 c 4 c... 4-it dder # s 5 s 4 s 3 s 2 s 3 s 2 s s
3-8 Subtractor Chapter 3: rithmetic Truth table and schematic symbol for a ripple-borrow subtractor: a i b i bor i diff i bor i+ b i a i bor i+ subtractor diff i (a i b i ) bori
3-9 Ripple-orrow Subtractor Chapter 3: rithmetic ripple-borrow subtractor can be composed of a cascade of full subtractors. Two binary numbers and are subtracted from right to left, creating a difference and a borrow at the outputs of each full subtractor for each bit position. b 3 a 3 b 2 a 2 b a b a bor subtractor subtractor subtractor subtractor bor 4 diff 3 diff 2 diff diff
3- Combined dder/subtractor Chapter 3: rithmetic single ripple-carry can perform both addition and subtraction, by forming the two s complement negative for when subtracting. (Note that + is added at c for two s complement.) b 3 b 2 b b DD / SUTRCT a 3 a 2 a a c c 4 s 3 s 2 s s
3-2 Carry-Lookahead ddition Chapter 3: rithmetic Carries are represented in terms of G i (generate) and P i (propagate) expressions. G i = a i b i and P i = a i + b i c = c = G c 2 = G + P G c 3 = G 2 + P 2 G + P 2 P G c 4 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G
3-22 Carry Lookahead dder Chapter 3: rithmetic b 3 a 3 b 2 a 2 b a b a G 3 P 3 G 2 P 2 G P G Maximum gate delay for the carry generation is only 3. The full s introduce two more gate delays. Worst case path is 5 gate delays. c 4 c 3 c 2 c c s 3 s 2 s s
-26 ppendix : Digital Logic Digital Components High level digital circuit designs are normally created using collections of logic gates referred to as components, rather than using individual logic gates. Levels of integration (numbers of gates) in an integrated circuit (IC) can roughly be considered as: Small scale integration (SSI): - gates. Medium scale integration (MSI): to gates. Large scale integration (LSI): -, logic gates. Very large scale integration (VLSI):,-upward logic gates. These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits.
Data Inputs -27 ppendix : Digital Logic Multiplexer D D D 2 D 3 F F D D D 2 D 3 Control Inputs F = D + D + D 2 + D 3
-28 ppendix : Digital Logic ND-OR Implementation of MUX D D D 2 F D 3
-29 ppendix : Digital Logic MUX Implementation of Majority Principle: Use the 3 MUX control inputs to select (one at a time) the 8 data inputs. C M F C
-3 ppendix : Digital Logic 4-to- MUX Implements 3-Var Function Principle: Use the and inputs to select a pair of minterms. The value applied to the MUX data input is selected from {,, C, C} to achieve the desired behavior of the minterm pair. C F C C C C F
-3 ppendix : Digital Logic Demultiplexer D F = D F = D F F F 2 F 3 F 2 = D F 3 = D D F F F 2 F 3
-32 ppendix : Digital Logic Gate-Level Implementation of DEMUX F D F F 2 F 3
-33 ppendix : Digital Logic Decoder Enable = Enable = D D Enable D 2 D 3 D D D 2 D 3 D D D 2 D 3 D = D = D 2 = D 3 =
-34 ppendix : Digital Logic Gate-Level Implementation of Decoder D D D 2 D 3 Enable
-35 ppendix : Digital Logic Decoder Implementation of Majority Function Note that the enable input is not always present. We use it when discussing decoders for memory. C M