ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Following the slides of Dr. Ahmed H. Madian Lecture 10 محرم 1439 ه Winter 2018
COURSE OUTLINE 1. Introduction 2. Gate-Level Minimization 3. Combinational Logic 4. Synchronous Sequential Logic 5. Registers and Counters 6. Memories and Programmable Logic 2
LECTURE OUTLINE Counters Definition and Introduction Binary Ripple Counters T FF-based D FF-based Synchronous Counters Up Counters Down Counters Unused States Design Problems 3
COUNTERS: A DEFINITION A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter The input pulses may be clock pulses, or they may originate from some external source and occur at a fixed interval of time or at random The sequence of states may follow the binary number sequence or any other sequence of states 000 001 010 011 100 101 000 010 100 000 010 100 4
COUNTERS: INTRODUCTION A counter that follows the binary number sequence is called a binary counter An n bit binary counter consists of n FFs and can count from 0 through 2 n 1 Counters are available in 2 categories: Ripple counters Synchronous counters 5
COUNTERS: INTRODUCTION In a ripple counter, a FF output transition serves as a source for triggering other FFs This means that the C input of some or all FFs are triggered, not by the common clock pulses, but rather by the transition that occurs in other FF outputs In a synchronous counter, the C inputs of all FFs receive the common clock 6
BINARY RIPPLE COUNTERS A binary ripple counter consists of a series connection of complementing FFs, with the output of each FF connected to the C input of the next higher order FF (see next slide) The FF holding the least significant bit receives the incoming count pulses The output of the first FF is always the complement of its input The T inputs of all the FFs in the first counter are permanently connected to Logic 1, making each FF complement if the signal in its C input goes through a negative transition The negative transition occurs when the output of the previous FF to which C is connected goes from 1 to 0 7
A 0 A 0 Count Count A 1 A 1 A 2 A 2 But what if we are interested in building a counter that counts down? How can we modify the current logic diagrams to achieve this new target? Logic 1 A 3 A 3 Reset Reset 8
BINARY RIPPLE COUNTERS: BONUS QUESTION How many flip-flops will be complemented in a 10 bit binary ripple counter to reach the next count after the following counts? a. 1001100111 b. 0011111111 c. 1111111111 9
SYNCHRONOUS COUNTERS In a synchronous binary counter, the FF controlling the least significant bit is complemented with every clock cycle Any other FF will only complement its stored bit when all the bits in the lower significant positions are equal to 1 For example, if the present state of a 4 bit counter is A 3 A 2 A 1 A 0 = 0011, the next count is 0100 A 0 is always complemented. A 1 is complemented because the present state of A 0 = 1. A 2 is only complemented if the present state of A 1 A 0 =11. However A 3 is not complemented, because the present state of A 2 A 1 A 0 = 011, which does not give an all 1s condition 10
SYNCHRONOUS COUNTERS The first stage, A 0, has its J and K equal to 1 if the counter is enabled The other J and K inputs are equal to 1 if all previous least significant stages are equal to 1 and the count is enabled The chain of AND gates generates the required logic for the J and K inputs in each stage Such a counter can be extended to any number of stages, with each stage having an additional FF and an AND gate that gives an output of 1 if all previous FF outputs are 1 11
A 0 4 BIT SYNCHRONOUS BINARY COUNTER Count enable A 1 A 2 JK FF characteristic table Is the polarity of the clock essential in this design? What happens if we implement this counter with a negative edge-triggered clock? Clk 12 A 3 To next stage
4 BIT SYNCHRONOUS BINARY UP/DOWN COUNTER So how can we design an up/down synchronous binary counter? 13
Up Down A 0 Function table With a mode control of 10 and a current count of 0101, what is the next count? This is not a mistake! With a mode control of 01 and a current count of 0111, what is the next count? A 1 A 2 A 3 T FF characteristic table Clk 14
UNUSED STATES What happens if we are interested in a counter design that does not include all states (counts)? 101 000 001 For example, here is a state diagram and a state table (next slide) for a counter that repeatedly counts from 000 to 101 100 010 What should we write in the table for the couple of unused states? 011 15
UNUSED STATES Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0??? 1 1 1??? 101 100 000 011 001 010 16
UNUSED STATES CAN BE DON T CARES Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 X X X 1 1 1 X X X To reach the simplest possible circuit, we can fill in don t cares for the next states This will also result in don t cares for the FF inputs, which might simplify the hardware If the circuit somehow ends up in one of the unused states {110,111}, its behavior will depend on exactly what the don t cares were filled in with 17
110 111 OR MAYBE WE DO CARE! 000 Present State Next State 101 001 Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 100 011 010 To reach the safest possible circuit, we can explicitly fill in next states for the unused states {110,111} This guarantees that even if the circuit somehow enters an unused state, it will eventually end up into one of the valid states This is called a self-starting counter 18
DESIGN PROBLEM Design a sequential logic circuit that implements the following recurring sequence: 000 010 011 100 101 111 000 Assume that the circuit is a self-starting one. 19
DESIGN PROBLEM: SOLUTION 1. From the word description and 001 110 the required specifications, we sketch the state diagram. Since 000 each state consists of 3 bits, we need 3 flip-flops 010 Here, T FFs would be a good choice, since we are going to toggle some bits in every state transition 111 101 100 011 20
DESIGN PROBLEM: SOLUTION 2. Next, we derive the state table. The present and next states are known from the state diagram. While the FF inputs are obtained with the help of the T FF excitation table or characteristic equation 21
DESIGN PROBLEM: SOLUTION Present State Next State FF Inputs Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 T 2 T 1 T 0 001 110 000 111 010 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 101 100 22 011
DESIGN PROBLEM: SOLUTION 3. The FF input equations are then simplified (carried out on the board) 4. Finally, the logic circuit of the counter is sketched (carried out on the board) 23
ASSIGNMENT 3 REMINDER! Deadline of assignment 3 is Monday the 10 th of December, 2018 24