ADVANCED processing techniques that make use of

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 9, SEPTEMBER 1997 1393 Simulating Process-Induced Gate Oxide Damage in Circuits Robert Tu, Joseph C. King, Hyungcheol Shin, Member, IEEE, and Chenming Hu, Fellow, IEEE Abstract Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator. I. INTRODUCTION ADVANCED processing techniques that make use of plasma and ion implantation enable us to manufacture highly integrated semiconductor circuits; however, these very processes can damage the gate oxides of the MOS devices being fabricated, reducing oxide reliability and changing device performance [1] [22] (Fig. 1). During these processing steps, aluminum or polysilicon patterns in the layout act as antennas, collecting charges. As a result, a finite current can pass through each gate oxide during processing. The current stress will degrade gate oxides or even cause catastrophic breakdown of the oxide. Fig. 2, [1] is a plot of the distribution of ramp breakdown voltages for oxides that have endured plasma processing ( ) and for control samples that were wetprocessed ( ). The difference between the two curves can be attributed to damage from plasma etching. The plasma process has destroyed 8% of the capacitors even before stressing begins. For oxides that do not breakdown, the charging current creates new oxide trapped charges and interface states [1]. Subsequent annealing steps will mask the damage so that gate oxides appear to be undamaged. However, the latent damage will manifest itself later during circuit operation in the form of degraded hot-carrier performance. The oxide traps and interface states created during processing will be easily uncovered by hot-carrier stressing, causing the device performance to change sharply when first stressed. Fig. 1. The two ways that wafer charge-up can affect circuit reliability: reduced gate oxide reliability (i.e., increase the chances of catastrophic breakdown) and degraded hot-carrier reliability. Fig. 2. Cumulative failure versus oxide breakdown voltage after both a plasma etch and a wet etch. Manuscript received March 12, 1996; revised March 31, 1997. The review of this paper was arranged by Editor A. H. Marshak. This work was supported by the Semiconductor Research Corporation under Contract 93-MJ-148, ISDO/STIO administered through ONR under Contract N0019-85-K-0603 and AMD. R. Tu is with Advanced Micro Devices, Sunnyvale, CA 94086 USA. J. C. King is with Rockwell International, Redondo Beach, CA 92660 USA. H. Shin is with Korean Advanced Institute of Science and Technology, Taejon 305 701, Korea. C. Hu is with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. Publisher Item Identifier S 0018-9383(97)06123-6. We present a simulator, a new module in the Berkeley Reliability Tools framework (BERT) [23] which determines oxide failure rates during and after processing and identifies the locations of strong charging where changes can be made to improve hot-carrier reliability [22]. With the existing BERT framework, we can simulate gate oxide failures through processing, burn-in, and circuit operation (Fig. 3). Since our knowledge of in-process damage is maturing, the next logical step is a tool such as this for designing-in- 0018 9383/97$10.00 1997 IEEE

1394 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 9, SEPTEMBER 1997 Fig. 3. Using the new module and the existing oxide reliability framework in BERT, we can simulate gate oxide failure rates through processing, burn-in, and circuit operation. The circuit oxide reliability simulator (used to determine oxide reliability during circuit operation) is composed of a pre/post processor to a circuit or timing simulator such as SPICE. reliability, exploring in-process screening, and improving process yield. II. ORGANIZATION AND OPERATION OF THE SIMULATOR From this point forward, we will focus on damage due to plasma processing. Extensive research has been done in this area. Similar oxide charge-up phenomenon (such as ion implantation) can be simulated using the same methodology. A top-level diagram of the simulator including the data needed to predict in-process damage is shown in Fig. 4. Using layout information (antenna geometries, oxide areas, protection diode locations, and the location on the wafer), the simulator determines the charging current going through each gate oxide during each step. With this information, the simulator uses standard oxide breakdown models to determine gate oxide failure rates and then circuit failure rates. A. Determining Charging Currents In order to predict oxide failure, we must first determine the amount of charging current passing through each gate oxide. Fig. 5 shows the step-by-step process of determining these charging currents for a single process step. The user experimentally determines the current density per antenna area/length for the specific process step. This result will be an input to the simulator. This current density per electrode area or peripheral length can be determined by using the following procedure [10], [12]. We begin by fabricating test capacitors using both plasma processing and wet processing. By stressing the wet-processed capacitors with different stress currents, we can generate a set of control capacitors with different degrees of damage. By comparing the plasma-processed capacitor with the set of wet-processed capacitors using criteria such as or CV curves, we can determine which wet-etched capacitor is most like the plasma damaged capacitor. Since we know the amount of stress current placed on the wet-etched capacitors, we can determine the stressing current for the plasma etched capacitor. Fig. 4. A top-level flowchart for the wafer charge-up simulator. For example, several CV curves are shown in Fig. 6, corresponding to wet-processed capacitors with different degrees of damage. As we can see, the CV curve of the capacitor fabricated using plasma ( symbols) corresponds to one of these CV curves. In this case, we find that the plasma-induced current is 10 na. The current density is calculated simply by dividing this current by the antenna area for a photoresist stripping step or by the peripheral length for an ashing or etching step. This dependence on antenna geometry will be explained later. Even though most of the oxide stressing occurs in the later stages of etching when the antenna is exposed, we will define the current stress time as the total etching time for simplicity and because overetching time is not a constant over the wafer. Fig. 7 shows the oxide charging current as a function of the location on the wafer [12]. There is clearly a radial dependence for the charging current. Normally, the magnetic field in an etcher is rotated in order to obtain better etch rate uniformity across the wafer [12] [18]. The results in Fig. 7 were obtained using an RIE etcher; however, similar results are also true of a MERIE etcher [17]. Thus, a simple radial function can model the spatial dependence of the charging current density. We can now predict the current density induced by the plasma at each location on the wafer. The charging current collected by an antenna equals the current density at that location multiplied by either the area or peripheral length of the antenna. This dependence of the charging current on antenna geometry can be understood as follows. The aluminum or polysilicon patterns in the layout act as antennas; thus, only the portion of each antenna that is exposed to the plasma ambient can collect charge. For steps such as photoresist stripping where the whole surface of the antenna is exposed, the stress current is proportional to the ratio of the area; whereas, in steps such as Al etching, where only the edge is exposed, the current is proportional to the peripheral length [20]. Fig. 8 is a plot of the plasma stressing current during Al etching versus Al pad peripheral lengths. Clearly, the stressing current is proportional to the peripheral length of the Al pads. The stressing current is negligible when photoresist covers the entire surface of the wafer, confirming that only the exposed portion of each antenna collects charge.

TU et al.: SIMULATING PROCESS-INDUCED GATE OXIDE DAMAGE 1395 Fig. 5. A flow chart for determining the amount of charging current flowing through each oxide. Fig. 7. The spatial dependence of oxide charging current in a plasma etcher at different power levels. The spatial variation has a radial dependence. Fig. 6. The CV s of wet-etched capacitors after 60 s of constant current stress at varying current levels. By matching the plasma etched curve with the corresponding current stressed curve, we can quantify the oxide charging current. A similar plot in Fig. 9 confirms that during photoresist stripping, charging current is proportional to A1 pad area. Thus for a single process step, the simulator can examine the layout and determine the areas and peripheral lengths of all the exposed antennas. Given the charging density per electrode area or peripheral length during processing, we can then directly determine the total current collected by each antenna. Shunting diodes provide an alternative leakage path for current that might otherwise damage gate oxides [21]. Often these diodes are placed purposely by the designer in order to alleviate the problems caused by plasma damage. In other cases, they are formed naturally in the design at the PN junctions of regular MOSFET source and drains. In either case, the simulator searches through the layout and identifies shunting diodes. If the current from the antenna is not diverted away by a protection diode, then the current will be distributed among the gate oxides attached to the antenna. The amount of current an oxide receives will be in direct proportion to, where is the area of the oxide and is the sum of the areas of all the oxides connected to the antenna. B. Oxide Breakdown Model Using the procedure outlined above, we can determine the charging current for each gate oxide. To determine the probability of failure for the oxide, the simulator uses a standard oxide breakdown model. Using existing oxide tests

1396 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 9, SEPTEMBER 1997 Fig. 8. Oxide charging current as a function of Al edge length. The oxide charging current during etching is proportional to Al edge length. Fig. 10. oxide. The procedure for calculating the failure probabilities for each gate Fig. 9. Oxide charging current as a function of electrode area. The oxide charging current during plasma photoresist stripping is proportional to electrode area. The process time is 60 min. (e.g., voltage ramp test), the user can characterize the oxide. Depending on the needs of the user, the oxide can be characterized for each process step or just once. The intrinsic defect distribution and properties of the oxide do not change greatly after it is formed. Since oxide damage and healing is modeled outside the basic oxide model, it is sufficient to characterize the gate oxide once, immediately after it has been formed, and we recommend doing this to save unnecessary characterization. The model for oxide breakdown is based on [24] and is referred to as the 1/E Model. According to this model, the oxide intrinsic lifetime ( )is where is oxide thickness, is oxide voltage, and are proportionality constants. Capacitors of practical size experience defect-related breakdown which causes them to have a nondeterministic lifetime. Thus, becomes a probabilistic variable. Every weak spot, i.e., defect point, behaves like an oxide with an effective thickness. The smaller the, the more severe the defect. Defect-related breakdown is modeled as [25] (1) (2) Note that the random variable has been substituted for in the above expression. The probability that a device undergoes oxide breakdown before a given is related to the probability that the oxide contains a specific value of. Equation (2) can be extended for use with time varying voltages using a quasi-static approach. Thus, time dependent dielectric breakdown (TDDB) may be modeled with [26] where is the time to breakdown. is the voltage which appears across the oxide. is the oxide thickness; and are experimentally determined parameters for a given technology. Each plasma and ion implantation step damages the gate oxide and experimental results suggest that these damages are additive. To calculate total damage, we characterize each process step separately (assigning a stress charge density due to plasma charging) and sum up the damages incurred at each step. The equivalent equation for (3) is where, and to the number of process steps in the process flow. For the case of oxide charging, is a constant for each step and is determined using the Fowler Nordheim tunneling equation [1] and are known constants. is the oxide area, and is the current going through the oxide. can be (3) (4) (5)

TU et al.: SIMULATING PROCESS-INDUCED GATE OXIDE DAMAGE 1397 Fig. 11. The effect of a 20 min anneal on charge to breakdown. Q bd is plotted versus injected charge after different anneal temperatures. Low-temperature anneals do not heal the charge-up damage. However, high-temperature anneals heal about one-third of the oxide damage. The 400 C anneal was done in forming gas (N 2 /H 2 ), and the 800 C and 900 C anneals were done in nitrogen. Fig. 12. Circuit schematic for the simulated differential pair with top three most damaged transistors including failure probability and maximum effective stressing voltage. T ox =12:5nm. determined by solving (5) iteratively using Newton Raphson iteration. Since is a constant The that will cause breakdown within the time period can be determined by solving for (4). Assuming that defects are distributed uniformly and independently across the test wafers and actual circuits, we can use a Poisson distribution to describe the defect density. The probability that a device fails at or before a specified is equal to the probability that the device contains one or more defects of size or smaller. Using the Poisson distribution, this probability may be expressed as (7) where is the area density of defects size or smaller (recall smaller s are more severe defects). (6) Fig. 13. Layout of the differential amplifier circuit shown in Fig. 11. Notice the large antenna mismatch for the differential pair M 1 and M 2. as a function of is determined from test capacitor breakdown statistics. The probability that the circuit fails at some user specified time is equal to the probability that at least one device in the circuit fails. This may be expressed as where is the number of MOS devices in the circuit, is the defect density for the th device. The complete procedure for determining failure probabilities is shown in Fig. 10. To determine failure probabilities throughout a gate oxide s whole lifetime including burn-in [27] and circuit operation [23], we extend (4) to (8) (9)

1398 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 9, SEPTEMBER 1997 Fig. 14. Simplified set of damaging process steps and anneals for an analog process used to simulate circuit in Fig. 11. Typical values for the stressing current were taken from literature. Fig. 15. Cumulative failure throughout circuit lifetime including processing and circuit operation. The failure rate without in-process burn-in is much higher than the one with in-process burn-in. The inset shows cumulative failure during processing after each step. C. Simulating a Complete Process To calculate total damage, we characterize each process step separately (assigning a stress current density due to plasma charging) and sum up the damages incurred at each step. However, annealing at all subsequent temperature steps can partially repair the gate oxide unless breakdown has occurred. Fig. 11 shows the charge to breakdown of capacitors which have been stressed by a constant current source (to simulate plasma damage) and subsequently annealed at different temperatures [28]. The solid line in the figure has a slope of 1 implying that a total injected charge of 30 C/cm (including pre/post anneal stressing) is needed to breakdown the oxide. The curves representing no anneal ( ) and a 400 C anneal ( ) follow approximately the same slope of 1, indicating that there has been no healing. An anneal that completely heals the oxide would give us a horizontal line at 30 C/cm. Both the 800 C and 900 C anneals (squares) show a change in slope between these two extremes. The change shows that the anneal has reduced the effect of pre-anneal stress on charge to breakdown ( ) by about one-third. A single parameter is sufficient to quantify the oxide recovery after annealing and is one-third for a typical case. The effect of annealing can now be easily incorporated into the existing framework. For example, for a process with two damaging plasma steps followed by an annealing step and another plasma step, the damage would be determined by solving for the equation (10) III. SIMULATION AND DISCUSSION In order to demonstrate the capabilities of the simulator, we will study the oxide reliability of a differential amplifier (Figs. 12 and 13) through processing and circuit operation. The circuit and layout are typical of a differential amplifier and use a typical CMOS fabrication process. Fig. 14 shows the steps in the CMOS process flow that will affect gate oxide reliability. Typical values for the stressing current for both etching and stripping were taken from [1], [22]. The charging current for our process is unidirectional although it is possible to have bidirectional charging currents. The second step in the process is an annealing step which will partially heal the damage caused during the poly etching step. We assume that

TU et al.: SIMULATING PROCESS-INDUCED GATE OXIDE DAMAGE 1399 annealing heals one-third of the oxide damage. Fig. 12 is the circuit schematic. Fig. 13 shows a schematic of the layout including the prominent antennas made of metal and poly. Diffusion areas are also shown. Since the stressing current for our process is positive (i.e., going from the poly gate through the oxide to the body), protection diodes can be made by attaching each gate to the p-substrate of a PN junction. Although we did not intentionally form any protection diodes, there are unintentional protection diodes protecting each gate which is attached to a PMOS source or drain diffusion. These locations are indicated on Fig. 12. The top three most damaged transistors are marked on the schematic in Fig. 12. In the figure, we have indicated the failure probabilities of the transistor after processing and the maximum effective stressing voltage encountered across the gate oxide during the whole process. Note that the damage on each of the MOSFET s in the differential pair ( )is different since a much larger antenna is connected to.a feedback path connects to the output. This feedback path is a metal line that must stretch across the whole length of the circuit in order to reach the output as seen in Fig. 13. Although the damage to each MOSFET can be passivated by annealing, the latent damage will reappear after hot-carrier stressing [22]. The result is is not matched with (device mismatch). This is a very serious problem for the differential amp pair. This mismatch is also time dependent, becoming worse with time. The inset to Fig. 15 is a bar graph of the failure rate during each of the processing steps. This is the failure rate due to gate oxide breakdown for the whole circuit. The figure also shows the total failure rate for the whole process. Fig. 15 itself shows the failure rate of the circuit while it is actually operating. 20 years of operation are shown. In this case, the in-process damage acts much like a burn-in, screening out circuits that would ordinarily breakdown early due to infant mortality; thus, the failures during circuit operation are greatly reduced. A second curve shows that without the burn-in screening, the failure rate during operation would be six orders larger. If we neglect the stressing due to plasma processing and include an extra burn-in screening, we could unnecessarily injure the circuits that survive the screening by using too vigorous a set of burn-in conditions. This is a good example of where the simulator can be useful for designing a set of burn-in conditions. In-process screening is a name given to burn-in done during processing instead of after processing. Burn-in is often time consuming and thus cuts into the profitability of the chips being fabricated. In-process screening could make burn-in easier and less time consuming because devices are much more accessible during processing. This simulator can easily handle the job of studying the benefits of in-process screening. IV. SUMMARY As VLSI circuits shrink in size, we will have to solve an increasing number of reliability problems. We have discussed the possibility of oxide damage during processing due to advanced techniques that make use of plasma or ion implantation. Since our research in this area is maturing, the time is right for a simulator that can help designers confront this problem. In this paper, we have discussed one such simulator with the ability to simulate the oxide reliability of VLSI circuits during and after processing. We have also simulated the oxide reliability of a differential pair through processing and operation. ACKNOWLEDGMENT R. Tu would like to thank C. Nguyen for generously providing the design and layout for the differential amplifier circuit. REFERENCES [1] H. Shin and C. Hu, Monitoring plasma-process-induced damage in thin oxide, IEEE Trans. Semiconduct. Manufact., vol. 6, p. 96, May 1993. [2] R. Rakkhit, F. Heiler, P. Fang, and C. Sander, Process-induced oxide damage and its implications to device reliability of submicron transistors, in Proc. 1993 Int. Rel. Phys. Symp., 1993, p. 293. [3] Y.-H. Lee et al., Correlation of plasma process-induced charging with Folwer Nordheim stress in P- and N-Channel transistors, in IEDM Tech. Dig., 1991, p. 65. [4] C. Gabriel and J. C. Mitchener, Reduced device damage using an ozone based photoresist removal process, Proc. SPIE, vol. 1086, p. 598, 1989. [5] F. Shone et al., Gate oxide charging and its elimination for metal antenna capacitor and transistor in VLSI CMOS double layer metal technology, in VLSI Symp. Tech. Dig., 1989, p. 73. [6] Y. Kawamoto, MOS gate insulator breakdown caused by exposure to plasma, in Proc. 1985 Dry Process Symp., Oct. 1985, p. 132. [7] K. Tsunokuni, K. Nojiri, S. Kuboshima, and K. Hirobe, The effect of charge build-up on gate oxide breakdown during dry etching, in Ext. Abst. 19th Conf. Solid-State Dev. and Mat., 1987, p. 195. [8] I.-W. Wu, R. H. Bruce, G. B. Anderson, M. Koyanagi, and T. Y. Huang, Damage to gate oxides in reactive ion etching, Proc. SPIE, vol. 1185, p. 284, 1989. [9] S. Fang and J. McVittie, Thin-oxide damage from gate charging during plasma processing, IEEE Electron Device Lett., vol. 13, p. 288, May 1992. [10] H. Shin, C.-C. King, T. Horiuchi, and C. Hu, Thin oxide charging current during plasma etching of aluminum, IEEE Electron Device Lett., vol. 12, p. 404, Aug. 1991. [11] C. T. Gabriel, Gate oxide damage from polysilicon etching, J. Vac. Sci. Technol. B, vol. 9, no. 2, p. 370, Mar./Apr. 1991. [12] H. Shin, C.-C. King, and C. Hu, Thin oxide damage by plasma etching and ashing processes, in Proc. 1992 Int. Rel. Phys. Symp., 1992, p. 37. [13] S. Fang and J. McVittie, A model and experiments for thin oxide damage from wafer charging in magnetron plasmas, IEEE Electron Device Lett., vol. 13, p. 347, June 1992. [14] M. Sekine, et al., Gate oxide breakdown phenomena in magnetized plasma, in Proc. 1991 Dry Process Symp., 1991, p. 99. [15] W. Greene, J. Kruger, and G. Kooi, Magnetron etching of polysilicon: Electrical damage, J. Vac. Sci. Tech., p. 366, 1991. [16] T. Namura et al., Wafer charging in different types of plasma etchers, Proc. SPIE, vol. 1593, p. 11, Sept. 1991. [17] H. Shin, K. Noguchi, X.-Y. Qian, N. Jha, G. Hills, and C. Hu, Spatial distributions of thin oxide charging in reactive ion etcher and MERIE etcher, IEEE Electron Device Lett., vol. 14, p. 88, Feb. 1993. [18] T. Namura, H. Okada, Y. Naitoh, Y. Todokoro, and M. Inoue, Charge buildup in magnetized process plasma, Jpn. J. Appl. Phys., vol. 30, no. 7, p. 1576, July 1991. [19] H. Muto, H. Fujii, and K. Nakanishi, A mechanism of gate oxide deterioration during As+ ion implantation, IEEE Trans. Electron Devices, vol. 38, p. 1296, 1991. [20] H. Shin and C. Hu, Dependence of plasma-induced oxide charging current on Al antenna geometry, IEEE Electron Device Lett., vol. 13, p. 50, Dec. 1993. [21] H. Shin, Z.-J. Ma, and C. Hu, Impact of plasma charging damage and diode protection on scaled thin oxide, in IEDM Tech. Dig., 1993, p. 467. [22] K. Noguchi and K. Okumura, The effect of plasma-induced oxide and interface degradation on hot-carrier reliability, in Proc. 1994 Int. Rel. Phys. Symp., 1994, p. 232. [23] R. Tu, et al., Berkeley reliability Tools-BERT, IEEE Trans. Computer- Aided Design, vol. 12, p. 1542, Oct. 1993.

1400 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 9, SEPTEMBER 1997 [24] I. C. Chen, S. Holland, and C. Hu, A quantitative physical model for time-dependent breakdown in SiO 2, in Proc. 1985 Int. Rel. Phys. Symp., 1985, p. 24. [25] J. Lee, I. C. Chen, and C. Hu, Modeling and characterization of oxide reliability, IEEE Trans. Electron Devices, vol. 35, p. 2268, Dec. 1988. [26] E. Rosenbaum, P. Lee, R. Moazzami, P. Ko, and C. Hu, Circuit reliability simulator-oxide breakdown module, in IEDM Tech. Dig., Dec. 1989, p. 331. [27] R. Moazzami, J. C. Lee, and C. Hu, Temperature acceleration of timedependent dielectric breakdown, IEEE Trans. Electron Devices, vol. 36, p. 2462, Nov. 1989. [28] J. King and C. Hu, Effect of low- and high-temperature anneal on process-induced damage of gate oxide, IEEE Electron Device Lett., Nov. 1994. Robert Tu received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley, in 1991, 1993, and 1996, respectively. He is currently with Advanced Micro Devices, Sunnyvale, CA, with the Programmable Logic Technology Group doing process integration. His research interests include silicon-on-insulator MOSFET modeling, device reliability modeling, and CAD. Hyungcheol Shin (S 92 M 93) received the B.S. degree (magna cum laude) and the M.S. degree in electronics engineering from the Seoul National University, Seoul, Korea, in 1985 and 1987, respectively. He received the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1993. From 1994 to 1996, he worked at Motorola Advanced Custom Technologies, Mesa, AZ, as a Device Engineer. He is now with Korea Advanced Institute of Science and Technology, Taejon, Korea, as an Assistant Professor. His research interests include nano electronics, SOI technology development, thin dielectrics, and VLSI device reliability. He has also conducted research on silicon image sensors. He has authored and coauthored one book and more than 30 research papers. Dr. Shin received the Best Paper Award at the 1991 AVS Plasma Etch Symposium. Chenming Hu (S 71 M 76 SM 83 F 90), for a photograph and biography, see p. 287 of the February 1997 issue of this TRANSACTIONS. Joseph C. King received the B.S. degree from the National Taiwan University, Taipei, Taiwan, R.O.C., and the M.S. and Ph.D. degrees from the University of California, Berkeley, in 1991 and 1996, respectively, all in electrical engineering. In 1996, he joined Rockwell Semiconductor Systems, Newport Beach, CA. He has been engaged in the research and development of submicron CMOS technology.