Implition Grphs n Logi Testing Vishwni D. Agrwl Jmes J. Dnher Professor Dept. of ECE, Auurn University Auurn, AL 36849 vgrwl@eng.uurn.eu www.eng.uurn.eu/~vgrwl Joint reserh with: K. K. Dve, ATI Reserh, Yrley, PA M. L. Bushnell, Rutgers University, Pistwy,NJ 2/2/05 VLSI D&T Group Seminr
Implition Grph An implition grph (IG) represents the implition reltions etween pirs of Boolen vriles. n implition ontrpositive implition 2/2/05 VLSI D&T Group Seminr 2
Implition Grph of Logi Gte = Boolen flse funtion: = 0 + + = 0 Chkrhr et l. -- IEEE-D&T, 990 2/2/05 VLSI D&T Group Seminr 3
Glol Implitions n Trnsitive Closure Trnsitive losure ege 0 2/2/05 VLSI D&T Group Seminr 4
Trnsitive Closure Trnsitive losure (TC) of irete grph ontins the sme set of noes s the originl grph. If there is irete pth from noe to, then the trnsitive losure ontins n ege from to. A Grph Trnsitive Closure A grph 0 0 0 0 0 0 0 0 0 0 0 0 0 2/2/05 VLSI D&T Group Seminr 5 0 0 0 0 0 0 0 0 0 0
Trnsitive Closure: Wrshll s Algorithm proeure Wrshll (vr A : rry[ n, n] of oolen; C : rry[ n, n] of oolen); { Wrshll mkes A the trnsitive losure of C } vr i, j, k : integer; egin for i := to n o for j := to n o A[i, j] := C[i, j]; for k := to n o O(n 3 ) for i := to n o for j := to n o if A[i, j] = flse then A[i, j] := A[i, k] n A[k, j] en; { Wrshll } S. Wrshll, A Theorem on Boolen Mtries, J. ACM, vol. 9, no., pp. -2. A. V. Aho, J. E. Hoproft n J. D. Ullmn, Dt Strutures n Algorithms, Reing, Msshusetts: Aison-Wesley, 983, p. 23. 2/2/05 VLSI D&T Group Seminr 6
Trnsitive Closure: Upte Algorithm Strt onstruting trnsitive losure (TC) y pling ll noes n no eges. This ege-less grph is its own TC. A eges to TC in ny ritrry orer For eh ege i j fin P : set of prent noes of i C : set of hil noes of j A eges {P, i } {C, j } K. Dve, Using Contrpositive Rule to Enhne the Implition Grphs of Logi Ciruits, Mster s Thesis, Rutgers University, Dept. of ECE, Pistwy, New Jersey, My 2004. 2/2/05 VLSI D&T Group Seminr 7
Upte Algorithm p i p2 {P, i } {C, j } j 2/2/05 VLSI D&T Group Seminr 8
Upte Algorithm Exmple A irete grph Trnsitive losure 2/2/05 VLSI D&T Group Seminr 9
Logi Testing: Stuk-t Fult A type of fult, whih uses line to hol onstnt logi vlue, irrespetive of hnge of stte t previous stges. There re two types of stuk-t-fults: Stuk-t- Stuk-t-0 Detetion of fult requires the fult to e tivte n its effet oserve t primry output (PO). Fult s-- is etetle, if following onitions re simultneously stisfie: = 0 O = fult is tivte oservility is true 2/2/05 VLSI D&T Group Seminr 0
Oservility Vriles Oservility vrile of signl represents whether or not tht signl is oservle t PO. It n e true or flse. O O = O (PO) O O C O = 0 O O + O + O O = 0 Agrwl, Bushnell n Lin, Reunny Ientifition using Trnsitive Closure, Pro. Asin Test Symp., 996, pp. 5-9. O 2/2/05 VLSI D&T Group Seminr
Reunnt Fults A fult tht hs no test is lle n untestle fult. Any untestle fult in omintionl iruit is reunnt fult euse it oes not use ny hnge in the input/output logi funtion of the iruit. Ientifition of reunnt fults is useful euse they n e remove from testing onsiertion, or from hrwre Fult stuk-t- is reunnt if either or O or O or O no ontrollility no oservility no rivility no rivility 2/2/05 VLSI D&T Group Seminr 2
Limittion of Implition Grph s--0 e s--0 Ciruit with two reunnt fults O O Implition grph (some noes n eges not shown) Implition grph shows no implitions of n on their oservilities. 2/2/05 VLSI D&T Group Seminr 3
Aing Prtil Implitions = Boolen flse funtion: = 0 + + = 0 Λ V Henftling n Wittmnn, AEÜ, 995 (Λ noe) Dve, Mster s Thesis, 2004 (V noe) Λ n V noes represent prtil implitions 2/2/05 VLSI D&T Group Seminr 4
Using Prtil Implitions s--0 e s--0 Ciruit with two reunnt fults O O Implition grph (some noes n eges not shown) Implition Prtil implition Trnsitive losure ege 2/2/05 VLSI D&T Group Seminr 5
Another Exmple s--0 s-- s--0 s-- s--0 e e Λ 2 Λ Λ 3 e V V 2 Λ 4 2/2/05 VLSI D&T Group Seminr 6
Results on ISCAS Ciruits Reunnt fults ientifie n run time Ciruit Totl fults TRAN Chkrhr et l. FIRE Iyer n Armovii Imp. grph Meht et l. Enhne Imp. Grph Dve et l. Re. fults CPU s Re. Fults CPU s Re. Fults CPU s Re. Fults CPU s 908 879 7 3.0 6.8 2 3.2 5 5.7 2670 2747 5 95.2 29.5 59 4.0 69 6.0 7552 7550 3 308.0 30 4.7 5.5 65 7.7 s238 355 69 7.4 6.9 20 2.6 5 5.4 Sun SPARC5 CPU Se. Sun SPARC2 CPU Se. 2/2/05 VLSI D&T Group Seminr 7
Referene Methos TRAN ATPG S. T. Chkrhr, V. D. Agrwl n S. G. Rothweiler, A Trnsitive Closure Algorithm for Test Genertion, IEEE Trns. CAD, vol. 2, no. 7, pp. 05-028, July 993. FIRE Implition nlysis M. A. Iyer n M. Armovii, FIRE: A Fult-Inepenent Comintionl Reunny Ientifition Algorithm, IEEE Trns. VLSI Systems, vol. 4, no. 2, pp. 295-30, June 996. Implition Grph V. J. Meht, Reunny Ientifition in Logi Ciruits using Extene Implition Grph n Stem Unoservility Theorems, Mster s Thesis, Rutgers University, Dept. of ECE, New Brunswik, NJ, My 2003. K. K. Dve, Using Contrpositive Rule to Enhne the Implition Grphs of Logi Ciruits, Mster s Thesis, Rutgers University, Dept. of ECE, New Brunswik, NJ, My 2004. 2/2/05 VLSI D&T Group Seminr 8
C908: Unientifie Reunnies Reunnt fults (s--) 952 953 926 949 0 0/ 979 887 0 74 Totl reunnt fults = 7; ientifie = 5 2/2/05 VLSI D&T Group Seminr 9
C535: Unientifie Reunny Reunnt fult (s--) PI 0/ PI 0 0/ 0 0/ 0 0/ 0 0 PO Totl reunnt fults = 59; ientifie = 58 2/2/05 VLSI D&T Group Seminr 20
0 C535: Continue... Reunnt fult (s--) PI 0/ PI 0/ 0/ 0 0 0/ PO 0 0 2/2/05 VLSI D&T Group Seminr 2
Conlusion Prtil implitions improve fult-inepenent reunny ientifition present results re the est known. Trnsitive losure omputtion run times re empirilly liner in the numer of noes for enhmrk iruits -- the known worst-se omplexity is O(N 3 ) for N noes. Upte lgorithm n effiiently ompute trnsitive losure when implition grph hs sprse onnetivity. Wekness of implition metho: Oservility of fnout stems. Reent work hs shown tht mny unoservle fnout stems n e ientifie from trnsitive losure nlysis. Reonvergent gte Domintor 2/2/05 VLSI D&T Group Seminr 22 Oservility of hs no iret reltion to oservilities of n, ut n e relte to tht of