EE247 Lecure 18 ADC Converers Sampling (coninued) Sampling swich charge injecion & clock feedhrough Complemenary swich Use of dummy device Boom-plae swiching Track & hold T/H circuis T/H combined wih summing/difference funcion T/H circui incorporaing gain & offse cancellaion T/H aperure uncerainy EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 1 Pracical Sampling Issues v IN M1 C v OUT Swich induced noise due o M1 finie channel resisance Clock jier Finie R sw limied bandwidh finie acquisiion ime R sw = f(n ) disorion Swich charge injecion & clock feedhrough EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 2
Sampling Swich Charge Injecion & Clock Feedhrough Swiching from Track o Hold V H +V h M1 V O V L V O ΔV C s off Firs assume is a DC volage When swich urns off offse volage induced on C s Why? EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 3 Sampling Swich Charge Injecion MOS xor operaing in riode region Cross secion view L D Disribued channel resisance & gae & juncion capaciances G C ov C ov L S C j sb B C j db D C HOLD Channel disribued RC nework formed beween G,S, and D Channel o subsrae juncion capaciance disribued & volage dependan Drain/Source juncion capaciors o subsrae volage dependan Over-lap capaciance C ov = L D xwxc ox associaed wih G-S & G-D overlap EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 4
Swich Charge Injecion Slow Clock V H Device sill conducing +V h V L - off Slow clock clock fall ime >> device speed During he period (- o off ) curren in channel discharges channel charge ino low impedance signal source Only source of error Clock feedhrough from C ov o C s EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 5 Swich Clock Feedhrough Slow Clock C ov V H +V h D C Δ = + ( ε ) ( ) ov V Vi Vh VL Cov + Cs Cov ( V h V L) Cs o = i+δ + C s V L V O V V V C C C V V V V V V 1 V V V = V 1+ + V ( ) ( ) ov ov ov o = i i+ h L = i h L C s C s Cs o i os - off ΔV Cov C where ε = ; V = V V C s ( ) ov os h L Cs EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 6
Swich Charge Injecion & Clock Feedhrough Slow Clock- Example 10μ/0.18μ M1 VO V H +V h C s =1pF ' 2 ov μ ox μ h L C = 0.1fF / C = 9fF / V = 0.4V V = 0 Cov 10μx0.1fF / μ ε = = =.1% Cs 1pF Allowing ε = 1/ 2LSB ADCresoluion < ~9bi C V = V V = 0.4mV ( ) ov os h L Cs V L V O - off ΔV EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 7 Swich Charge Injecion & Clock Feedhrough Fas Clock Q ch M1 VO V H +V h nqch n+m=1 mq ch C s =1pF V L V O ΔV off Sudden gae volage drop no gae volage o esablish curren in channel channel charge has no choice bu o escape ou owards S & D EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 8
Swich Charge Injecion & Clock Feedhrough Fas Clock Clock Fall-Time << Device Speed: C 1 Q Δ V = V V ( ε ) ε ( ) ov ch o H L Cov + Cs 2 Cs ( V V ) (( )) C 1 WC L V V V ov ox H i h H L Cov + Cs 2 Cs o = i + + os 1 WCoxL V V 1 V where = 2 Cs C 1 WC L V V = ( V V ) C 2 C ov os H L s ( V ) ox H h s For simpliciy i is assumed channel charge divided equally beween S & D Source of error channel charge ransfer + clock feedhrough via C ov o C s V H V L V O off +V h ΔV EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 9 Swich Charge Injecion & Clock Feedhrough Fas Clock- Example M1 10μ/0.18μ VO C s =1pF V H +V h ff ff Cov = 0.1, Cox = 9,V 2 h = 0.4V,VDD = 1.8V, VL = 0 μ μ WLCox 10μx0.18μx9fF / μ ε = 1/ 2 = = 1.6% ~5 bi C 1pF ov os H L s s 2 ( V ) C 1 WCoxL VH h V = ( V V ) = 1.8mV 14.6mV = 16.4mV C 2 C s V L V O off ΔV EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 10
Swich Charge Injecion & Clock Feedhrough Example-Summary 1.6% ε 16mV V OS.1% Clock fall ime 0.4mV Clock fall ime Error funcion of: Clock fall ime Inpu volage level Source impedance Sampling capaciance size Swich size Clock fall/rise should be conrolled no o be faser (sharper) han necessary EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 11 Swich Charge Injecion Error Reducion How do we reduce he error? Reduce swich size o reduce channel charge? 1Qch Δ Vo = 2Cs Cs Ts τ = RONC s = (noe: = kτ ) W μcox ( VGS Vh) 2 L Consider he figure of meri (FOM): W μcox ( VGS Vh) 1 L Cs FOM = 2 τ ΔV C WC L V V V 2 FOM μ L (( )) o s ox H i h Reducing swich size increases τ increased disorion no a viable soluion Small τ and small ΔV use minimum chanel lengh (mandaed by echnology) For a given echnology τ x ΔV ~ consan EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 12
Sampling Swich Charge Injecion & Clock Feedhrough Summary Exra charge injeced ono sampling capacior @ swich device urn-off Channel charge injecion Clock feedhrough o C s via C ov Issues due o charge injecion & clock feedhrough: DC offse induced on hold C Inpu dependan error volage disorion Soluions: Slowing down clock edges as much as possible Complemenary swich? Addiion of dummy swiches? Boom-plae sampling? EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 13 Swich Charge Injecion & Clock Feedhrough Complemenary Swich V H B B B V L In slow clock case if area of n & p devices widhs are equal (W n =W p ) effec of overlap capacior for n & p devices o firs order cancel (cancellaion accuracy depends on maching of n & p widh and overlap lengh L D ) Since in CMOS echnologies μ n ~2.5μ p choice of W n =W p no opimal from lineariy perspecive (W p >W n preferable) EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 14
Swich Charge Injecion Complemenary Swich Fas Clock ( ) Q = W C L V V V ch n n ox n H i h n ch p p ox p i L ( Vh p ) Q = W C L V V 1 Qch n Q ΔVo 2 Cs C ch p s V H V L ( ε ) V = V 1+ + V o i os 1 WnCoxLn+ WpCoxLp ε 2 Cs In fas clock case To 1 s order, offse due o overlap caps cancelled for equal device widh Inpu volage dependan error worse! B EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 15 Swich Charge Injecion Dummy Swich M1 B M2 V O C s V H B Q 1 Q 2 W M2 =1/2W M1 1 Q Q Q 2 M1 M1 1 ch + ov V L M2 M2 2 ch + ov Q Q 2Q 1 For W W Q Q & Q 2Q 2 M 1 M2 M 2 = M1 2 = 1 ov = ov EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 16
Swich Charge Injecion Dummy Swich M1 B M2 V O C s V H B Q 1 Q 2 W M2 =1/2W M1 V L Dummy swich same L as main swich bu half W Main device clock goes low, dummy device gae goes high dummy swich acquires same amoun of channel charge main swich needs o lose Effecive only if exacly half of he charge sored in M1 is ransferred o M2 (depends on inpu/oupu node impedance) and requires good maching beween clock fall/rise EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 17 Swich Charge Injecion Dummy Swich R M1 B M2 W M2 =1/2W M1 VO C s C s To guaranee half of charge goes o each side creae he same environmen on boh sides Add capacior equal o sampling capacior o he oher side of he swich + add fixed resisor o emulae inpu resisance of following circui Issues: Degrades sampling bandwidh EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 18
Dummy Swich Effeciveness Tes Dummy swich W=1/2W main As Vin is increased Vc1-Vin is decreased channel charge decreased less charge injecion Noe large Ls good device area maching Ref: L. A. Biensman e al, An Eigh-Channel 8 13i Microprocessor Compaible NMOS D/A Converer wih Programmable Scaling, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 19 φ + V O+ Swich Charge Injecion Differenial Sampling Cs V V = V V V = V o+ o od i+ i id V + V V + V Voc = = 2 2 Vo+ = Vi+ 1+ 1 + Vos1 V = V 1+ + V o+ o i+ i Vic ( ε ) ( ε ) ( ε + ε ) o i 2 os2 ( ε ε ) V = V + V + V + V V 2 1 2 od id id 1 2 ic os1 os2 - Cs To 1 s order, offse erms cancel V O- Noe gain error ε sill abou he same Has he advanage of beer immuniy o noise coupling and cancellaion of even order harmonics EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 20
Avoiding Swich Charge Injecion Boom Plae Sampling D M1 V H Cs V O V L D M2 Swiches M2 opened slighly earlier compared o M1 Injeced charge by he opening of M2 is consan since is GS volage is consan & eliminaed when used differenially Since C s boom plae is already open when M1 is opened No signal dependan charge injeced on C s EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 21 Flip-Around Track & Hold S2A D D v IN D C S3 S1A S2 v OUT S1 Concep based on boomplae sampling v CM EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 22
Flip-Around T/H-Basic Operaion high S2A D D v IN D S1A C S2 S3 Charging C vout Q φ1 =V IN xc S1 v CM Noe: Opamp has o be sable in uniy-gain configuraion EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 23 Flip-Around T/H-Basic Operaion high S2A D D D C S3 Holding v IN S1A S2 v OUT S1 Q φ2 =V OUT xc V OUT =V IN v CM EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 24
Flip-Around T/H - Timing S2A D D v IN D C S3 S1A S1 S2 v CM vout S1 opens earlier han S1A No resisive pah from C boom plae o Gnd charge can no change "Boom Plae Sampling" EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 25 Charge Injecion A he insan of ransiioning from rack o hold mode, some of he charge sored in sampling swich S1 is dumped ono C Wih "Boom Plae Sampling", only charge injecion componen due o opening of S1 and is o firs-order independen of v IN Only a dc offse is added. This dc offse can be removed wih a differenial archiecure EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 26
Flip-Around T/H Consan swich S o minimize disorion S2A D D v IN D S1A C S2 S3 v OUT S1 v CM Noe: Among all swiches only S1A & S2A experience full inpu volage swing EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 27 Flip-Around T/H S1 is chosen o be an n-channel MOSFET Since i always swiches he same volage, i s onresisance, R S1, is signal-independen (o firs order) Choosing R S1 >> R S1A minimizes he non-linear componen of R = R S1A + R S1 Typically, S1A is a wide (much lower resisance han S1) & consan S swich In pracice size of S1A is limied by he (nonlinear) S/D capaciance ha also adds disorion If S1A s resisance is negligible delay depends only on S1 resisance S1 resisance is independen of V IN error due o finie ime-consan independen of V IN EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 28
Differenial Flip-Around T/H Choice of Sampling Swich Size THD simulaed w/o sampling swich boosed clock -45dB THD simulaed wih sampling swich boosed clock (see graph) Ref: K. Vleugels e al, A 2.5-V Sigma Dela Modulaor for Broadband Communicaions Applicaions IEEE JSSC, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 29 Differenial Flip-Around T/H S11 S12 Offse volage associaed wih charge injecion of S11 & S12 cancelled by differenial naure of he circui During inpu sampling phase amp oupus shored ogeher Ref: W. Yang, e al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC Wih 85-dB SFDR a Nyquis Inpu, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 30
Differenial Flip-Around T/H Gain=1 Feedback facor=1 φ2 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 31 Differenial Flip-Around T/H Issues: Inpu Common-Mode Range Δn-cm =V ou_com -V sig_com Amplifier needs o have large inpu common-mode compliance EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 32
Inpu Common-Mode Cancellaion Noe: Shoring swich M3 added Ref: R. Yen, e al. A MOS Swiched-Capacior Insrumenaion Amplifier, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 33 Inpu Common-Mode Cancellaion Track mode (φ high) V C1 =V I1, V C2 =V I2 V o1 =V o2 =0 Hold mode (φ low) V o1 +V o2 =0 V o1 -V o2 = -(V I1 -V I2 )(C 1 /(C 1 +C 3 )) Inpu common-mode level removed EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 34
Swiched-Capacior Techniques Combining Track & Hold wih Oher Funcions T/H + Charge Redisribuion Amplifier T/H & Inpu Difference Amplifier T/H & Summing Amplifier Differenial T/H Combined wih Gain Sage Differenial T/H Including Offse Cancellaion EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 35 T/H + Charge Redisribuion Amplifier Track mode: (S1, S3 on S2 off) V C1 =V os V IN, V C2 =0 V o =V os EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 36
T/H + Charge Redisribuion Amplifier Hold Mode 2 1 Hold/amplify mode (S1, S3 off S2 on) Offse NOT cancelled, bu no amplified Inpu-referred offse =(C 2 /C 1 ) x V OS, & ofen C 2 <C 1 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 37 T/H & Inpu Difference Amplifier Sample mode: (S1, S3 on S2 off) V C1 =V os V I1, V C2 =0 V o =V os EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 38
Inpu Difference Amplifier Con d Subrac/Amplify mode (S1, S3 off S2 on) During previous phase: V C1 =V os V I1, V C2 =0 V o =V os 1 Offse NOT cancelled, bu no amplified Inpu-referred offse =(C 2 /C 1 )xv OS, & C 2 <C 1 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 39 T/H & Summing Amplifier EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 40
T/H & Summing Amplifier Con d Sample mode (S1, S3, S5 on S2, S4 off) V C1 =V os V I1, V C2 =V os -V I3, V C3 =0 V o =V os EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 41 T/H & Summing Amplifier Con d Amplify mode (S1, S3, S5 off, S2, S4 on) 3 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 42
Differenial T/H Combined wih Gain Sage Employs he previously discussed echnique o eliminae he problem associaed wih high common-mode volage excursion a he inpu of he opamp Ref: S. H. Lewis, e al., A Pipelined 5-Msample/s 9-bi Analog-o-Digial Converer IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 43 Differenial T/H Combined wih Gain Sage φ1 High Ref: S. H. Lewis, e al., A Pipelined 5-Msample/s 9-bi Analog-o-Digial Converer IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 44
Differenial T/H Combined wih Gain Sage Gain=4C/C=4 Inpu volage common-mode level removed opamp can have low inpu common-mode compliance Amplifier offse NOT removed Ref: S. H. Lewis, e al., A Pipelined 5-Msample/s 9-bi Analog-o-Digial Converer IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 45 Differenial T/H Including Offse Cancellaion Operaion during offse cancellaion phase shown Auxilary inpus added wih A main /A aux.=10 During offse cancellaion phase: Aux. amp configured in uniy-gain mode: Vou=V os main offse sored on C AZ & canceled Ref: H. Ohara, e al., "A CMOS programmable self-calibraing 13-bi eigh-channel daa acquisiion peripheral," IEEE Journal of Solid-Sae Circuis, vol. 22, pp. 930-938, December 1987. EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 46
Differenial T/H Including Offse Cancellaion Operaional Amplifier Operaional amplifier dual inpu folded-cascode opamp M3,4 auxiliary inpu, M1,2 main inpu To achieve 1/10 gain raio W M3, 4 =1/10x W M1,2 & curren sources are scaled by 1/10 M5,6,7 common-mode conrol Oupu sage dual cascode high DC gain V ou =g m1,2 r o n1 + g m3,4 r o n2 Ref: H. Ohara, e al., "A CMOS programmable self-calibraing 13-bi eigh-channel daa acquisiion peripheral," IEEE Journal of Solid-Sae Circuis, vol. 22, pp. 930-938, December 1987. EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 47 Differenial T/H Including Offse Cancellaion Phase + - (V INAZ+ -V INAZ- )= -g m1,2 /g m3,4 V offse V offse During offse cancellaion phase AZ and S1 closed main amplifier offse amplified by g m1 /g m2 & sored on C AZ Auxiliary amp chosen o have lower gain so ha: Aux. amp charge injecion associaed wih opening of swich AZ reduced by A aux /A main =1/10 Insignifican increase in power dissipaion resuling from addiion of aux. inpus Requires an exra auo-zero clock phase EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 48
V V CLK Track & Hold Aperure Time Error V CLK x n +V TH n M1 V O x n C s x Time Transiion from rack o hold: Occurs when device urns fully off V CLK =n +V TH Sharp fall-ime wr signal change no aperure error EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 49 V x V CLK x x Track & Hold Aperure Time Error n +V TH n Time Slow falling clock aperure error n =A sin(2π f in ) ε= f in xax fall /V CLK SDR= - 20logε -4[dB] (imperical see Ref.) Example: Nyquis rae 10-bi ADC & A=V CLK /4 SQNR=62dB for disorion due o aperure error < quan noise fall < 2x10-3 /f in Wors case: f in = f s /2 fall < 4x10-3 /f s e.g. f s =100MHz, fall <40psec Ref: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold echnique using a Miller hold capaciance," IEEE Journal of Solid-Sae Circuis, vol. 26, pp. 643-651, April 1991. EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 50
Track & Hold Aperure Time Error Aperure error analysis applies o simple sampling nework Boom plae sampling minimizes aperure error Boosed clock reduces aperure error Clock edge fall/rise rade-off beween swich charge injecion versus aperure error Ref: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold echnique using a Miller hold capaciance," IEEE Journal of Solid-Sae Circuis, vol. 26, pp. 643-651, April 1991. EECS 247- Lecure 18 Nyquis Rae ADCs-Sampling Neworks 2008 H.K. Page 51