Stop Watch (System Controller Approach)

Stop Watch (System Controller Approach)

Problem Design a stop watch that can measure times taken for two events Inputs CLK = 6 Hz RESET: Asynchronously reset everything X: comes from push button First Push: Start timer Second Push: Store the time taken for the first event Third Push: Store the time taken for the second event SEL: select output (High: first event time, Low: second event time) Outputs Two decimal digits to be connected to two seven segment displays Can display ~ 99

Overall Architecture Design CLK TENSEC SEC RESET X SEL Which LBB (among those we learn in the class) and how many? How to decompose the whole system into data part and control part?

Design System Architecture First step: divide the system into a control unit and data unit Data unit stores, routes, combines, and generally process data Control unit starting & stopping the process, testing conditions, and deciding what to do next

System controller design

Table (Variable Entered Table) P.S. N.S. Output State symbol Q Q D D S S ENCNT A B C unused

Excitation Eqs, Output Eqs Q Q D= D= Q Q Q S= S= ENCNT=

Alternative (VHDL program)

4-bit Serial Adder (Decomposing state machines, synchronous design methodology, system controller design)

Review of combinational adders -bit full adder and 4-bit ripple adder

Binary serial adder Serial input feed (two data streams A and B) Generate serial output CLR clear the previous carry synchronously A i CLR HOLD S i HOLD hold the previous value of the carry B i Carry

Binary serial adder implementation LS83: dual bit full adders carry A B Q(Carry) S

Problem Statement Design a 4-bit adder based on a serial approach Parallel feed of X and X2 Parallel out of Y comes out after few cycles Final carry available X X 2 4 4 START may be long (External guy will negate START only after detecting DONE) START CONTROL 4-bit adder 4 DONE if CONTROL=, X plus X 2 Y if CONTROL=, X plus Y Y CARRY Y

Start from LBB Here, we have some basic building blocks in mind 4-bit shift registers, binary serial adder, etc Tie these elements together and make them controllable from the outside world We want to take maximum advantage of common building blocks (MSI chips that are available)

Design System Architecture First step: divide the system into a control unit and data unit Data unit stores, routes, combines, and generally process data Control unit starting & stopping the process, testing conditions, and deciding what to do next

Data unit & Control unit X X 2 4 4 START Shift register Shift register 4 Y CONTROL Binary serial adder Carry Control unit Data unit DONE

Architecture X RIN A B C D S S LIN SYSCLK CLR Q A Q B Q C Q D 74LS94 CLR HOLD X2 Ai Bi Binary Serial Adder Si RIN A B C D S S LIN SYSCLK CARRY SYSCLK CLR Q A Q B Q C Q D 74LS94 CARRY Y START Control Unit DONE CONTROL

Decomposing state machine Second step: the state machine part (control unit) can be decomposed into several parts Main machine (system controller) provides the primary inputs and outputs and does top level control Submachines perform lower-level steps under control of main machine Typical submachine counter Saves 2 n states in main machine Easier to follow the control 2 bit counter to count # of bits added Our system controller

Architecture X S S RIN A B C D S S LIN CLR_L HOLD_L SYSCLK CLR Q A Q B Q C Q D 74LS94 CLR HOLD X 2 S 2 S 2 SYSCLK Ai Bi Binary Serial Adder Si RIN A B C D S S LIN SYSCLK CLR Q A Q B Q C Q D 74LS94 CARRY Y 3 Y 2 Y Y C4 START CONTROL System Controller DONE CLRCNTR CLRCNTR_L SYSCLK D C B A CLR 74LS63 RCO Q D Q C Q B Q A LOAD EnP EnT S S S 2 S 2 CLR HOLD C4

System controller design a b c d START CLRCNTR HOLD DONE,, START CLR X CONTROL S S X S S else Hold),, Load (if ), (Load 2 2 2 ), (Shift ), (Shift 2 2 2 X S S X S S C4 C4 START (?),, CLRCNT HOLD DONE START

Example results (5) + () ------------- (6) Sate Carry Reg Reg 2 Counter a - - - b - - - c c 2 c 3 c 4 d 5

State assignment and Transition Table QQ QQ (DD) DONE CLRCNTR CLR HOLD S S S2 S2 a ST x x b x CONT CONT c C4 d ST x x x

Excitation and Output Eqs. ST ST C4 D = Q + ST Q D = QQ + Q ST + Q C 4 x x DONE = CLRCNTR = CLR = HOLD = x x c c x x S = S = S 2 = Q Q CONTROL S + 2 = Q CONTROL QQ

Logic Diagram

Asynchronous Inputs and Output Glitches Things to watch out for in synchronous design Clock skew Gating the clock Asynchronous inputs Output glitches

Example Binary counting order for our previous state SS(Load X), assignment DONE, HOLD, CLRCNTR START START CLR a b S S (if CONTROL Load X, else Hold), 2 2 2 START DONE, HOLD d c S S (Shift X ), S S (Shift X ), 2 2 2 START C4 C4 QQ QQ (DD) DONE CLRCNTR CLR HOLD S S S2 S2 a ST x x b x CONT CONT c C4 d ST ST x x x

Focus on part of solution ST - ST C4 ST - D = Q Q + QQ + ST Q D = ST Q Q + ST QQ + C4 Q Q DONE = Q Q + QQ S = Q ST SYSCLK D DONE ST D S ST SYSCLK C4

Asynchronous START Is START synchronous or asynchronous? Could be either Assume asynchronous (comes from another system not using same SYSCLK) Look at transition from to by negating START What happens if t s, t h of D f/fs are not satisfied due to asynchronous START? Usually stay at or go to Problem? early change to START= => late change to START= => Problem: unexpected results can happen Delays not equal, f/fs different Generally could do either if t s, t h not satisfied on occasion

Synchronize START (Synchronizer) START D START _ SYNC SYSCLK Change right after SYSCLK edge, so START_SYNC will satisfy t s, t h of f/fs ST Q SYSCLK D DONE ST D S ST SYSCLK C4

Additional Problem? What else besides START_SYNC= or? Metastable stuck in middle for a while What happen if START does not satisfy t s, t h of Synchronizer D f/f START_SYNC not or not for a while Metastability real problem (early versions of several microprocessor chips had this problem!) Synchronizer Failure and Metastability Solutions?

Output Glitch on DONE Look at transition between b= and c= One f/f change at a time because slightly different delay s For a moment in the transition from to = or DONE= between states b ( ) and c ( ) SYSCLK DONE Problem? May or may not. DONE is used for synchronous inputs of other parts not likely the problem What if DONE is used for asynchronous CLR of other parts?

START Put a register (Stabilizer) on output One D f/f on DONE START _ SYNC DONE _ REG D D SYSCLK SYSCLK ST Q SYSCLK D DONE ST D S ST SYSCLK C4

Work? DONE_REG delayed usually no problem SYSCLK DONE DONE_REG Register output not always needed Good state assignment (compare this with our first state assignment) Some good output logics (e.g., S)

Synchronous Design Methodology (Summary) All LBBs and f/fs are clocked by the same common clock signal We use guaranteed LBBs and f/fs by the manufacturer (critical race free!!) Glitches on combinational circuits connecting LBBs and f/fs have no effect, since the control inputs are sampled only after the glitches have had a chance to settle out Three tasks to ensure reliable system operation Minimize and determine the amount of clock skew Ensure that f/fs have positive setup- and hold-time margins Identifying asynchronous inputs, synchronize them with the clock Filter any problematic output glitches with output stabilizers