MODEL REV CHANGE LIST ZL9. Preliminary Release

Similar documents
Centrino DOTHAN CELEROM-M. Page : 3, 4 PCIE. HOST BUS 533MHz HOST BUS 400MHz ALVISO 1257 BGA LVDS RGB TVOUT. Page : 5 ~ 8 DMI I/F PCIE ICH6-M 609 BGA

MODEL REV CHANGE LIST 1 2A 2A 2A 1A 1A 2A 2A 1A 1A 2A 2A 1A 1A 1A 1A 1A 1A 1A CT3/5 MB BOARD. Page CT3/5 MB 31CT3MB CT3MB0031

DC/DC +3V_SRC +5VSUS PG 34 LVDS TVOUT USB2.0 (P3) USB2.0 (P2) USB2.0 (P0~P1,P4) USB2.0 (P0~P7) LAN RTL8100S PG 25 CARDBUS PC7411 PG 21,22,23

SVT-2 REV : 3C


MA1 SYSTEM BLOCK DIAGRAM. Intel Dothan/Yonah Processor. 478 ufcpga. VinaFix.com P3,4. FSB 533/400MHz. Alviso-GM GMCH PCI-EXPRESS 82875GM/GME

ZC1 SYSTEM BLOCK DIAGRAM. Yonah/Merom 479 ufcpga

SIT REV : 3A

SVT REV : 3B

ZR1 Block Diagram PCIE. Yonah / Merom. INTEL Mobile_479 CPU. Page : 3,4. HOST BUS 667/533MHz. Calistoga 945GM / 945PM / 940GML 1466 BGA TVOUT RGB

ZH2 Block Diagram. Yonah/Merom INTEL Mobile_479 CPU. Page : 3,4. HOST BUS 533/667 MHz SDVO CALISTOGA-GM 1466 FCBGA TVOUT RGB. Page : 6 ~ 11 DMI I/F

REV MODEL CHANGE LIST FIRST RELEASE

QUANTA COMPUTER INC.

SHELBY-INTEGRATED CLOCKS ICS PG 17. sdvo SI1362 PG 18 USB2.0 (P5,P6) USB2.0 (P3,P4) USB2.0 (P7) 1394 CONN PG 25 USB2.

Model Name: 8I945GMF. Revision 1.0

CPU Thermal Sensor GMT781-1 EXT.CLOCK GEN ICS954226AG-T. 533 MHZ Memory Dual channel DDR II CHANNEL A DDR II CHANNEL B 1X PCI-E<PORT1> 2.

Intel ECX Form Factor POC Board Based on Intel 915GM Chipset

BL1 CELERON-M/PENTIUM-M. VF-co-cc. INTEL Mobile_479 CPU. Page:2, 3 HOST BUS 400MHZ NB RC410MB/RC410MD ATI. Page: 5, 6, 7, 8 2X PCIE.

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET


EUCLID SPB. Model Name: 8I945GME. Revision 1.0 REAR AUDIO JACK DISCRETE POWER VCORE PWM_ISL6556 ATX, OTHERS POWER RTL8110S/RTL8100C FRONT PANEL

TE1 Block Diagram. Intel. Merom (35W) FSB(667/800MHZ) Page 18 CRT. PCI-E 16X Lan. Crestline GM 533/ 667 MHZ DDR II. Page 5,7,8,9,10,11.

FP7 (CULV) BLOCK DIAGRAM

PA1A BLOCK DIAGRAM NWD/PRESCOTT / SPRINGDALE

ZG5 NB Block Diagram

PCB NO. DM205A SOM-128-EX VER:0.6

VER : 3A. Thermal Sensor & Fan P37 LVDS. E-switch PI2PCIE412-DZHE LVDS MXM III-NB8E (GT/SE/GLM) VRAM 256M VRAM 512M P18 HDMI HDMI P19 P17 SPDIF_MXM

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface.

DM1 DC/DC CPU VR PG 43 PG 39 LVDS. Chrontel 7009 DVOB TV EN-CONDE PG 13 USB ATA 66/100 ATA 66/100 33MHZ, 3.3V PCI PHY PG 32 SWITCH PG 33 USB

Sapporo 1.0 BLOCK DIAGRAM

DC/DC NVDD/+1.2V +3V/+5V +1.05V/+1.8VSUS/+1.8V/+0.9V +1.5V/+2.5V. HOST BUS 533/667 MHz. Page 12,13,14,15 INT_LVDS INT_TVOUT INT_VGA +2.

BIOSTAR GROUP VER:6.7. uatx. 775 CPU, FSB1066, PCI-Ex16, PCI-Ex1,DDR-II* 2, 10/100 LAN,PCI*2

A B C D REVISIONS +3V J39 PHY_INT TXD15 TXPAR PRST AC16 AC21 AD22 AF22 AE22 AF17 AC22 AE16 AE21 AD18 AE7 AD17 AE19 AE20 AF20 AC20 A16 B13 TXD14

XIO2213ZAY REFERENCE DESIGN


#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

PTN3356 Evaluation and Applicaiton Board Rev. 0.10

VM9M Block Diagram Intel UMA

T76S: MEROM/965-PM/ICH8-M/NB8M-SE BLOCK DIAGRAM

BF4 BLOCK DIAGRAM. Mobile P4 prescott or Celeron prescott. North Bridge: 852GME (Montara-GT) Sourth Bridge: ICH4-M. Clocking

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP.

VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:

CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power

INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST

HIgh Voltage chip Analysis Circuit (HIVAC)

CPU NORTH BRIDGE SOUTH BRIDGE

Generated by Foxit PDF Creator Foxit Software For evaluation only.

Quanta Computer Inc. REV 3A PROJECT : ZO1 COVER SHEET 1 OF 1 PROJECT LEADER: JIM HSU DOCUMENT NO: 204 DATE :2007/04/14 MB ASSY'S P/N : 31Z01MB00XX

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766

VIA Apollo ProMedia Board Schematics

PCIextend 174 User s Manual

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0.

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115

UW3 Block Diagram. XDP Page 31. Page 3~5. Port x3 WWAN. Page 20 Page 16. Page 6~10. SIM Card. Page 20 AUDIO CODEC IDT 92HD79BX

SY3. BlOCK DIAGRAM. Intel. TigerPoint. Intel PineView-M VGA LCD. USB CNN x2. Bluetooth WWAN. Camera

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2.

CPU Intel Penryn (Socket P) 3,4. FSB 800/1067 MHz. Cantiga GM LVDS. Panel CRT VGA. x4 DMI. 34 x 34mm 1329 FCBGA HDMI 10~15 DMI X4.

35H MPa Hydraulic Cylinder 3.5 MPa Hydraulic Cylinder 35H-3

Penryn / Cantiga / ICH9-M

CONTENTS: REVISION HISTORY: NOTES:

Penryn 479 ufcpga. NB Cantiga

A[0..14] A[0..15] D[0..7] A[0..15] D[0..7] D[0..7] R/W I/O Phi0 MAP R/W R/W. I/O Phi0 MAP. Phi0 MAP. ROMDIS Phi2. ROMDIS Phi2. Id: 1/

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V

FM6B Hepburn Intel UMA

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0

Merom. Page 3,4 HOST. 667/800MHz NORTH BRIDGE INTEL. Crestline. Page 5 ~ 10. DMI Interface SOUTH BRIDGE INTEL ICH8-M.

SCHEMATIC AD9265 EVALUATION BOARD REV. DRAWING NO. 02_A03421 RELAY CONTROL CHART A A DE N V C L O REVISIONS JUMPER TABLE S.

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK

SW9 (14") BLOCK DIAGRAM

N02 BLOCK DIAGRAM ULV DOTHAN+ALVISO(915GMS)+ICH6-M

Z06 SYSTEM BLOCK DIAGRAM

POWER VGA DC/DC CPU VR PG 51 PG V_ALW/+5V_ALW/+15V_ALW DC/DC. nvidia G86/G72M PCI EXPRESS GFX. PCIEx16 PG 18,19,20,21,22. USB2.

VREF XREF=1/A1,1/B2,7/A2 C103 AVDD 0.1U VDDCORE DRVDD VDDIO ENC+ ENC- AIN+ OVR EC2 XREF=2/B2 XREF=2/B2 XREF=2/B2 XREF=2/A1 XREF=1/A1,7/B1 XREF=2/B2

FM6 Hepburn Intel Discrete GFX

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

Merom / Crestline / ICH8-M

FAN & THERMAL SMSC1423 PG 39 CLOCK SLG8SP513V (QFN-64) PG 17 LVDS. DP Port VGA. USB2.0 x 3. PCIEx1. PCIEx1 USB2.0. PCIEx2 USB2.0. PCIEx1 USB2.

All use SMD component if possible

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%

VISE (MS-6715) Intel (R) Springdale (GMCH) + ICH5 Chipset Intel Northwood & Prescott mpga478b Processor

PCnet-FAST+ Am79C PQFP

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz

Preface. Notebook Computer M560A. Service Manual. Preface

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode

Cover Sheet. Block Diagram DDR SLOT DDR TERMINATOR AGP SLOT PCI SLOTS LAN CONTROLLER

S Note-3 Block Diagram

D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF.

MS Version 0A 06/21/2001 Update. CPU: Willamette/Northwood mpga-478b Processor. System Brookdale Chipset:

SCHEMATIC AD9265 CMOS EVALUATION BOARD REV. DRAWING NO. AD9265CE01A REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O

HF SuperPacker Pro 100W Amp Version 3

Transcription:

E MOEL REV HNGE LIST ZL Preliminary Release Page : dd.pf for Signal quanlity Page : dd R0 0om for UM. Page : seprate STLE# for IE interrupt. Page :add R 0ohm for M-T. Page : enlarge H,H to mm for VG sink Nut. Page : dd 0Kohm for keep the GPIO normal Low. Page : dd R 0ohm for Po Po sound. Page : dd R, Q for STLE#. Page : PL->0.uH,PR->0ohm,PR0->0ohm,PR->0ohm,P->0P,PR->0K for power efficiency. Page 0 : PR0->0K,P->H,P->.U,P->.n,PL->.UH,PR->K for power efficiency. Page 0 : P->000P,P->000P,P->000P,P0->00P,P->00P,P->000P for EMI. Page : PR->0, PR->00K,PR->0,PR->00K for battery charger modify,p->000p for EMI. Page : PR->.K, PL->.0UH for power efficiency. Page : R0->00Kohm, Q->N00,Q->N00,dd Q O0 for SPIF on/off LE. Page :el R, Q for H LE can't light issue. Model Page 0 0 0 FM ZL M TO QUNT PROJET : ZL O. NO.??? REV: SSY: ZLM000 OMPUTER PPROVE Y : Vic Lin # HEKE Y: Jerry Lin # RWING Y : Jerry Wang #0 TE: 00//0 E

PU ORE SENTEH SITSTR SYSTEM V/V MXIM MX Page: LOK GEN IS0 (RTMT-) Page: ZL ELERON-M/PENTIUM-M INTEL Mobile_ PU Page:, RT Page: LVS Page: VPU V_S/VSUS V VPU VSUS V V.VSUS.V 0.VSUS 0.V.V.V_S.V.0V.V NVV ON NP Page: SENTEH S0 SI- SENTEH S SENTEH S Page:0 SENTEH S SENTEH S0 Page: MI IN R-II SOIMM Page: 0 R-II SOIMM Page: 0 PT H Page: 0 IE-O Page: 0 UIO OE Realtek L (L0) Page: Page: SPEKER ST H Page: 0 MP MX MOEM LINE OUT Page: R-II T /00 T /00 RJ Page: Page: Page: Page: T /00 H udio N INTEL LVISO PM/GM Touchpad Page: Page:,,, MI I/F S INTEL IH-M Page:,, K NS P/V Keyboard HOST US /00MHZ LP MHZ Page: Page: FLSH Page: PIE PI-E US PI US MHZ US.0 FN Page: Ti M-T Page:,, UM(option) RG LVS SYSTEM US PORT * US,, Page: MINI-PIE slot Wireless LN (Option) Page: TI PMI PI0 REQ# / GNT# INT# Page: MINI-PI Wireless LN 0 REQ# / GNT# INT#, INT# Page: RELTEK RTL00L REQ0# / GNT0# INT# Page: luetooth US interface US Page: TYPE II SLOT Page: RJ Page: TTERY HRGER MXIM MX Page: PROJET : ZL Quanta omputer Inc. Size ocument Number Rev LOK IGRM ate: Monday, ecember, 00 Sheet of

E U V H#[..] H#[0..] R {} H#[..] H#[0..] {} H# P H#0 H# # 0# U H# H# # # V anias H# 0K_ Q H# # # R H# MT MT {,,} H# # # V H# H# # # H# H/W MONITOR W N00 H# # OF # T H# V H#0 # # W H# R H# 0# # 0 Y H# H# # # 0 Y H# 0K_ Q H# # # U H#0 H# # 0# H# MLK MLK {,,} H# # # E Y H# H# # # H# N00 H# # # F H# V MIL V H# # # E H# R _ V_THM H# # # H# R0 H#0 # # H H# H# 0# # G H# H# # # L H#.U/0V_ U E 0K_ H# # # M H#0 MX_L# {} H# # 0# H H# THERM V -LT KSMT H# # # F H# XN SMT REQUEST T KSMLK H# # # G H# XP SMLK PHSE PHSE H# # # J H# -OVT E SIGNLS SIGNLS 00P_ H# # # M H# THERM G H# # # J F H# MX_OV# {} H#0 # # L E H# 0 mil trace / H# 0# # N F H# # # M H# 0 mil space # H H#0 SLVE RESS: 0# N H# # K H# {} HST0# U ST0# # Y H# {} HST# E ST# # H# # T H# # U H# {} HREQ#0 R REQ0# # V H# {} HREQ# P REQ# # R H# {} HREQ# T REQ# # R H# {} HREQ# P REQ# # R H#0 {} HREQ# T REQ# 0# H# # U H# # V H# {} S# N ERROR S# # U SIGNLS H# # V H# # Y H#.0V R _ H_IERR# # H# IERR# # Y H# # H# {} HREQ0# N REQ0# # H#0 {} PRI# J RITRTION PRI# 0# H# {} NR# L PHSE NR# # 0 H# {} HLOK# J SIGNLS LOK# # H# # H# {} HIT# K HIT# # H#.0V {} HITM# K SNOOP PHSE HITM# # E H#.0V {} EFER# L SIGNLS EFER# # F H#.0V.0V R *./F_ PM0# # H# R *./F_ PM# PM0# # F0 RESPONSE H# PM# PM# # E Q R *./F_ PHSE H#0 R 00/F_ R *./F_ PM# PM# 0# SIGNLS H# PM# # F H# *_ {} HTRY# M TRY# # F H# THERMTRIP# {} RS#0 H _SHT# {} R RS0# # F R _ {} RS# K PMS0 RS# {} RS# L RS# 0M# {} 0M# FERR# 0M# STN0# HSTN0# {} {} FERR# P IGNNE# FERR# STP0# HSTP0# {} {} IGNNE# OMPTIILITY HSTN# {} PUPWRG IGNNE# STN# K {} PUPWRG E SIGNLS SMI# PWRGOO STP# L HSTP# {} {} SMI# SMI# STN# W HSTN# {} HSTP# {} R./F_ TK STP# W HSTN# {} R *./F_ TO TK STN# E IGNOSTI HSTP# {}.0V R 0_ TI TO STP# E & TEST R _ TMS TI SIGNLS R 0_ TRST# TMS HI0# {} HLK_ITP TRST# I0# T0 HI# {} HLK_ITP# ITP_LK0 I# J T0 HI# {} R _ PREQ# ITP_LK I# T 0 HI# {}.0V R0 _ PRY# PREQ# I# 0 0 V R 0_ R# PRY# R# SY# M SY# {} {} R# RY# {} INTR RY# H {} INTR NMI LINT0 {} NMI EXEUTION STPLK# LINT {} STPLK# ONTROL HLK_PU# {} PUSLP# STPLK# LK {,} PUSLP# SIGNLS HLK_PU {} PSLP# SLP# LK0 {} PSLP# PSLP# PUPWRG V {,} THERMTRIP#.0V R0 _ THERM THERM THERMTRIP# PU_PROHOT# THERM THERM THERMTRIP# PROHOT# anias_processor THERML IOE INIT# RESET# PWR# R./F_.0V PUINIT# {} PURST# {} PWR# {} Size ocument Number Rev PU ( HOST US )- PROJET : ZL Quanta omputer Inc. ate: Monday, ecember, 00 Sheet of E

E E OMP OMP OMP0 OMP TEST TEST PU_V Z00 Z00 OMP0 OMP OMP OMP GTLREF0 PU_VI0 {} PU_VI {} PU_VI {} PU_VI {} PU_VI {} PU_VI {} PRSLP# {} SELPS_LK {,} SELPS_LK {,} V_ORE V_ORE V_ORE V_ORE PU_V.0V.0V.0V.0V.V Size ocument Number Rev ate: Sheet of PU ( POWER )- Monday, ecember, 00 Size ocument Number Rev ate: Sheet of PU ( POWER )- Monday, ecember, 00 Size ocument Number Rev ate: Sheet of PU ( POWER )- Monday, ecember, 00 0U/.V/XR(00) *0 0 : STUFF : N 0." max MIL MIL OMP0 ~ max length 00 MIL PLE one 0U & one 0.0U for each V pin T0 T0 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL R _ R _ 0U/.V_ 0 0U/.V_ 0 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ R *K_ R *K_.U/0V_ 0.U/0V_ 0 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ VI0 E VI F VI F VI G VI G VSENSE E VP0 0 VP VP VP VP E VP E VP E VP F0 VP F VP F VP0 F VP K VP L VP L VP M VP M VP N VP N VP P VP P VP0 R VP R VP T VP T VP U VP P VP W VI H N0 N F N N TEST PSI E W W Y Y Y Y 0 0 0 E E E E0 E E E E E0 E E F F F F F F F F F F W W W V V V V V U U U U T T T T T R R R SENSE F OF POWER, GROUN N N VI anias U anias_processor OF POWER, GROUN N N VI anias U anias_processor V00 V V0 V V V V W V0 J V E V E V V V 0 V0 V V Y V K V0 V E V V V V V V W V J V0 V F0 V0 V F V0 0 V F V0 E V F V0 E V0 E V0 E V0 F V0 E V0 E V F V F V F V F0 V F V G V F V E V V V V V0 V V V H V V V V 0 V V Y V U V E V 0 V V V V V V V H V G V0 E V0 F V V N V OMP0 P OMP P OMP OMP GTLREF0 GTLREF E GTLREF G GTLREF TEST TEST F 0 0 E E E E0 E E E E E0 E E F F F F F F F F F F F F G G G G G H H H H J J J J J K K K K K L L L L M M M M M N N N N N P P P P R R OF POWER, GROUN, RESERVE SIGNLS anias U anias_processor OF POWER, GROUN, RESERVE SIGNLS anias U anias_processor 0U/.V_ 0U/.V_ 0U/.V_ 0 0U/.V_ 0 0U/.V_ 0U/.V_ R./F_ R./F_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_.0U/V_.0U/V_ T0 T0.U/0V_.U/0V_ R *K_ R *K_ T T 0U/.V_ 0U/.V_ R./F_ R./F_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ T T 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ R *./F_ R *./F_.U/0V_.U/0V_ T0 T0.0U/V_.0U/V_ 0U/.V_ 0 0U/.V_ 0 0U/.V_ 0U/.V_.0U/V_.0U/V_ T0 T0 R 0_ R 0_ 0U/.V_ 0U/.V_ R K/F_ R K/F_.0U/V_.0U/V_ 0U/.V_ 0 0U/.V_ 0 T0 T0 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_.0U/V_.0U/V_ T T 0U/.V_ 0U/.V_ R *./F_ R *./F_ R./F_ R./F_ T0 T0 0U/.V_ 0U/.V_ R./F_ R./F_ R K/F_ R K/F_ 0U/.V_ 0U/.V_

FS FS FS PU SR PI 0 00 00 OTHN- 00 0 0 00 OTHN- 0 00 0 0 00 00 0 0 0 00 0 0 00 0 00 00 RSV 00 {} LK_EN# {,} STP_PU# {} STP_PI# {,} SELPS_LK Iref=m, Ioh=*Iref SMK SMT G_XIN.MHZ/0PF G_XOUT LK_EN# SELPS_LK IREF VTT_PWRG#/P : change for signal quality M_REF R_HLK_PU R_HLK_PU# R_HLK_MH R_HLK_MH# R_OT R_OT# R_PIE_MINI R_PIE_MINI# R _ *0P_ R.K_ SELPS_LK RP HLK_PU HLK_PU# _PR_S RP HLK_MH HLK_MH# _PR_S RP OT OT# _PR_S RP REFSSLK REFSSLK# _PR_S RP LK_PIE_MINI LK_PIE_MINI# _PR_S V L 0L-0_ LKV R_PIE_IH LK_PIE_IH VPI SR RP 0 R_PIE_IH# LK_PIE_IH# VPI SR# _PR_S.0V.0V V 0U/0V_.0U/0V_.0U/0V_ SR_ST LK_PIE_ST SR_ST RP0 SR#_ST# LK_PIE_ST# SR#_ST# _PR_S R R R0 R _ V_KGREF R_MH_GPLL LK_MH_GPLL VREF SR RP R_MH_GPLL# LK_MH_GPLL# SR# 0 _PR_S *K_ *K_.0U/0V_ PELK_VG_R LK_PIE_VG SR RP0 0K_ PELK_VG_R# LK_PIE_VG# R._ V_KG_ SR# _PR_ SELPS_LK SELPS_LK SELPS0_LK V ITPLK/SR R R ITPLK#/SR# R0 0U/0V_.0U/0V_ V R_PLK_ V_KG_PU ITP_EN/PILKF0 R0 _ L 0L-0_ R K_ *0_ *0_ VSR SEL_M#/PILKF *0K_ R_PLK_LN R00 _ VSR PILK R0 R_PLK_PM VSR PILK R _ R_PLK_MINI 0U/0V_.U/0V_ VPU PILK R0 _.0U/0V_ R_PLK_IH PILK R0 _._ US_/FS SELPS0_LK R _ V V_KG 0 V 0 0 *0P_ *0P_ *0P_ *0P_ P_.P_.0U/0V_ 0U/0V_ : change for signal quality RP P_ P_ R Y /F_ U 0 XIN 0 XOUT SMLK SMT PU_STOP# PI/PIE_STOP# TEST_MOE/FS IREF RTMT--V-LFT REF0 REF/FS PULK0 PULK0# PULK PULK# OT_ OT_# M_SS/SR0 M_SS#/SR0# SR SR# SR SR# 0 R_REFSSLK R_REFSSLK# 0 <Temphar> M_IH {} SELPS_LK {,} HLK_PU {} HLK_PU# {} HLK_MH {} HLK_MH# {} OT {} OT# {} REFSSLK {} REFSSLK# {} LK_PIE_MINI {} LK_PIE_MINI# {} LK_PIE_IH {} LK_PIE_IH# {} LK_PIE_ST {} LK_PIE_ST# {} LK_MH_GPLL {} LK_MH_GPLL# {} LK_PIE_VG {} LK_PIE_VG# {} PLK_ {} PLK_LN {} PLK_PM {} PLK_MINI {} PLK_IH {} LK_US {} {,} PT_SM Q N00 0K_PR_S SMT SMT {0} HLK_PU HLK_PU# HLK_MH HLK_MH# R R R R./F_./F_./F_./F_ LK_PIE_VG LK_PIE_VG# LK_PIE_ST LK_PIE_ST# R R0 R R./F_./F_./F_./F_ V Q0 SMbus address : LK_MH_GPLL LK_MH_GPLL# OT OT# R R R R./F_./F_./F_./F_ {,} PLK_SM SMK SMK {0} N00 REFSSLK REFSSLK# LK_PIE_MINI LK_PIE_MINI# LK_PIE_IH LK_PIE_IH# R R R R R R./F_./F_./F_./F_./F_./F_ Size ocument Number Rev LK GEN PROJET : ZL Quanta omputer Inc. ate: Monday, ecember, 00 Sheet of

H# H# H# H#0 H# H# H# H# H# H#[..] H# H# H# H# HPUSLP#_GMH H# H# H# H# HXSOMP H# H# H# H# H# H# H# H# H# H# H#0 H#0 H# H# H# H# H# H# H# HXROMP HXSOMP HYSWING HYSWING HYROMP H# H# H# H# H# H# HVREF H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# HYSOMP H# H#0 H# H# H# HXROMP H# H#0 H#0 H# H# H# H# H# H# H# H# HYROMP H# H# H# H# H# H#0 H# H# HYSOMP H# H# H# H#0 H# H# H# H#0 H# HXSWING H# H# H#[0..] HXSWING HLOK# {} EFER# {} HREQ# {} HSTP# {} HIT# {} HI0# {} HI# {} RS# {} HSTP# {} HREQ0# {} HREQ#0 {} HSTN# {} PUSLP# {,} HI# {} HREQ# {} HREQ# {} RS# {} H#[0..] {} HST# {} PRI# {} PWR# {} HSTN0# {} H#[..] {} S# {} HSTP# {} RS#0 {} NR# {} SY# {} HLK_MH# {} HSTP0# {} HTRY# {} HREQ# {} HSTN# {} HST0# {} PURST# {} HI# {} HITM# {} RY# {} HLK_MH {} HSTN# {}.0V.0V.0V.0V.0V Size ocument Number Rev ate: Sheet of LVISO - HOST Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO - HOST Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO - HOST Monday, ecember, 00 O NOT INSTLL FOR OTHN- N INSTLL FOR OTHN- R /F_ R /F_ R0./F_ R0./F_.U/0V_.U/0V_ T T H0# E H# E H# F H# H H# E H# F H# E H# H# K H# F H0# J H# J H# H H# F H# K H# H H# H H# H H# K H# K H0# J H# G H# H H# J H# L H# K H# J H# P H# L H# J H0# P H# L H# U H# V H# R H# R H# P H# T H# R H# R H0# U H# R H# T H# T H# R H# T H# V H# U H# W H# U H0# V H# W H# W H# U H# U H# Y H# Y H# V H# Y H# W H0# W H# Y H# Y H# W HTRY# H# G H# H# E H# H# 0 H# F H# H0# 0 H# E0 H# G0 H# H# E H# F0 H# G H# G H# 0 H# H0# H# H# H# H# F H# G H# E H# H# H# H0# H# F HS# F HPREQ# HREQ# HREQ# HREQ# HREQ# HPRI# HNR# HLOK# HHIT# HHITM# HEFER# E HSY# HRY# F HPWR# G HRS0# HRS# HRS# HPURST# H0 HLKINN HLKINP REQ0# E HINV#0 H HINV# K HINV# T HINV# U HST0# HST# E HSTN0# G HSTN# K HSTN# R HSTP# W HSTP0# G HSTP# K HSTP# R HSTN# V HYROMP T HXSWING HVREF J HXSOMP HXROMP HERY# F HREQ0# HPUSLP# G HYSOMP L HYSWING P HOST U LVISO_PM HOST U LVISO_PM T T R 00/F_ R 00/F_ 0 G Y V T P M K H E N 0 L J F E E 0 Y W V U T R P N M L 0 K J H G F E N H 0 L F W V 0 U T R P N M L K J H 0 G F E N J 0 Y L G W V U T 0 R P N M L K J H G F 0 E P0 E0 0 0 0 Y0 0 M 00 J 0 G 0 0 0 W 0 V 0 U 0 P 0 L 0 H 0 G F E W E 0 N L J G F W G E 0 J G J F F H L H 0 J E N F F K0 V0 0 G0 F0 E0 0 0 N G W T J 0 H L U N J F G 0 L K H K N L 0 J G K J F J 0 N L J G F Y H F 0 00 Y0 0 L0 0 0 0 N 0 H 0 E 0 0 0 V 0 T 0 K H L Y P L E N 0 K G V G J E T 0 P L J P L W E N F 0 Y U P L H J 0 N L H E V T P 0 L J G E N L J G 0 Y LVS UE LVISO_PM UE LVISO_PM.U/0V_.U/0V_ R./F_ R./F_ R./F_ R./F_ R0 00/F_ R0 00/F_ R 00/F_ R 00/F_.U/0V_.U/0V_ R 0_ R 0_ R /F_ R /F_ Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL R./F_ R./F_ R 00/F_ R 00/F_

{,} {,} {,} {,} {,} {,} {,} {,} {} {} LK T VG_LU VG_GRN VG_RE VSYN HSYN LK_MH_GPLL# LK_MH_GPLL {,} LON {,} PHL_LK {,} PHL_T L_POWER_ON {,} {,} {,} {,} {,} {,} {,} {,} R R R R R R0 R TXLOUT0- TXLOUT0 TXLLKOUT TXLLKOUT- TXLOUT TXLOUT- TXLOUT TXLOUT- R0 R R R For UM LK_N T_N VG_LU_N 0_@UM VG_GRN_N 0_@UM VG_RE_N 0_@UM VSYN_N HSYN_N /F_ for sparete UM and VG display-on R0 R R R R 0_@UM 0_@UM 0_@UM R 0_@UM R 0_@UM R 0_@UM 0_@UM R *0_@UM T0 T *0_@UM *0_@UM *0_@UM.K/F_ T T T0 T T TXLLKOUT-_N TXLLKOUT_N TXLOUT0-_N TXLOUT-_N TXLOUT-_N TXLOUT0_N TXLOUT_N TXLOUT_N *0_ *0_ *0_ *0_ H H J E E E 0 0 H G REFSETJ0 T E LON_ F L_LK F L_T F LV_EN F F F 0 UF RP TXLLKOUT_N TXLLKOUT-_N *PR-00_@UM RP TXLOUT0-_N TXLOUT0_N *PR-00_@UM RP TXLOUT_N TXLOUT-_N *PR-00_@UM RP TXLOUT_N TXLOUT-_N *PR-00_@UM SVOTRL_T SVOTRL_LK GLKN GLKP TV_ TV_ TV_ TV_REFSET TV_IRTN TV_IRTN TV_IRTN LK T LUE LUE# GREEN GREEN# RE RE# VSYN HSYN REFSET LKLT_TRL LKLT_EN LTL_LK LTL_T L_LK L_T LV_EN LIG LVG LVREFH LVREFL LLKN LLKP LLKN LLKP LTN0 LTN LTN LTP0 LTP LTP LTN0 LTN LTN LTP0 LTP LTP LVISO_PM MIS TV VG LVS PI-EXPRESS GRPHIS EXP_OMPI EXP_IOMPO EXP_RXN0 EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN0 EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXP0 EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP0 EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_TXN0 EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN0 EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXP0 EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP0 EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP E0 F G0 H J0 K L0 M N0 P R0 T U0 V W0 Y 0 E F0 G H0 J K0 L M0 N P0 R T0 U V0 W E F G H J K L M N P R T U V W Y E F G H J K L M N P R T U V W R./F_ GMHEXP_RXN0 GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN0 GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXP0 GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP0 GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_TXN0 GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN0 GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXP0 GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP0 GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP VG_PIE 0 0 0 0 0 0 0 0 0 0 0 0 00.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_ 0.u apacitors place at first / of trace GMHEXP_RXN[0..] {} GMHEXP_RXP[0..] {} GMHEXP_TXN0 GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN0 GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXP0 GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP0 GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXN[0..] {} GMHEXP_TXP[0..] {} {0} {0} {0} {0} {0} {0} {0} {0} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {,0} {,0} {,0} {,0}.VSUS MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP LK_SRM0 LK_SRM T LK_SRM LK_SRM T LK_SRM0# LK_SRM# T LK_SRM# LK_SRM# T {,0} {,0} {,0} {,0} {,0} {,0} {,0} {,0} R R KE0 KE KE KE SM_S0# SM_S# SM_S# SM_S# R0 R0 M_OT0 M_OT M_OT M_OT *0./F_ *0./F_ 0./F_ 0./F_ 0.VSUS For R It's point to point, ohm trace, keep as short as possible. LK_SRM LK_SRM LK_SRM# LK_SRM# KE0 KE KE KE SM_S0# SM_S# SM_S# SM_S# M_OOMP0 M_OOMP M_ROMPN M_ROMPP SMXSLEW SMYSLEW Y Y M L E J F 0 N K E0 J F 0 P M H K N M H G F F P L M N0 K0 K F E E F F0 U MIRXN0 MIRXN MIRXN MIRXN MIRXP0 MIRXP MIRXP MIRXP MITXN0 MITXN MITXN MITXN MITXP0 MITXP MITXP MITXP SM_K0 SM_K SM_K SM_K SM_K SM_K SM_K0# SM_K# SM_K# SM_K# SM_K# SM_K# SM_KE0 SM_KE SM_KE SM_KE SM_S0# SM_S# SM_S# SM_S# SM_OOMP0 SM_OOMP SM_OT0 SM_OT SM_OT SM_OT SMROMPN SMROMPP SMVREF0 SMVREF SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT MI R MUXING FG/RSV PM LK N LVISO_PM FG[0:]=00 FOR FS FG[0:]=0 FOR FS 00 FG0 FG FG FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG FG0 RSV RSV RSV RSV RSV RSV RSV G H G F F G E J E E H H J H G G G G J 0 FG0 FG FG FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG FG0 PM_EXTTS#0 R PM_EXTTS# R0 R 0_ OT# OT REFSSLK# REFSSLK TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N R0.K_ R 0_ R 0_ R00 *K_ R0 R R0 R0 T T0 T T T T T T T T T T0 T0 T0 T T *K_ K_.0V SELPS_LK {,} SELPS_LK {,} FG Low=MIx High=MIx FG Low=R High=R FG Low=REVERSE LNE High=NORML FG FOR PU FG[:] have internal pullup resistors. FG[:] have internal pulldown resistors M_USY# EXT_TS0# EXT_TS# THRMTRIP# PWROK RSTIN# REF_LKN REF_LKP REF_SSLKN REF_SSLKP N N N N N N N N N N0 N J J H F 0 E P N P P P N R 00_ T T T00 T T T T T T *K_ K_ T T T T 0K_ 0K_ PM_MUSY# {}.V THERMTRIP# {,} IMVP_PWRG {,,} PLTRST# {,,0} OT# {} OT {} REFSSLK# {} REFSSLK {} PROJET : ZL Quanta omputer Inc. Size ocument Number Rev LVISO - MI / VG Monday, ecember, 00 ate: Sheet of

S_RVENIN# S_RVENOUT# R M R M R M0 R M R M R M R M R M R M R M R M R M R M0 R M R M R M R M R M R M R M R M0 R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M0 R M R M R M R M R M0 R M R M R M R M0 R M R M R M R M R M R M R M R M0 R M R M R M R M R M R M0 R M R M R M R M0 R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M0 R M R M R M R M R M R M R M R S# R M0 R M R M R M R M R M0 R M R M R M R M R M R M R M R QS R QS R QS R QS R QS R QS R QS R M R M R M R M R MWE# R SRS# R SS# R S0# R S# R M R M R M R M0 R M R M R M R QS0 R M0 R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS#0 R M R M R M R M R M R M R M0 R M R M0 R M R M R M R M R M0 R MWE# R SRS# R SS# R S# R S0# R S# R M0 R M R M R M R M R M R M R M R QS0 R QS R QS R QS R QS R QS R QS R QS#0 R QS# R QS# R QS# R QS# R QS# R QS# R QS# R M0 R M R M R M R M R M R M R M R M R M R M0 R M R M R M R QS R M R M R M R M R M R M R M S_RVENIN# S_RVENOUT# R S# {,0} R M[0..] {0} R MWE# {,0} R SRS# {,0} R S0# {,0} R S# {,0} R SS# {,0} R QS#[0..] {0} R M[0..] {0} R M[0..] {,0} R QS[0..] {0} R M[0..] {0} R QS#[0..] {0} R M[0..] {,0} R QS[0..] {0} R M[0..] {0} R MWE# {,0} R SRS# {,0} R SS# {,0} R S# {,0} R S0# {,0} R S# {,0} Size ocument Number Rev ate: Sheet of LVISO - RII Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO - RII Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO - RII Monday, ecember, 00 T T Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL SQ0 E SQ E SQ G SQ G SQ E SQ E SQ F SQ F0 SQ H SQ H SQ0 K SQ G0 SQ G SQ G SQ H SQ J SQ K0 SQ J0 SQ H SQ H SQ0 K SQ H0 SQ H SQ G SQ F SQ G SQ J SQ K SQ H SQ H SQ0 G SQ J SQ G0 SQ G SQ G SQ H SQ H SQ H0 SQ J SQ K SQ0 J SQ K SQ J SQ H SQ K SQ J SQ J SQ K SQ G SQ G SQ0 SQ SQ H SQ G SQ E SQ SQ SQ SQ SQ SQ0 SQ SQ SQ S_S0# J S_S# G S_S# G S_M0 F S_M K S_M K S_M K S_M J0 S_M K S_M E S_M S_QS0 F S_QS K S_QS J S_QS K S_QS M0 S_QS H S_QS F S_QS S_QS0# F S_QS# K S_QS# K S_QS# J S_QS# L0 S_QS# H S_QS# F S_QS# S_M0 H S_M K S_M H S_M J S_M K S_M J S_M K S_M H S_M J0 S_M H0 S_M0 J S_M G S_M G0 S_M G S_S# H S_RS# K S_RVENIN# F S_RVENOUT# F S_WE# H R SYSTEM MEMORY UG LVISO_PM R SYSTEM MEMORY UG LVISO_PM T T SQ0 G SQ H SQ L SQ L SQ H SQ J SQ K SQ L SQ M SQ N SQ0 P SQ M SQ M SQ M SQ L SQ M SQ N SQ P SQ N SQ P SQ0 L0 SQ M0 SQ M SQ L SQ P SQ M SQ M SQ M SQ L SQ M SQ0 N SQ P SQ M SQ L SQ L SQ P SQ P SQ P0 SQ L SQ M SQ0 N SQ N SQ N SQ P SQ P SQ M SQ L SQ M SQ K SQ K SQ0 G SQ G SQ L SQ M SQ H SQ G SQ F SQ E SQ SQ SQ0 F SQ F SQ SQ S_S0# K S_S# K S_S# L S_M0 J S_M P S_M L S_M P S_M P S_M P S_M J S_M S_QS0 K S_QS P S_QS N S_QS P S_QS M S_QS M S_QS J S_QS E S_QS0# K S_QS# P S_QS# N0 S_QS# N S_QS# N S_QS# M S_QS# H S_QS# E S_M0 L S_M P S_M P S_M M S_M N S_M M S_M L S_M P0 S_M M S_M L0 S_M0 M S_M N0 S_M M0 S_M M S_S# N S_RS# P S_RVENIN# F S_RVENOUT# F S_WE# P R SYSTEM MEMORY U LVISO_PM R SYSTEM MEMORY U LVISO_PM T T T T

V_MPLL V_HPLL VP_GMH_P VP_GMH_P VP_GMH_P VP_GMH_P V._R_P V._R_P V._R_P V._R_P V._R_P V_GPLL_ V_GPLL V._R_P V_PLL V_PLL V_PLL V_PLL VG_PIE V_RLL V_RT VGFOLLOW V_RT.0V.0V.V.VSUS VG_PIE.V.V.V.V.V.V.V.0V.0V.V.V.0V.VSUS.0V.V.V.V.V.V Size ocument Number Rev ate: Sheet of LVISO - POWER Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO - POWER Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO - POWER Monday, ecember, 00 00m 0m 0m 0m 0m 0m 0m 0m For R m GM link.v PM link 0m 0m m L LMPGSN_ L LMPGSN_ R *0_ R *0_.U/0V_.U/0V_ 0U/.V_ 0U/.V_ L UH_0 L UH_0 VTT_NTF0 W VTT_NTF V VTT_NTF U VTT_NTF T VTT_NTF R VTT_NTF P VTT_NTF N VTT_NTF M VTT_NTF L VTT_NTF W VTT_NTF0 V VTT_NTF U VTT_NTF T VTT_NTF R VTT_NTF P VTT_NTF N VTT_NTF M VTT_NTF L VSM_NTF0 VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF0 VSM_NTF VSM_NTF 0 VSM_NTF 0 VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF0 VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF0 VSM_NTF V_NTF0 W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF0 V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF0 U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF0 T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF0 R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF P V_NTF0 N V_NTF M V_NTF L V_NTF Y0 V_NTF R0 V_NTF P0 V_NTF N0 V_NTF M0 V_NTF L0 V_NTF Y V_NTF0 R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF Y V_NTF R V_NTF P V_NTF N V_NTF M V_NTF0 L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF P V_NTF N V_NTF M V_NTF L _NTF0 _NTF _NTF Y _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF _NTF0 _NTF Y _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF R _NTF 0 _NTF0 0 _NTF _NTF _NTF _NTF _NTF _NTF _NTF Y _NTF R _NTF _NTF0 _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF R _NTF P _NTF N _NTF M _NTF0 L _NTF _NTF _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF R _NTF P _NTF0 N _NTF M _NTF L _NTF _NTF _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF0 R _NTF P _NTF N _NTF M _NTF L _NTF _NTF Y _NTF _NTF Y NTF U LVISO_PM NTF U LVISO_PM L LMPGSN/0_ L LMPGSN/0_ R *0_ R *0_.U/V_.U/V_ 0 0U/.V_ 0 0U/.V_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_ 0U/.V_ 0U/.V_.U_.U_ 0.U/0V_ 0.U/0V_ 0U/0V_ 0U/0V_.U/0V_.U/0V_.0U/V_.0U/V_ 0.U/0V_ 0.U/0V_ 0U/.V_ 0U/.V_ L 0UH L 0UH V0 T V R V N V M V K V J V V V U V T V R V0 P V N V M V L V K V J V H V G V V V U V0 T V R V P V N V M V L V K V J V H V K V0 H V K V J V K V K V K V K V W0 V U0 V T0 V0 K0 V V V U V K V W V V V T V K V K VH_MPLL0 VH_MPLL V_PLL V_PLL V_HPLL V_MPLL V_RT0 F V_RT E V_RT G V_SYN H0 VTT0 K VTT J VTT K VTT W VTT V VTT U VTT T VTT R VTT P VTT N VTT0 M VTT L VTT K VTT W0 VTT V0 VTT U0 VTT T0 VTT R0 VTT P0 VTT N0 VTT0 M0 VTT K0 VTT J0 VTT Y VTT W VTT U VTT R VTT P VTT N VTT M VTT0 L VTT J VTT N VTT M VTT N VTT M VTT N VTT M VTT VTT N VTT0 M VTT N VTT M VTT N VTT M VTT N VTT M VTT VTT V VTT N VTT0 M VTT G V_TV0 F V_TV E V_TV0 V_TV V_TV0 F V_TV E V_TVG H _TVG G V_TV VQ_TV H V_LVS0 V_LVS V_LVS V_LVS VHV0 VHV VHV VSM0 M VSM H VSM P VSM VSM VSM VSM P VSM N VSM M VSM L VSM0 K VSM J VSM H VSM G VSM F VSM E VSM P VSM N VSM M VSM L VSM0 K VSM J VSM H VSM G VSM F VSM E VSM E VSM E VSM E VSM E VSM0 E0 VSM E VSM E VSM E VSM E VSM E VSM E VSM P VSM N VSM M VSM0 L VSM K VSM J VSM H VSM G VSM F VSM E VSM P VSM N VSM M VSM0 L VSM K VSM J VSM H VSM G VSM F VSM E VSM VSM VSM VSM0 0 VSM VSM P VSM M VSM E VTX_LVS0 VTX_LVS VTX_LVS V_SM0 F0 V_SM P V_SM F V_SM F VG0 E VG W VG U VG R VG N VG L VG J V_GPLL0 Y V_GPLL Y V_GPLL Y V_GG F _GG G POWER UH LVISO_PM POWER UH LVISO_PM.U/0V_.U/0V_.U/0V_.U/0V_ Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL.U/0V_.U/0V_ L LMPGSN_ L LMPGSN_.U/0V_.U/0V_.U/0V_.U/0V_.U/V_.U/V_ 0U/.V_ 0U/.V_.U/0V_.U/0V_.U/0V_.U/0V_ 0.U/0V_ 0.U/0V_ R 0_ R 0_ *H *H 0U/.V_ 0U/.V_ L 0UH L 0UH L LMPGSN_ L LMPGSN_ L *LMPGSN/0_ L *LMPGSN/0_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_.0U/V_.0U/V_.U/0V_.U/0V_ 00.U/0V_ 00.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/.V_.U/.V_ L UH_0 L UH_0 0U/.V_ 0U/.V_ 0.U/0V_ 0.U/0V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_.U/0V_.U/0V_ 0U/.V_ 0U/.V_.U/0V_.U/0V_ 0U/.V_ 0U/.V_ 0.U/.V_ 0.U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_.U/0V_.U/0V_ 0.U/0V_ 0.U/0V_ R 0./F_ R 0./F_

0.V 0.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ *0U/0V_ Layout note: Place one cap close to every pullup resistors terminated to 0.V 0.V R M[0..] {,0} 0 0 0 0.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ R M[0..] {,0} Layout note: Place one cap close to every pullup resistors terminated to 0.V {,0} R S# R M0 R S# RP _PR_S R M R M RP _PR_S R S# {,0} R S# KE0 RP {,0} M_OT {,0} KE0 _PR_S {,0} SM_S# {,0} R SS# {,0} R MWE# R M R M RP _PR_S 0.V {,0} R SRS# {,0} SM_S# {,0} M_OT {,0} SM_S# {,0} R S0# {,0} M_OT {,0} KE R SRS# SM_S# RP0 M_OT SM_S# RP R M0 R S0# RP R M M_OT RP KE R M RP _PR_S _PR_S _PR_S _PR_S _PR_S {,0} KE {,0} KE {,0} R S# M_OT SM_S# RP R SS# R MWE# RP KE R M KE R S# R M R M R M R M RP0 RP RP RP _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S 0.V 0.V R M R M R M R M RP RP _PR_S _PR_S 0.V {,0} R MWE# {,0} R SS# R MWE# R SS# R M R M RP RP _PR_S _PR_S R M R M RP0 _PR_S {,0} R S0# R M0 R S0# RP _PR_S 0.V R M R M RP _PR_S 0.V R M R M RP _PR_S {,0} R SRS# R SRS# R M RP _PR_S {,0} SM_S0# {,0} M_OT0 {,0} R S# SM_S0# M_OT0 R S# R M0 RP RP _PR_S _PR_S 0.V PROJET : ZL Quanta omputer Inc. Size ocument Number Rev R TERMINTION ate: Monday, ecember, 00 Sheet of

R M R M R QS R QS# R M R M0 R M R M R QS R M R M R M R M R QS# R M0 R QS R M R S0# R MWE# R M SM_S# R M0 R M R SS# R QS# R M SM_S# R M R QS# R M R M R M R QS0 R QS R M0 R M R M R QS# M_OT M_OT LK_SRM LK_SRM# R S# R QS# R QS R QS# R SRS# R M R M R M R QS R M R M KE R M R M KE R M R M R S# R QS R M R QS# R M R M R S# R QS0 R QS# R M R M KE0 R M R M R S# R SS# R M0 R M R QS# R M R M R M R M R M R M R QS R MWE# R M LK_SRM0 R QS# R S0# R M R M R QS R QS R M R M0 SM_S0# R M LK_SRM0# R QS R QS# R QS# R M M_OT0 R M0 R M0 R M R QS# R QS#0 R M R M R M R QS R M KE SM_S# R M R M R QS R SRS# R M M_OT R M R M R M R M R M R M R QS#0 R QS LK_SRM LK_SRM# LK_SRM# LK_SRM R M R M R M R M R M R M R M0 R M R M R M R M R M R M R M R M R M R M R M0 R M R M R M R M R M0 R M0 R M R M R M R M R M R M R M R M R M R M R M R M R M0 R M R M R M R M R M R M R M R M R M R M R M R M R M0 R M R M R M0 R M R M R M R M R M0 R M R M R M R M R M R M R M0 R M R M R M R M R M R M R M R M R M R M R M R M R M R M0 R M R M SMK SMT SMT SMK R M R M R M R M R M R M R M R M R M0 R M R M R M R M R M R M R M R M R M R M0 R M R M R S0# {,} R MWE# {,} R QS#[0..] {} R M[0..] {} R M[0..] {,} R M[0..] {} R QS[0..] {} SM_S# {,} R QS#[0..] {} R M[0..] {} SM_S0# {,} R SS# {,} R M[0..] {,} R S# {,} R M[0..] {} M_OT {,} R SRS# {,} M_OT0 {,} LK_SRM0 {} LK_SRM0# {} R QS[0..] {} R S0# {,} R MWE# {,} SM_S# {,} R SS# {,} SM_S# {,} R S# {,} M_OT {,} M_OT {,} LK_SRM {} LK_SRM# {} R SRS# {,} KE {,} KE {,} KE {,} KE0 {,} LK_SRM# {} LK_SRM {} R S# {,} LK_SRM# {} LK_SRM {} R S# {,} SMT {} SMK {} 0.VSUS V V.VSUS.VSUS.VSUS V V V.VSUS.VSUS.VSUS.VSUS.VSUS 0.VSUS 0.VSUS 0.VSUS Size ocument Number Rev ate: Sheet of R SO-IMM ( 00P ) <OrgName> <Orgddr> <Orgddr> <Orgddr> <Orgddr> 0 Monday, ecember, 00 Size ocument Number Rev ate: Sheet of R SO-IMM ( 00P ) <OrgName> <Orgddr> <Orgddr> <Orgddr> <Orgddr> 0 Monday, ecember, 00 Size ocument Number Rev ate: Sheet of R SO-IMM ( 00P ) <OrgName> <Orgddr> <Orgddr> <Orgddr> <Orgddr> 0 Monday, ecember, 00 LOK 0,, LOK,, SMbus address 0 SMbus address KE, KE 0, R 0K_ R 0K_ R 0K_ R 0K_.U/0V_.U/0V_.U/.V_.U/.V_ R 0K_ R 0K_ 0.U/0V_ 0.U/0V_ VREF Q0 Q QS#0 QS0 Q Q Q Q QS# QS Q0 Q 0 Q Q QS# QS Q Q Q Q M N Q Q KE0 V N _ V V 0 V0 0 0/P 0 0 0 WE# 0 V S# S# V OT Q Q QS# QS Q Q Q0 Q Q Q M0 0 Q Q Q 0 Q M K0 0 K0# Q Q 0 0 Q0 Q N 0 M Q Q 0 Q Q QS# QS 0 0 Q0 Q KE 0 V V 0 V 00 0 0 V 0 0 RS# 0 S0# 0 V OT0 V N 0 Q Q M 0 Q Q Q 0 Q M Q Q 0 Q Q NTEST 0 QS# QS Q0 Q Q Q M Q Q S SL V(SP) QS# QS 0 Q Q Q Q 0 K K# M 0 Q Q Q0 0 Q QS# QS 0 Q Q S0 S 00 P00 R SRM SO-IMM (00P) N P00_R_.0MM_ST P00 R SRM SO-IMM (00P) N P00_R_.0MM_ST.U/0V_.U/0V_.U/.V_.U/.V_.U/.V_.U/.V_ VREF Q0 Q QS#0 QS0 Q Q Q Q QS# QS Q0 Q 0 Q Q QS# QS Q Q Q Q M N Q Q KE0 V N _ V V 0 V0 0 0/P 0 0 0 WE# 0 V S# S# V OT Q Q QS# QS Q Q Q0 Q Q Q M0 0 Q Q Q 0 Q M K0 0 K0# Q Q 0 0 Q0 Q N 0 M Q Q 0 Q Q QS# QS 0 0 Q0 Q KE 0 V V 0 V 00 0 0 V 0 0 RS# 0 S0# 0 V OT0 V N 0 Q Q M 0 Q Q Q 0 Q M Q Q 0 Q Q NTEST 0 QS# QS Q0 Q Q Q M Q Q S SL V(SP) QS# QS 0 Q Q Q Q 0 K K# M 0 Q Q Q0 0 Q QS# QS 0 Q Q S0 S 00 P00 R SRM SO-IMM (00P) N0 P00_R_.0MM_ST P00 R SRM SO-IMM (00P) N0 P00_R_.0MM_ST.U/.V_.U/.V_.U/.V_.U/.V_ 0.U/.V_ 0.U/.V_ 0.U/0V_ 0.U/0V_.U/.V_.U/.V_.U/0V_.U/0V_.U/.V_.U/.V_.U/0V_.U/0V_.U/0V_.U/0V_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ R 0_ R 0_.U/0V_.U/0V_ R 0_ R 0_.U/0V_.U/0V_.U/.V_.U/.V_ Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL.U/0V_.U/0V_.U/.V_.U/.V_.U/.V_.U/.V_ R 0K_ R 0K_.U/.V_.U/.V_.U/.V_.U/.V_.U/0V_.U/0V_

VRT P_ LK_KX R *0K_ INTVRMEN R 0_ VPU R00 VRT R 0K/F_ 0.U/0V_ Y.KHZ VRT P_ R {} NMI JP {} 0M# {} FERR# {} IGNNE# *SHORT_ P {} INTR {} PUINIT# {} RIN# {} GTE0 LK_KX R 0M_ RT_RST# M_ SM_INTRUER# INTVRMEN Y RTX Y RTX U RTRST# INTRUER# INTVRMEN F NMI F R0 R_FERR# 0M# F _ FERR# G IGNNE# G INTR F RIN# INIT# GTE0 RIN# F 0GTE RT LP PU L0 L/F L/F L/F LRQ0# LRQ#/GPI LFRME# PUPWRG/GPO INIT_V# THRMTRIP# SMI# STPLK# PUSLP# PSLP#/TP[] PRSLP#/TP[] P N N N N P P LP_RQ0# LP_RQ# R 0_ G E T E THERMTRIP#_IH G E E R_PUSLP# E R0 0_ L0/FWH0 {} L/FWH {} L/FWH {} L/FWH {}.0V LFRME#/FWH {} PUPWRG {} R _ SMI# {} STPLK# {} PSLP# {} PRSLP# {} R /F_ R *0_ V LP_RQ0# R 0K_ LP_RQ# R0 0K_ epop for othan. Populate for Yonah THERMTRIP# {,} PUSLP# {,} INSTLL FOR OTHN- N NOT INSTLL FOR OTHN- R_VRT R00.U/.V_ R0 K_ Q R0 VRT RT_N0 K_ MMT0 N TON {} PLK_IH RT RT_N0 R *_ *P_ V V R0 R VPU R0 K_ R0 0K_ V V.0V IRQ PHRY 0K_ RIN# 0K_ GTE0 {,,} [0..] {,,} PME# {,,,} PIRST# {,,0} PLTRST# {,,,} LKRUN# {0} P[0..] 0K_.K_ R R R0 _ V FERR# P[0..] {0} PS# {0} PS# {0} P0 {0} P {0} P {0} PIOR# {0} PIOW# {0} PHRY {0} IRQ {0} PREQ {0} PK# 0 0 0 0 PME# INTERNL 0K PULLUP R R 0_ 0K_ P0 P P P P P P P P P P0 P P P P P E E F F E F E H J K K L G H H H M K K L K P G R R F F F E E F E G PS# PS# E P0 P P PIOR# E PIOW# PHRY F IRQ PREQ PK# 0 0 0 0 PME# PILK PIRST# PLTRST# LKRUN#/GPIO 0 0 S# S# 0 IOR# IOW# IORY IEIRQ REQ K# IH-M PI IE ST -/ ZLI /E0# /E# /E# /E# FRME# IRY# TRY# EVSEL# STOP# PR SERR# PERR# PLOK# REQ0# REQ# REQ# REQ# REQ#/GPI0 REQ#/GPI REQ#/GPI0 GNT0# GNT# GNT# GNT# GNT#/GPO GNT#/GPO GNT#/GPO PIRQ# PIRQ# PIRQ# PIRQ# PIRQE#/GPI PIRQF#/GPI PIRQG#/GPI PIRQH#/GPI STLE# ST0_RXN ST0_RXP ST0_TXN ST0_TXP ST_RXN ST_RXP ST_TXN ST_TXP ST_LKN ST_LKP STRIS# STRIS Z_IT_LK Z_SYN Z_RST# Z_SIN0 Z_SIN Z_SIN Z_SO epop for othan. Populate for Yonah J E0# {,,} H E# {,,} G E# {,,} G E# {,,} J J J E G E PLOK# L REQ0# M REQ# REQ# REQ# F REQ# E RYI RYI0 F E F N L M L M E G F F G G F GNT0# GNT# GNT# RYON# M_I0 M_I M_I ST_TXN0_ ST_TXP0_ 0 _ITLK_S _SYN_S 0 _RESET#_S F F0 0 FRME# {,,} IRY# {,,} TRY# {,,} EVSEL# {,,} STOP# {,,} PR {,,} SERR# {,,} PERR# {,,} T REQ0# {} REQ# {} REQ# {} T T GNT0# {} GNT# {} GNT# {} T T T0 T _SIN0 {} _SIN {} T INT# {} INT# {} INT# {} INT# {} M_I0 {} M_I {} M_I {} for IE interrupt R T T0 STLE# {} R0 ST_RXN0 {0} ST_RXP0 {0} LK_PIE_ST# {} LK_PIE_ST {}./F_ R _ R _ R _ R _ R _ R _ V V 0K_ V REQ# RYI0 RYI REQ# PERR# SERR# FRME# REQ0# INT# INT# INT# INT# MONITOR_PLUG# {} 00PF_@ST 0 00PF_@ST Place within 00mils of IH ball _SYN_M {} _SYN {} _RESET#_M {} _RESET# {} _SOUT_M {} _SOUT {} PI Pullups RP 0.K_0PR RP 0.K_0PR RP 0K_PR ST_TXN0 {0} ST_TXP0 {0} V EVSEL# IRY# REQ# PLOK# V REQ# STOP# TRY# V _ITLK_S R _ R _ *P_ *P ITLK_M {} _ITLK {} Size ocument Number Rev IH-M PU PI IE PROJET : ZL Quanta omputer Inc. ate: Monday, ecember, 00 Sheet of

V_S V_S V_S V_S V LK_US R R TLOW# RING# SI# KSMI# PR_STS SMLINK0 SMLINK.K_ THRM# PWRTN# HS INTERNL PULLUP R0 R0 *0_ R00 R *0P_ RP 0K_PR R0 R 0K_ 0K_ RP PLK_SM SM_LINK_LERT# PT_SM LI# 0K_PR 0K_ 0K_ 0K_ 0K_ IH_PWROK RSMRST# {} M_IH T {} LK_PIE_IH# {} LK_PIE_IH {} PIE_RXN0 {} PIE_RXP0 {} PIE_TXN0 {} PIE_TXP0 {} MI_RXN0 {} MI_RXP0 {} MI_TXN0 {} MI_TXP0 {} MI_RXN {} MI_RXP {} MI_TXN {} MI_TXP {,} PLK_SM {,} PT_SM {,} LI# {} IH_PWROK {} PRSLPVR {} NSWON# {} RSMRST# {,,} IMVP_PWRG {} PM_MUSY# {} LK_US {} PSPK {} KSMI# {} PR_STS {} SI# {} EMIL_LE# {0} RST_H# T T {} USP0 {} USP0- {} USP {} USP- T T T T0 : for MINI PIE detect fail R0 *_ 0 *P_ *.U/0V_ *.U/0V_ T LK_US T T T T0 LI# LUS# KSMI# PR_STS SI# O0# O# O# O# HSON0 HSOP0 HSIN0 HSIP0 E T T R R V V U U H H G G K K J J Y W W RING# T THRM# 0 IH_PWROK PRSLPVR E0 TLOW# V U RSMRST# Y IMVP_PWRG F W V E0 F E R M R 0 V U USP0P USP0N O0# USPP USPN O# USPP USPN O#/GPI USPP USPN O#/GPI LK MI0_RXN MI0_RXP MI0_TXN MI0_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_LKN MI_LKP HSIN0 HSIP0 HSON0 HSOP0 HSIN HSIP HSON HSOP SMLK SMT SMLERT#/GPI RI# THRM# PWROK PRSLPVR/TP TLOW#/TP0 PWRTN# RSMRST# VRMPWRG M_USY#/GPIO SUS_STT#/LPP# SUSLK LK SPKR GPI GPI GPI GPI GPO GPO GPO GPIO US MI PI-EXPRESS SM&SMI PM MIS&GPIO USPP USPN O# USPP USPN O# USPP USPN O#/GPI0 USPP USPN O#/GPI USRIS USRIS# MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_ZOMP MI_IROMP HSIN HSIP HSON HSOP HSIN HSIP HSON HSOP SMLINK0 SMLINK LINKLERET# SLP_S# SLP_S# SLP_S# LN_RST# SYS_RESET# WKE# MH_SYN# STP_PI#/GPO STP_PU#/GPO0 SERIRQ GPIO ST0GP/GPIO GPIO GPIO STGP/GPIO STGP/GPIO0 STGP/GPIO GPIO GPIO 0 0 Y Y W W F F M M L L P P N N W U Y T T T V U U G 0 P F R T E F G O# O# O# O# USRIS MIOMP SMLINK0 SMLINK SM_LINK_LERT# RSMRST# PIE_WKE# MH_SYN# SERIRQ T T T T T T T T F0 MPIT# M_I T T USP {} USP- {} USP {} USP- {} USP {} USP- {} R0 R MI_RXN {} MI_RXP {} MI_TXN {} MI_TXP {} MI_RXN {} MI_RXP {} MI_TXN {} MI_TXP {} SUS# {} SUS# {} T R# {} STP_PI# {} STP_PU# {,} SERIRQ {,,} T T T T M/ US M/ US M/ US PIE R.V.V V_S Place within 00mils of IH-./F_./F_ R 00_ O# O0# O# O# Place within 00mils of IH- SERIRQ MH_SYN# LUS# PIE_WKE# RP 0 0K_0PR 0K_PR RP R K_ O# O# O# O# V V_S V_S R *0K_ R R *0K_ R R *0K_ R V R0 *0K_ M_I0 M_I M_I M_I R M_I0 {} M_I {} M_I {} T T T T T0 F F G EE_S EE_SHLK EE_OUT EE_IN RSV RSV RSV RSV RSV IH-M LN RESERVE LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_LK LN_RSTSYN RSV RSV RSV RSV E E E F F G U RSV=TP T T T T R *_ needs to be pulled down if programmed as ST *0K_ *0K_ *0K_ *0K_ PRSLPVR R 00K_ PROJET : ZL Quanta omputer Inc. PULLLOW Size ocument Number Rev IH-M US MI LP ate: Monday, ecember, 00 Sheet of

VREF_SUS _V_PIE VMIPLL VREF_SUS VREF VREF VMIPLL.V.V_S.V VRT V.V.V.V VRT V V V V_S V_S.V V V_S.V.0V.V V V_S.V.V_S.V V_S V_S.V_S Size ocument Number Rev ate: Sheet of IH-M POWER Monday, ecember, 00 Size ocument Number Rev ate: Sheet of IH-M POWER Monday, ecember, 00 Size ocument Number Rev ate: Sheet of IH-M POWER Monday, ecember, 00 _V_PI _V_IH. m m 0m 0m m m m m m 0m u 0.U/0V_ 0.U/0V_ H H 00.U/0V_ 00.U/0V_.U/0V_.U/0V_ R0 _ R0 _ U/0V_ U/0V_.U/0V_.U/0V_ RV RV.U/0V_.U/0V_ 0U/.V_ 0U/.V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.0U/V_.0U/V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ 0U/.V_ 0U/.V_.U/0V_.U/0V_.U/0V_.U/0V_ V V V V V V V V F V F V 0 F V G V G V G V G V H V H V J V J V K V 0 K V L V L V M V M V N V N V N V N V N V 0 P V P V P V P V R V R V T V T V U V U V 0 V V V V W V W V Y V Y V V V V V 0 V V E V E V F V G V V V V V 0 V V E V E V F V G VMIPLL V E VSTPLL E V G0 VLN_/VSUS VLN_/VSUS F VLN_/VSUS G VLN_/VSUS G VSUS VSUS U VSUS V VSUS V VSUS W VSUS Y VSUS VSUS VSUS VSUS 0 F VSUS G VSUS G V V 0 0 V V L V L V L V L V L V M V M V P V 0 P V T V T V U V U V U V U V U V F V V V V V V V G V G V 0 G V 0 V V V E V H V H V J V L V L V 0 M V P VSUS R VSUS U VSUS G V V V 0 V V E0 V E V E V E V E V F0 V G0 V G V P V VREF VREF VREF_SUS F VUSPLL VSUS 0 VRT VLN_/VSUS G0 VLN_/VSUS G V_PU_IO V_PU_IO V_PU_IO G VSUS VSUS VSUS E VSUS F VSUS F VSUS G VSUS G PIE ST ORE IE PI US ORE PE/IE REF US U IH-M PIE ST ORE IE PI US ORE PE/IE REF US U IH-M Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL.U/0V_.U/0V_ R 0_ R 0_.U/0V_.U/0V_ U/0V_ 00 U/0V_ 00 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 E0 0 E 0 E 0 E 00 E 0 E 0 E 0 E 0 F0 0 F 0 F 0 F 0 F 00 G 0 F 0 0 G 0 G 0 G 0 G0 0 G 0 G 0 G 0 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 E 0 E 00 E 0 E 0 E 0 F 0 F 0 F 0 F 0 G 0 G 0 G 00 G 0 G 0 H 0 H 0 H 0 J 0 J 0 J 0 J 0 K 00 K 0 K 0 K 0 K 0 L 0 L 0 L 0 L 0 L 0 M 0 M M M M M M M M N N 0 N N N N N N N P P P 0 P P P R R R R R R R 0 R R R R T T T T T T 0 T T T T U U U U U V 0 V V V W W W W W Y Y 0 Y Y E U IH-M U IH-M RV RV.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ L UH_0 L UH_0 0.U/0V_ 0.U/0V_.U/0V_.U/0V_ 0.U/0V_ 0.U/0V_.0U/V_.0U/V_.0U/V_.0U/V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ L LMP00SPG_0 L LMP00SPG_0.U/0V_.U/0V_.U/0V_.U/0V_ U/0V_ U/0V_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_

TI MT (X ) GMHEXP_TXP0 GMHEXP_TXN0 GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP0 GMHEXP_TXN0 GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_RXP0 GMHEXP_RXN0 GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP0 GMHEXP_RXN0 GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN 0.u apacitors place at last / of trace 0 0.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG.U_@VG V_GMHEXP_RXP0 V_GMHEXP_RXN0 V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP0 V_GMHEXP_RXN0 V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN {} {} {} {} E Y W V V U T R R P N M M L K J J H G F F E W V V U U T T R R P P N N M M L L K K J J H H G G F F E E GMHEXP_TXP[0..] GMHEXP_TXN[0..] GMHEXP_RXP[0..] GMHEXP_RXN[0..] U PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PI Express Part of GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_PWRNTL GPIO_MEMSSIN VO / EXT TMS / GPIO N_VOVMOE VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ VPNTL_0 VPNTL_ VPNTL_ VPNTL_ VREFG W V Y W Y V Y V W Y W V V U V U U E F E F E E E E W G_GPIO[..0] G_GPIO[..0] {} G_GPIO0 G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO0 G_GPIO G_GPIO G_GPIO G_GPIO T VG_PWR_SW VG_PWR_SW {} GPIO_MEMSSIN R 0K_@VG PHL_T PHL_T {,} MIO[..0] {} PHL_LK PHL_LK {,} MIO0 MIO MIO MIO R0 _@VG V L.V R0.U_@VG _@VG L.V U L LMPGSN_@VG LPV.V LPV U_@VG LP LMPGSN_@VG LVR_ LVR LVR LMPGSN_@VG LVR_ LVR LVR U_@VG U_@VG U_@VG U_@VG LR_ LR_ LR_ LR_ Part of RP PR-00_@VG TXLLKOUT_M TXLLKOUT {,} TXLLKOUT-_M TXLLKOUT- {,} RP PR-00_@VG TXLOUT_M TXLOUT {,} TXLOUT-_M TXLOUT- {,} RP PR-00_@VG TXLOUT_M TXLOUT {,} TXLOUT-_M TXLOUT- {,} RP PR-00_@VG TXLOUT0_M TXLOUT0 {,} TXLOUT0-_M TXLOUT0- {,} TXLK_UP TXLK_UN TXOUT_UP TXOUT_UN T T TXOUT_UP TXOUT_UN TXOUT_UP E TXOUT_UN E TXOUT_U0P E TXOUT_U0N E TXLLKOUT_M TXLK_LP TXLLKOUT-_M TXLK_LN TXOUT_LP F TXOUT_LN F T T TXLOUT_M TXOUT_LP TXLOUT-_M TXOUT_LN TXLOUT_M TXOUT_LP E TXLOUT-_M TXOUT_LN E TXLOUT0_M TXOUT_L0P TXLOUT0-_M TXOUT_L0N {} {} LK_PIE_VG LK_PIE_VG# {,,0} PLTRST# R0 P_@VG Y PLTRST# MHZ@VG XTLIN R XTLOUT *M_@VG.V R R P_@VG 0_@VG V R R0 R0 R R0 R R R R PEX_RST *_@VG *_@VG _@VG K_@VG.K_@VG 0K_@VG _@VG XTL_IN XTL_OUT K_@VG K_@VG K_@VG T *0K_@VG Y Y0 V W W0 Y E F F E0 F0 F F E E R *0K_@VG PIE_REFLKP PIE_REFLKN PIE_LRP PIE_LRN PIE_LI PIE_TEST PWRG_MSK PWRG RSET _R_PR Y_G OMP P HSYN VSYN LK T XTLIN XTLOUT TESTEN TEST_YLK TEST_MLK PLLTEST STEREOSYN LK THERM TMS SS SSOUT SSIN TX0M TX0P TXM TXP TXM TXP TXM TXP LK T HP R G HSYN VSYN RSET T LK GPIO UXWIN PLUS MINUS 0 E F E E0 E F F F E 0 F F E E E F 0 T T T T T T0 T T T T T T T VG_RE VG_GRN VG_LU HSYN VSYN R _@VG R T LK THERM_VG THERM_VG.K_@VG R R R V 0/F_@VG 0/F_@VG 0/F_@VG VG_RE {,} VG_GRN {,} VG_LU {,} HSYN {,} VSYN {,} T {,} LK {,} VG_RE VG_GRN VG_LU Need Tune R,G, resistance R R.K_@VG.K_@VG V G _IUMP m(connect ) MOILE FUNTION PQKFG_@VG IGON LON L_POWER_ON LON_VG : for no back light issue R 0_ R K_@VG R K_@VG L_POWER_ON {,} LON {,} PQKFG_@VG MEMORY LOK SPRE SPETRUM Thermal Sensor for Graphic SLVE RESS: MIL V V V L LMPGSN_@VG V_THM 0 R.K_@VG R *0K_@VG SRS R0 0K_@VG GPIO_MEMSSIN R XTLIN SRS _@VG SSLK 0P_@VG U XIN SRS SSLK XOUT V P REF Y@VG XTLOUT PLLV MK_P MK_M R.U_@VG *0K_@VG L LMPGSN_@VG U/0V_@VG V THERM_VG 0 mil trace / 0 mil space THERM_VG.U_@VG 00P_@VG U V /LERT XN S XP SLK /THERM G- P@VG VG_THERML_S VG_THERML_SLK VG_THERM# VG_THERM# {} SRS= OWN -.% 0 OWN -.% M OWN -0.% MK_M R 0_@VG R 0P_@VG _@VG R R./F_@VG 0_@VG XTL_IN VG_THERML_S VG_THERML_SLK V Q N00@VG N00@VG MT MLK MT {,,} MLK {,,} PROJET : ZL Quanta omputer Inc. V Q Size ocument Number Rev MT (PIE//) ate: Monday, ecember, 00 Sheet of

{} VM_Q[..0] VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q F E0 E E F E E F F F E E F0 E0 F E 0 0 F G H H K K L L F G H G K L J K M M N N R U R T M M N N R R T T U Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Part of INTERFE MEMORY M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ QMb_0 QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ QS_0 QS_ QS_ QS_ QS_ QS_ QS_ QS_ RSb Sb WEb Sb_0 Sb_ KE LK0 LK0b LK LKb MVREF MVREFS ROMSb N_MEMVMOE_0 N_MEMVMOE_ 0 E 0 E G F E F F H F F J J P P E E J H P P E F Y VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS T VM_LK0 VM_LK0# VM_LK VM_LK# MVREF MVREFS VM_RS# VM_S# VM_WE# VM_S0# VM_KE R 00_@VG T R MEMVMOE_0 MEMVMOE_ VM_M0 {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M0 {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M[..0] {} VM_RQS[..0] {} VM_RS# {} VM_S# {} VM_WE# {} VM_S0# {} VM_KE {} VM_LK0 {} VM_LK0# {} VM_LK {} VM_LK# {} 00_@VG U_@VG.V R R *.K_@VG.K_@VG VR MEMVMOE_0 MEMVMOE_.V.V.V VM_KE Place close to GPU R 00_@VG R.V V_T V_T R 00_@VG U_@VG 0K_@VG.V V_T V_T MEMTEST E PQKFG_@VG R00 0_@VG R *.K_@VG R.K_@VG PROJET : ZL Quanta omputer Inc. Size ocument Number Rev MT (MEMORY /) ate: Monday, ecember, 00 Sheet of

MPV VI V.V_V PV PIE_PV_ N_VQ TPV TXVR.V.V V.V.V.V.V.V.V.V.V NVV V.V.V.V NVV NVV V.V.V Size ocument Number Rev ate: Sheet of MT (POWER) Monday, ecember, 00 Size ocument Number Rev ate: Sheet of MT (POWER) Monday, ecember, 00 Size ocument Number Rev ate: Sheet of MT (POWER) Monday, ecember, 00 PLE NER LLS IOE SUPPLIES POWER TO V RIL WHILE V REGULTOR STLIZES URING POWER ON U_@VG U_@VG U_@VG U_@VG 0U/0V_@VG 0U/0V_@VG.0U_@VG.0U_@VG.U_@VG 0.U_@VG 0 0U/0V_@VG 0U/0V_@VG 00P_@VG 00P_@VG U_@VG U_@VG U_@VG U_@VG.U/0V_@VG.U/0V_@VG U_@VG 00 U_@VG 00.0U/V_@VG.0U/V_@VG U_@VG U_@VG U/V_@VG U/V_@VG U_@VG U_@VG U_@VG U_@VG U/V_@VG U/V_@VG L LMPGSN_@VG L LMPGSN_@VG U_@VG U_@VG.0U_@VG.0U_@VG.U/0V_@VG.U/0V_@VG VI_ L VI_ N VI_ P VI_ T V_ L V_ L V_ L V_ M V_ M V_ M V_ M V_ N V_ N V_0 N V_ P V_ P V_ P V_ R V_ R V_ R V_ R V_ T V_ T V_0 T V_ W V_ W V_ W V_ Y V_ Y ENTER RRY Part of UF PQKFG_@VG ENTER RRY Part of UF PQKFG_@VG U_@VG U_@VG U_@VG U_@VG.U/0V_@VG.U/0V_@VG U/V_@VG U/V_@VG U/V_@VG U/V_@VG U_@VG U_@VG U_@VG U_@VG.U_@VG 0.U_@VG 0 U_@VG U_@VG L LMPGSN_@VG L LMPGSN_@VG U_@VG 0 U_@VG 0 0 0U/0V_@VG 0 0U/0V_@VG L0 LMPGSN_@VG L0 LMPGSN_@VG U_@VG U_@VG L *LMPGSN_@VG L *LMPGSN_@VG 00P_@VG 00P_@VG L LMPGSN_@VG L LMPGSN_@VG U_@VG U_@VG TPV TP TXVR_ TXVR_ 0 TXR_ 0 TXR_ TXR_ 0 V_ V_ N_VQ V N_ I Q 0 VRH L MPV MP PV P E VR_ Y VR_ VR_ VR_ PIE_PV PIE_PV PIE_PV VI Q Y I 0 N N_ VI VR_ W VR_ Y VR_ Y VR_ W VR_ W VR_ W VR_ V V_ K V_ T V_ U V_ W V_ H V_ H PIE_V PIE_V PIE_V V_ H V_ P PIE_V E PIE_VR N0 PIE_VR P0 PIE_VR T0 PIE_VR U0 PIE_VR K0 PIE_VR J0 PIE_VR L PIE_VR L0 PIE_VR M PIE_VR 0 N PIE_VR P PIE_VR K PIE_VR J PIE_VR R PIE_PV VR_ VR_ VR_ VR_ VR_ VR_ T VR_ VR_ VR_ VR_0 VR_ VR_ VR_ VR_ VR_ VR_ E VR_ H VR_ F0 VR_ E VR_0 G VR_ G VR_ G VR_ H VR_ J VR_ VR_ H VR_ H VR_ H VR_ H VR_0 G VR_ L VR_ J VR_ L VR_ L VR_ N VR_ R VR_ R VR_ R VR_0 N RH J VR_ G Part of I/O POWER U PQKFG_@VG Part of I/O POWER U PQKFG_@VG Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL U_@VG U_@VG L LMPGSN_@VG L LMPGSN_@VG L LMPGSN_@VG L LMPGSN_@VG U_@VG U_@VG U/V_@VG U/V_@VG.0U/V_@VG.0U/V_@VG U_@VG U_@VG 00P_@VG 00P_@VG 0 0U/0V_@VG 0 0U/0V_@VG U_@VG U_@VG PIE H0 PIE G PIE PIE PIE PIE G PIE PIE W PIE PIE 0 H PIE F PIE L PIE J PIE Y PIE PIE M PIE H PIE PIE L PIE 0 J PIE K PIE PIE K PIE PIE G PIE E PIE M0 PIE P PIE N PIE 0 M PIE P PIE T PIE F PIE N PIE R0 PIE R PIE R PIE T PIE PIE 0 K PIE U PIE V0 PIE U PIE V PIE V PIE W PIE Y PIE N PIE T PIE 0 PIE W PIE PIE W PIE H0 0 _ G _ L _0 G E 0 T _ F _ F G0 _ G H H _0 H _ H _ J _ 0 _ K _ L _ L _ M _ M _0 M _ M _ M _ N _ N _ P _ P _ P _ P _ P _0 R _ R _ T _ T _ T _ U _ U _ U _ W _ W0 _0 W _ W _ Y _ Y _ Y _ E _ F 0 0 _ M _ R _ F _ F _ G ORE Part of UE ORE Part of UE U_@VG U_@VG.U_@VG 0.U_@VG 0 U/V_@VG U/V_@VG U/V_@VG U/V_@VG *U/V_@VG *U/V_@VG RV@VG RV@VG 0U/0V_@VG 0U/0V_@VG L LMPGSN_@VG L LMPGSN_@VG.U_@VG 0.U_@VG 0 U_@VG 0 U_@VG 0 U/V_@VG 0 U/V_@VG 0.0U_@VG.0U_@VG 0U/0V_@VG 0U/0V_@VG U_@VG U_@VG L0 LMPGSN_@VG L0 LMPGSN_@VG U/V_@VG U/V_@VG.U_@VG.U_@VG.U/0V_@VG.U/0V_@VG 0U/0V_@VG 0U/0V_@VG U_@VG 0 U_@VG 0 U_@VG U_@VG U_@VG U_@VG U/V_@VG U/V_@VG U_@VG U_@VG L LMPGSN_@VG L LMPGSN_@VG.U/0V_@VG.U/0V_@VG U_@VG U_@VG.U_@VG.U_@VG RV@VG RV@VG 0U/0V_@VG 0U/0V_@VG.U_@VG.U_@VG U/V_@VG U/V_@VG U_@VG U_@VG 0 0U/0V_@VG 0 0U/0V_@VG U_@VG U_@VG 00P_@VG 00P_@VG.U/0V_@VG.U/0V_@VG *00P_@VG *00P_@VG.U_@VG.U_@VG

V STRPS PIN ESRIPTION SI EFULT R R *0K_@VG *0K_@VG G_GPIO0 G_GPIO R R 0K_@VG *0K_@VG G_GPIO[..0] G_GPIO[..0] {} TX_PWRS_EN G_GPIO0 FULL SWING R *0K_@VG R *0K_@VG R *0K_@VG R0 *K_@VG G_GPIO G_GPIO G_GPIO G_GPIO R *K_@VG G_GPIO R *K_@VG R *K_@VG R0 *K_@VG R *0K_@VG R *0K_@VG R0 *0K_@VG R *0K_@VG R *0K_@VG G_GPIO R *K_@VG G_GPIO R *K_@VG G_GPIO R *0K_@VG G_GPIO0 G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO G_GPIO0 G_GPIO G_GPIO G_GPIO TX_EEMPH_EN EUG_ESS G_GPIO G_GPIO TRNSMITTER E-EMPHSIS ENLE - TX E-EMPHSIS ISLE FOR MOILE Strap to set the debug muxes to bring out EUG signals even if registers are inaccessible. 0 0 R R *0K_@VG *0K_@VG G_GPIO0 G_GPIO R R *0K_@VG *0K_@VG FORE OMPLINE G_GPIO Force chip to get to compliance state queckly for tester pruposes 0 R *0K_@VG G_GPIO R *0K_@VG R *0K_@VG G_GPIO R *0K_@VG ROMIFG(:0) G_GPIO(,,,) M 0000 M 000 M 000 MIO[..0] {} Recerved 00 V R0 *0K_@VG MIO0 R0 0K_@VG RM_FG0 MIO0 R 0K_@VG MIO R *0K_@VG RM_FG MIO R0 0K_@VG MIO R0 *0K_@VG RM_FG MIO R0 0K_@VG MIO R0 *0K_@VG RM_FG MIO MT VRM onfiguration Table RM_FG[:0] ESRIPTION 0000 R, Mx, pcs ( M ) 000 000 R, Mx, pcs ( M ) R,Mx, pcs ( M ) 00 R,Mx, pcs ( M ) others MULTIFUN(:0) LT(:) Multi-function device select 00 - single function device. 0 - two function device. No GP in either function 0 - two function device. GP only in function 0 - two function device. GP in both functions If USFG pin based straps are set to PI, then GP will not be enabled in any function. 00 VIP_EVIE LT(0) Indicates if any slave VIP host devices drove this low during reset. 0 - Slave VIP host port devices present - No slave VIP host port devices reporting presence during reset 0 WNGR LT() 0 - evice remain a workstation grade part. 0 - Part is downgraded to a Normal part (internal pull-down) PROJET : ZL Quanta omputer Inc. Size ocument Number Rev MT (STRP/MIS) ate: Monday, ecember, 00 Sheet of

VM_M VM_M0 VM_LK0# VM_LK0 VM_S0# VM_WE# VM_RS# VM_KE VM_LK VM_LK# VM_S# VM_LK# VM_M VM_LK VM_M VM_LK0 VM_LK0# VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M0 VMREF0 VMREF VL VL VL VMREF VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_S# VM_M0 VM_S0# VM_M VM_M VM_M VM_M VM_M VM_KE VM_M0 VM_M VM_M VM_RS# VM_WE# VM_M VM_M VM_M VM_S0# VM_WE# VM_M VM_M VM_S# VM_M VM_RS# VM_M0 VM_KE VM_M0 VM_M VM_M VM_M VM_M VM_KE VM_M VM_M0 VM_S0# VM_M VM_RS# VM_M VM_M VM_M VM_WE# VM_S# VM_M0 VL VMREF VM_OT VM_OT VM_OT VM_OT VM_Q VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_RQS VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS0 VM_WQS VM_WQS VM_WQS VREF_0 VREF_0 VREF_0 VREF_ VREF_ VREF_ VM_WQS VM_WQS VM_WQS VM_WQS VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_RQS VM_RQS VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q0 VM_M VM_M VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_LK VM_LK# VM_LK0# VM_LK0 VM_OT VM_LK0 {} VM_LK0# {} VM_LK# {} VM_LK {} VM_S0# {} VM_RS# {} VM_KE {} VM_WE# {} VM_S# {} VM_M {} VM_M {} VM_M0 {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M {} VM_M0 {} VM_Q[..0] {} VM_RQS[..0] {} VM_M[..0] {} VM_M {} VM_M {} VM_M {} VG_PWR_SW {}.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V Size ocument Number Rev ate: Sheet of VRM (GR) Monday, ecember, 00 Size ocument Number Rev ate: Sheet of VRM (GR) Monday, ecember, 00 Size ocument Number Rev ate: Sheet of VRM (GR) Monday, ecember, 00 mil mil mil mil mil mil Mb : KJGT^0 Mb : KG-T^0 R /F_@VG R /F_@VG 0 0U/0V_@VG 0 0U/0V_@VG V N Q UQS VQ UQ Q UM UQS Q UQ VQ UQ VQ VQ UQ0 VQ UQ Q UQ UQ Q UQ V E N E E Q E LQS E VQ E LQ F Q F LM F LQS F Q F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H Q H LQ H LQ H Q0 H LQ H VL J VREF J J L J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M N N N N N P P P P P V R R N R N R N R U GR-G@VG U GR-G@VG.U_@VG.U_@VG U_@VG U_@VG R /F_@VG R /F_@VG R /F_@VG R /F_@VG 0.0U_@VG 0.0U_@VG.U_@VG.U_@VG R /F_@VG R /F_@VG.U_@VG.U_@VG 000P_@VG 000P_@VG R /F_@VG R /F_@VG U_@VG U_@VG.U_@VG.U_@VG.0U_@VG.0U_@VG L 0_@VG L 0_@VG.0U_@VG.0U_@VG L 0_@VG L 0_@VG R /F_@VG R /F_@VG R /F_@VG R /F_@VG.0U_@VG.0U_@VG R /F_@VG R /F_@VG 0.U_@VG 0.U_@VG R 0/F_@VG R 0/F_@VG R 0/F_@VG R 0/F_@VG R /F_@VG R /F_@VG.U_@VG.U_@VG 000P_@VG 000P_@VG R /F_@VG R /F_@VG R 0/F_@VG R 0/F_@VG R 0/F_@VG R 0/F_@VG R *0_@VG R *0_@VG.U_@VG.U_@VG 000P_@VG 000P_@VG.0U_@VG.0U_@VG R /F_@VG R /F_@VG R 0/F_@VG R 0/F_@VG R /F_@VG R /F_@VG.U_@VG.U_@VG 0U/0V_@VG 0U/0V_@VG L 0_@VG L 0_@VG 000P_@VG 000P_@VG R 0/F_@VG R 0/F_@VG R0 /F_@VG R0 /F_@VG R /F_@VG R /F_@VG 0.U_@VG 0.U_@VG 0 U_@VG 0 U_@VG V N Q UQS VQ UQ Q UM UQS Q UQ VQ UQ VQ VQ UQ0 VQ UQ Q UQ UQ Q UQ V E N E E Q E LQS E VQ E LQ F Q F LM F LQS F Q F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H Q H LQ H LQ H Q0 H LQ H VL J VREF J J L J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M N N N N N P P P P P V R R N R N R N R U GR-G@VG U GR-G@VG.U_@VG.U_@VG R /F_@VG R /F_@VG.U_@VG.U_@VG Q N00@VG Q N00@VG U_@VG U_@VG.0U_@VG.0U_@VG R /F_@VG R /F_@VG R 0/F_@VG R 0/F_@VG V N Q UQS VQ UQ Q UM UQS Q UQ VQ UQ VQ VQ UQ0 VQ UQ Q UQ UQ Q UQ V E N E E Q E LQS E VQ E LQ F Q F LM F LQS F Q F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H Q H LQ H LQ H Q0 H LQ H VL J VREF J J L J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M N N N N N P P P P P V R R N R N R N R U GR-G@VG U GR-G@VG L 0_@VG L 0_@VG.U_@VG.U_@VG 0U/0V_@VG 0U/0V_@VG R 0/F_@VG R 0/F_@VG V N Q UQS VQ UQ Q UM UQS Q UQ VQ UQ VQ VQ UQ0 VQ UQ Q UQ UQ Q UQ V E N E E Q E LQS E VQ E LQ F Q F LM F LQS F Q F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H Q H LQ H LQ H Q0 H LQ H VL J VREF J J L J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M N N N N N P P P P P V R R N R N R N R U GR-G@VG U GR-G@VG.U_@VG.U_@VG R 0K_@VG R 0K_@VG Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL.U_@VG.U_@VG 0 0U/0V_@VG 0 0U/0V_@VG