UNSIGNED BINARY NUMBERS DIGITAL ELECTRONICS SYSTEM DESIGN WHAT ABOUT NEGATIVE NUMBERS? BINARY ADDITION 11/9/2018

Similar documents
Combinational Logic Design Arithmetic Functions and Circuits

Combinational Logic. By : Ali Mustafa

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits

CprE 281: Digital Logic

Complement Arithmetic

14:332:231 DIGITAL LOGIC DESIGN. Why Binary Number System?

EE260: Digital Design, Spring n Digital Computers. n Number Systems. n Representations. n Conversions. n Arithmetic Operations.

Carry Look Ahead Adders

Module 2. Basic Digital Building Blocks. Binary Arithmetic & Arithmetic Circuits Comparators, Decoders, Encoders, Multiplexors Flip-Flops

Introduction to Digital Logic Missouri S&T University CPE 2210 Subtractors

Hakim Weatherspoon CS 3410 Computer Science Cornell University

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

COMBINATIONAL LOGIC FUNCTIONS

Fundamentals of Digital Design

14:332:231 DIGITAL LOGIC DESIGN. 2 s-complement Representation

Design of Sequential Circuits

CS 140 Lecture 14 Standard Combinational Modules

Building a Computer Adder

Total Time = 90 Minutes, Total Marks = 100. Total /10 /25 /20 /10 /15 /20

CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April

Lecture 5: Arithmetic

ELCT201: DIGITAL LOGIC DESIGN

Numbers and Arithmetic

Binary addition by hand. Adding two bits

ENGIN 112 Intro to Electrical and Computer Engineering

ECE380 Digital Logic. Positional representation

Numbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C.

Hardware Design I Chap. 4 Representative combinational logic

Chapter 03: Computer Arithmetic. Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design

Lecture 2 Review on Digital Logic (Part 1)

Numbers and Arithmetic

Combina-onal Logic Chapter 4. Topics. Combina-on Circuit 10/13/10. EECE 256 Dr. Sidney Fels Steven Oldridge

ELEN Electronique numérique

Number representation

ECE/CS 250 Computer Architecture

Logic. Combinational. inputs. outputs. the result. system can

CprE 281: Digital Logic

Digital Logic (2) Boolean Algebra

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

We are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors

Numbering Systems. Contents: Binary & Decimal. Converting From: B D, D B. Arithmetic operation on Binary.

211: Computer Architecture Summer 2016

Chapter 5 Arithmetic Circuits

Adders, subtractors comparators, multipliers and other ALU elements

Binary addition example worked out

14:332:231 DIGITAL LOGIC DESIGN

ECE260: Fundamentals of Computer Engineering

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

UNIT II COMBINATIONAL CIRCUITS:

ECE 250 / CPS 250 Computer Architecture. Basics of Logic Design Boolean Algebra, Logic Gates

A crash course in Digital Logic

Systems I: Computer Organization and Architecture

Adders, subtractors comparators, multipliers and other ALU elements

Computer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

A B OUT_0 OUT_1 OUT_2 OUT_

Chapter 1 CSCI

Adders - Subtractors

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

Chapter 5. Digital systems. 5.1 Boolean algebra Negation, conjunction and disjunction

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design

Lecture 8: Sequential Multipliers

E40M. Binary Numbers. M. Horowitz, J. Plummer, R. Howe 1

ECE 2300 Digital Logic & Computer Organization

CSE 20 DISCRETE MATH. Fall

Class Website:

What s the Deal? MULTIPLICATION. Time to multiply

LOGIC GATES. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

Lecture 7: Logic design. Combinational logic circuits

Ex code

IT T35 Digital system desigm y - ii /s - iii

CMP 334: Seventh Class

Combinational Logic. Review of Combinational Logic 1

hexadecimal-to-decimal conversion

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Exam for Physics 4051, October 31, 2008

EECS Variable Logic Functions

Implementation of Boolean Logic by Digital Circuits

Chapter 7 Logic Circuits

Review Problem 1. should be on. door state, false if light should be on when a door is open. v Describe when the dome/interior light of the car

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.

Design of Combinational Logic

Review for Test 1 : Ch1 5

convert a two s complement number back into a recognizable magnitude.

Logic Simplification. Boolean Simplification Example. Applying Boolean Identities F = A B C + A B C + A BC + ABC. Karnaugh Maps 2/10/2009 COMP370 1

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H Lipasti. Fall 2010 University i of Wisconsin-Madison

Arithmetic Circuits How to add and subtract using combinational logic Setting flags Adding faster

Digital Electronics Circuits 2017

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Introduction to Digital Logic

Sample Test Paper - I

CSE477 VLSI Digital Circuits Fall Lecture 20: Adder Design

1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p

CPE100: Digital Logic Design I

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.

CMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing

Transcription:

DIGITAL ELECTRONICS SYSTEM DESIGN LL 2018 PROFS. IRIS BAHAR & ROD BERESFORD NOVEMBER 9, 2018 LECTURE 19: BINARY ADDITION, UNSIGNED BINARY NUMBERS For the binary number b n-1 b n-2 b 1 b 0. b -1 b -2 b -m the decimal number is: Example: 101.001 2 =? D b 2 5 + 2-3 = 5.125 BINARY ADDITION Addition is an essential operation for all kinds of computing We need to understand how to do this for binary numbers We need to understand how to do this for positive and negative numbers We need to understand how to implement this efficiently in hardware 5 + 7 1 2 Carry Sum 1 1 1 1 0 1 + 1 1 1 1 1 0 0 Carryout Sums Carry bits 5 7 12 WHAT ABOUT NEGATIVE NUMBERS? So far we have just considered unsigned numbers when converting from base 10 to binary. What about negative numbers and how do we add two signed numbers in binary? 3 ways of representing signed numbers: Signed magnitude 1 s complement 2 s complement 1

SIGNED MAGNITUDE The Most Significant Bit (MSB) is the sign bit: 0 positive, 1 negative The rest of the bits define the magnitude Need to know how many bits are available to represent a number! Example: (2) 10 = (0010) 2 = (0 010) S&M (-2) 10 = (1 010) S&M Makes adding and subtracting a pain Can t just add them regularly Also, two representations for zero (+0 and -0) SIGNED MAGNITUDE ADDITION (1) 10 0001 + (5) 10 + 0101 (6) 10 0110 (both positive, so a positive result) (-2) 10 1010 + (-4) 10 + 1100 (-6) 10 1110 (both negative, so keep the negative sign) ( 4) 10 0100 (larger number smaller number) + (-3) 10 + 1011 (keep the sign of the larger number) ( 1) 10 0001 (signs are different subtract smaller from larger number, keep sign of larger number) Need a comparator to supplement adder/subtractor 1 S COMPLEMENT 1 S COMPLEMENT ADD/SUBTRACT To negate a number, complement (invert, flip) each bit Example: ( 4) 10 = (0100) 2 = (0100) 1 s comp (-4) 10 = (1011) 1 s comp Like sign and magnitude, the high bit indicates the sign of the number What about adding and subtracting? (-2) 10 1101 + (-4) 10 + 1011 (-6) 10 11000 -- not right, (-6) 10 = (1001) 1 s comp + 1 add C out back to LSB --------- 1001 -- now it works (4) 10 0100 + (-3) 10 + 1100 (1) 10 10000 -- not right, add Cout back to LSB + 1 --------- 0001 -- now it works Better than sign and magnitude (can subtract by adding the negative) But requires 2 addition operations (need to conditionally add C out ) 2

ANOTHER ENCODING FOR BINARY 2 S COMPLEMENT REPRESENTATION MSB has weight -2 n-1 Range of an n-bit number is -2 n-1 through 2 n-1-1 Most negative number (-2 n-1 ) has no positive counterpart -2 2-2 1-2 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0-4 1 0 1-3 1 1 0-2 1 1 1-1 2 S COMPLEMENT To negate in 2 s complement, complement (flip) each bit and then add 1 Example: Represent (-5) 10 in 2 s complement using 4 bits (5) 10 = (0101) 2 s comp 1010 + 1 -------- 1011 (-5) 10 = (1011) 2 s comp Like sign and magnitude, the MSB indicates the sign of the number Sign extension: Pad the high bits with the value of the MSB Example: (-6) 10 = (1010) 2 = (111010) 2 Range: for n bits: [-2 n-1, (2 n-1 1)] 1 more neg. than pos. number 2 S COMPLEMENT ADDITION Add numbers as you would for unsigned addition Examples with 4 bits: 4 0100-4 + 1100 (subtract by negating 2 nd number & adding) ------ ------ 0 10000 (ignore carry out since signs were different) 5 0101 + 6 + 0110 ------ ------- 11 1011 -- overflow (two positives, got a negative) 2 s complement has one representation for 0 and arithmetic is easier It s the most commonly used negative number representation 3

SIGNED BINARY NUMBERS GRAY CODES Represent decimal numbers 0-8 in binary such that only bit changes value as you count up/down Why would such an encoding be advantageous? Decimal Gray code 0 0000 1 0001 2 0011 3 0010 4 0110 5 0111 6 0101 7 0100 8 1100 9 1101 HALF ADDER FULL ADDER Truth Table a b Sum Carry Truth Table a b carry sum 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 a b Cin Sum Carry Id a b c in carry sum 0 0 0 0 0 0 1 0 0 1 0 1 2 0 1 0 0 1 3 0 1 1 1 0 4 1 0 0 0 1 5 1 0 1 1 0 6 1 1 0 1 0 7 1 1 1 1 1 How do you express sum and carry as Boolean functions? 4

THE FULL ADDER BUILDING A BINARY ADDER A C in B S A B C in Full Adder () C out S 1 1 1 1 0 1 + 1 1 1 1 1 0 0 Carryout Sums Carry bits 5 (A) 7 (B) 12 (S) Inputs & outputs for the i th bit position C out Inputs: A i, B i, and C i (carry-in) Outputs: S i (sum) and C i+1 (carry out) Carry out of a bit position is the carry in for the next bit position THE RIPPLE CARRY ADDER A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 2 S COMPLEMENT SUBTRACTION Negate second operand and add: C out =C 4 C 0 =C in 01101000 (104) 00010001 (17) S 3 S 2 The carry out of one stage ripples to the carry in of the next S 1 S 0 01101000 (104) 11101111 (-17) 01010111 (87) 5

A 64-BIT ADDER/SUBTRACTOR GLITCHING IN A RIPPLE CARRY ADDER Ripple Carry Adder (RCA) built out of 64 Full Adders Subtraction complement all subtrahend bits (xor gates) and set low order carry-in RCA Simple logic, so low (area) cost Slow: (O(N) for N bits) and lots of glitching add/subt B 0 B 1 B 2 B 63 A 0 A 1 A 2 A 63 C 0 =C in S 0 C 1 S 1 C 2 S 2... C 3 C 63 S 63 C 64 =C out S15 S Output Voltage (V) Cin S14 S2 S1 S0 3 2 S3 Cin S4 S15 1 S2 S5 S10 S1 S0 0 0 2 4 6 8 10 12 Time (ps) 6