ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28
COURSE OUTLINE. Introduction 2. Gate-Level Minimization 3. Combinational Logic 4. Synchronous Sequential Logic 5. Registers and Counters 6. Memories and Programmable Logic 2
LECTURE OUTLINE Combinational Logic Circuits Steps of Combinational Logic Design The XOR Function Half Adder Full Adder Binary Adder/Subtractor Binary Multiplier Magnitude Comparator Parity Generator/Checker 3
COMBINATIONAL LOGIC Combinational logic circuits can have any number of inputs and outputs The logic states of the inputs at any given instant determine the state of the output Sequential circuits, which we will discuss later in this course, will feature circuits in which the outputs are not determined solely by the inputs at the same time 4
HOW TO DESIGN A COMBINATIONAL LOGIC CIRCUIT?. From the specifications of the circuit, determine the required number of inputs and outputs and assign a letter (symbol) to each 2. Derive the truth table that defines the required relationship between the inputs and outputs 3. Obtain the simplified Boolean functions for each output as a function of the input variables (using a K- map) 4. Sketch the logic diagram 5
DESIGN PROBLEM Design a digital system whose output is defined as logically low if the 4-bit input binary number is a multiple of 3; otherwise, the output will be logically high. The output is defined if and only if the input binary number is greater than 2 6
INPUT/OUTPUT RELATIONSHIP AND TRUTH TABLE Design a digital system whose output is defined as logically low if the 4-bit input binary number is a multiple of 3; otherwise, the output will be logically high The output is defined if and only if the input binary number is greater than 2 7
BOOLEAN FUNCTION SIMPLIFICATION USING A K-MAP 8
BOOLEAN FUNCTION SIMPLIFICATION USING A K-MAP SOP POS Y SOP = B D + A C + A BD + BC D + AB C + ACD Y POS = (A + B)(B + C + D )(A + C + D)(A + B + C + D)(A + B + C + D ) 9
SKETCHING THE LOGIC DIAGRAM
XOR THE XOR FUNCTION The XOR symbol is denoted as Its Boolean operation is x y = xy + x y The XNOR symbol is denoted as X Y Z Its Boolean operation is x ʘ y = xy + x y The identities of the XOR operation are XNOR given by: x = x x = x x x = x x = X Y Z Commutative and associative: A B = B A (A B) C = A (B C) = A B C x y = x y
THE XOR IMPLEMENTATION The output analysis for the first circuit is very easy! The output at each of the NAND gates for the second circuit is as follows: At L: xy = x + y At L2: x(x + y ) = xx + xy = xy = x + y At L3: y(x + y ) = x y + yy = x y = x + y L L2 L3 L4 At L4: (x +y)(x + y ) = (x + y) + (x + y ) = xy + x y = x y 2
ARITHMETIC CIRCUITS We will continue with the design of digital logic circuits One of the famous digital logic circuits is the calculator How to design it? 3
ARITHMETIC CIRCUITS An arithmetic circuit is a combinational circuit that performs arithmetic operations such as: Addition Subtraction Multiplication Division A combinational circuit that performs the addition of two bits is called a Half Adder + = + = + = + = carry outputs one digit outputs two digits! sum So, we need two binary outputs to represent the addition block (carry & sum) 4
HALF ADDER It is required to design a combinational circuit that adds two binary numbers and produces the output in the form of two bits, sum and carry Solution:. We need to determine the inputs and output of the system and give letters for all of them: Our system has two inputs (x, y) and two outputs (S, C) x y Half Adder S C 5
HALF ADDER 2. Derive the truth table according to the given relation between inputs and outputs Inputs x y Outputs C S 6
HALF ADDER 3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map C = xy S = xy + x y = x y 7
HALF ADDER 4. Sketch the logic diagram 8
FULL ADDER It is required to design a combinational circuit that adds three binary numbers and produces the output in the form of two bits, sum and carry Solution:. We need to determine the inputs and outputs of the system and give letters for all of them: Our system has three inputs (x, y, z) and two outputs (S, C) x y z Full Adder S C 9
2 FULL ADDER 2. Derive the truth table according to the given relation between the inputs and outputs Decimal Equivalent Outputs Inputs S C z y x 2 2 2 3
FULL ADDER 3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map Remember that: S = x y z + x yz + xy z + xyz = z x y + xy + z x y + xy = z(x y + xy ) + z (x y + xy ) = z x y + z x y = z x y = x y z x y = x y, x y = xy + x y, x y = xy + x y 2
FULL ADDER 3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map C = xy + xz + yz 22
FULL ADDER 4. Sketch the logic diagram S = x y z + x yz + xy z + xyz C = xy + xz + yz 23
FULL ADDER The logic circuit for the full adder could also be sketched using two half adders and a single OR gate Half adder Half adder S = x y z Compare the obtained Boolean expression for C here and the one obtained in slide 22 C = x y z + xy = xy + x y z + xy = xy z + x yz + xy 24
4-BIT BINARY RIPPLE CARRY ADDER Connecting n full adders in cascade allows us to add n-bit binary numbers together Example: Connecting 4 full adders in cascade allows us to add to. A = A 3 A 2 A A = B = B 3 B 2 B B = 25
4-BIT BINARY RIPPLE CARRY ADDER B 3 = A 3 = B 2 = A 2 = B = A = B = A = C = C 4 = S 3 = S 2 = S = S = This adder is extremely slow, as each stage must wait for the previous one to get the carry from it! 26
BINARY SUBTRACTOR The subtraction of binary numbers can be easily done using complements The subtraction A B is done by taking the 2 s complement of B and adding it to A The 2 s complement can be obtained by taking the s complement and adding to the least significant bit (LSB) The s complement can be implemented easily with an inverter gate We can add to the sum by making the initial input carry of the parallel adder equal to 27
BINARY ADDER/SUBTRACTOR This is equivalent to A plus the 2 s complement of B Subtractor B A FA S C out C in = Adder/Subtractor B A FA S C out C in If C in =, circuit acts as an Adder If C in =, circuit acts as a Subtractor Remember that B = B and B = B 28
BINARY MULTIPLIER 2 bits 2 bits = max 4 bits () 2 () 2 = () 2 (3) (3) = (9) 29
MAGNITUDE COMPARATOR It is required to design a circuit to compare between two inputs A = {A, A 2 } and B = {B, B 2 }. Both inputs consist of two binary bits and the circuit has three outputs: Greater than, Less than or Equal Solution:. We need to determine the inputs and outputs of the system and give letters for all of them: Our system has four inputs (A, A, B, B ) and three outputs (G, L, E) A A B B Magnitude Comparator 3 G L E
MAGNITUDE COMPARATOR 2. Derive the truth table that defines the required relationship between the inputs and outputs 3
MAGNITUDE COMPARATOR 3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map G A, A, B, B = A A B + A B B + A B 32
MAGNITUDE COMPARATOR 3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map E A, A, B, B = A A B B + A A B B +A A B B + A A B B 33
MAGNITUDE COMPARATOR 3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map L A, A, B, B = A A B + A B B + A B 34
MAGNITUDE COMPARATOR 4. Sketch the logic diagram for the output G A A B A G B B A B G A, A, B, B = A A B + A B B + A B 35
MAGNITUDE COMPARATOR 4. Sketch the logic diagram for the output E A A A B B A B B A A B B A A B B E E A, A, B, B = A A B B + A A B B +A A B B + A A B B 36
MAGNITUDE COMPARATOR 4. Sketch the logic diagram for the output L A A B A L B B A B L A, A, B, B = A A B + A B B + A B 37
PARITY BITS XOR functions are very useful in systems requiring error detection and correction (e.g. communication systems) A parity bit is used to detect errors that occur during the transmission of binary information A parity bit is an extra bit included with a binary message to make the number of s either even or odd The message, including the parity bit, is transmitted and then checked for errors at the receiver 38
PARITY BITS An error is detected if the checked parity does not correspond with the one transmitted The circuit that generates the parity bit in the transmitter is called a parity generator The circuit that checks the parity bit in the receiver is called a parity checker 39
PARITY BITS: AN EXAMPLE OF EVEN PARITY Consider a three-bit message to be transmitted together with an evenparity bit For even parity, the bit P must be generated to make the total number of s even P is an odd function, thus we can express it using the XOR operator as P = x y z 4
PARITY BITS: AN EXAMPLE OF EVEN PARITY The three-bits in the message, as well as the parity bit, are transmitted to the destination At the destination, a parity checker circuit is used to check for possible errors Since the information was transmitted with even parity, the four bits received must have an even number of s An error occurs during the transmission if the four bits received have an odd number of s (this means that a bit has changed in value) The output of the parity checker circuit will be equal to if an error occurs 4
PARITY BITS: AN EXAMPLE OF EVEN PARITY The output of this circuit is equal to whenever there is an odd number of s in the inputs Does having a value of C = insures that there are no errors? 42
PARITY GENERATOR AND CHECKER CIRCUITS A parity generator/checker circuit can be implemented in a single circuit This is done if the input P is connected to logic and the output is marked with P This is possible because z = z 43