Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br
Sequential Logic CMOS Sequential Circuits inputs Current State Combinational Logic State outputs Next State 2 Storage Mechanisms: Positive feedback Charge-Based Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.2
Sequential Logic CMOS Sequential Circuits inputs Current State Combinational Logic Registers outputs Next State Positive Feedback: uses latches or registers Slide 18.3
Naming Conventions In Rabaey s IC book: A latch is level sensitive A register is edge-triggered Many other books: Flip-flop is an edge-triggered Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.4
Latch Versus Register Latch stores data when clock is low Register stores data when clock rises Clk Clk Clk Clk Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.5
Latches Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.6
Characterizing Timing Register Latch t 2 or t O Clk Clk t C2 or t CO t C2 or t CO Slide 18.7
Timing efinitions CMOS Sequential Circuits Register tsu th t ATA STABLE t Clk tco ATA STABLE t tsu = setup time th = hold time tco = tc2q = maximum propagation delay (or time from clock to output ) tcd = minimum propagation delay (or contamination delay) Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.8
Maximum Clock Frequency td Logic = maximum propagation delay tc Logic = minimum propagation delay (or contamination delay) ck T inputs Combinational Logic outputs tco td Logic tsu Current State Registers Next State T tco + td Logic + tsu f = 1/T tsu, th, tco, tcd Slide 18.9
Avoiding Race Condition td Logic = maximum propagation delay tc Logic = minimum propagation delay (or contamination delay) ck T inputs Combinational Logic outputs th tc Logic Current State Registers Next State tcd tcd + tc Logic th tsu, th, tco, tcd Slide 18.1
Maximum Clock Frequency inputs Current State Combinational Logic Registers outputs Next State ck tco T td Logic tsu In contemporary designs: The maximum logic depth is around 12 gates Approx. 15% of the clock period is due to register overheads tcd + tc Logic th is quite easy to meet if clock slew can be disregarded Slide 18.11
Positive Feedback: Bi-Stability V i1 V o1 = V i2 V o2 V o1 V i2 V o2 = V i1 V i1 V o2 Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.12
Positive Feedback: Bi-Stability V i1 V o1 = V i2 V o2 V o1 V i2 V o2 = V i1 V i1 V o2 A V o1 = V i2 C Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.13 B V o2 = V i1
Meta-Stability CMOS Sequential Circuits V o1 = V i2 G>1 around C V o1 = V i2 G<1 around A and around B metastable point d V o2 = V i1 d V o2 = V i1 G is the loop gain Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.14
Changing the State of a Bistable Cutting the feedback loop: Multiplexer-based structure Once the loop is open, a new value can be easily written in This is the most popular approach in today s latches Overpowering the feedback loop: By applying a trigger signal at the input of the bistable a new value is forced into the cell Careful sizing of the transistors in the feedback loop and trigger circuitry Currently, is used to built static background memories 1 1 1 1 Slide 18.15
Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Converting into a MUX Slide 18.16
Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Converting into a MUX Slide 18.17
Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Forcing the state If the transmission gate has minimum sized transistors, the lower inverter must be even weaker! Slide 18.18
Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Forcing the state Slide 18.19
Writing into a Static Latch Converting into a MUX Forcing the state Slide 18.2
Mux-Based Latches Negative latch (transparent when = ) Positive latch (transparent when = 1) 1 1 Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.21
Mux-Based Latch CMOS Sequential Circuits : α 1 = 1 How many transistor loads seen by per bit? Slide 18.22
Mux-Based Latch V OH = V - V Tn V V - V Tn M M V NMOS only Noise margin degradation V - V Tn Slide 18.23
Mux-Based Latch V V - V Tn M M t phl.69 R eq-nmos C L R eq (R on (t 1 ) + R on (t 2 ))/2 R on (t) V S (t)/i (t) NMOS only V - V Tn V Switching performance degradation C L Slide 18.24
Mux-Based Latch CMOS Sequential Circuits V V - V Tn M Not completely OFF M V NMOS only V - V Tn Short-circuit power increases Slide 18.25
Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.26
Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 I 1 T 1 M I 4 T 3 I Slide 18.27
Master-Slave Register Multiplexer-based latch pair tsu V I2-T2 1 I 2 I 3 T 2 I 3 I 5 T 4 I 6 1 I 1 T 1 I 1 T 1 M I 4 T 3 I 1 1 Slide 18.28
Setup Time CMOS Sequential Circuits Source: Rabaey; Chandrakasan; Nikolic, 23 tsu =.21 ns Slide 18.29 tsu =.2 ns
Master-Slave Register Multiplexer-based latch pair V I2-T2 tco 1 I 2 I 3 T 2 I 3 I 5 T 4 I 6 1 I 1 T 1 I 1 T 1 M I 4 T 3 I 1 1 Slide 18.3
Master-Slave Register Multiplexer-based latch pair tco 1 I 2 T 2 I 3 I 5 T 4 I 6 I 6 1 I 1 T 1 M I 4 T 3 1 I 1 Slide 18.31
Clk to Output () elay tco LH tco HL Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.32
Reduced Clock Load Master-Salve Register Must be weak Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.33
Avoiding Clock Overlap X A B may change on the rising edge! Node A driven by and B: undefined state! Source: Rabaey; Chandrakasan; Nikolic, 23 Slide 18.34
Avoiding Clock Overlap φ1 X φ2 A B φ2 φ1 φ1 φ2 Non-overlap Slide 18.35
Avoiding Clock Overlap φ1 X φ2 A B φ2 φ1 φ1 φ2 Non-overlap Slide 18.36
Avoiding Clock Overlap φ1 X φ2 A B φ2 φ1 φ1 φ2 Non-overlap Slide 18.37
Avoiding Clock Overlap φ1 X φ2 A B φ2 φ1 φ1 φ2 Non-overlap Slide 18.38
Overpowering the Feedback Loop Cross-Coupled Pairs NOR-based set-reset Source: Rabaey; Chandrakasan; Nikolic, 23 Asynchronous doesn t fit in dominant methodology! (99% of the ICs are synchronous) How to turn it into a synchronous circuit? Slide 18.39
Ratioed CMOS SR Latch This is not used in datapaths any more, but is a basic building memory cell (W/L) M2 = 3 (W/L) M1 Slide 18.4 (W/L) M4 = 3 (W/L) M3
Ratioed CMOS SR Latch = 1: R = 1 @ = 1 = V = V V = V /2 3(W/L) M7-M8 (W/L) M4 (W/L) M2 = 3 (W/L) M1 Slide 18.41 (W/L) M4 = 3 (W/L) M3
Ratioed CMOS SR Latch = : S = 1 @ = 1 = 1 V = V V = V /2 3(W/L) M5-M6 (W/L) M2 (W/L) M2 = 3 (W/L) M1 Slide 18.42 (W/L) M4 = 3 (W/L) M3
Ratioed CMOS SR Latch 3(W/L) M5-M6 (W/L) M2 = (W M2 /L min ) = (3W M1 /L min ) (W/L) M5-M6 = W/(2 L min ) W = W M5 = W M6 (W M2 /L min ) = 3 (W M1 / L min ) Slide 18.43
Ratioed CMOS SR Latch 3(W/L) M5-M6 3 W/(2 L min ) = 3 W M1 /L min For W M1 = 2 L min : W = W M5 = W M6 4 L min (W M2 /L min ) = 3 (W M1 / L min ) Slide 18.44 How accurate is the value of W for L min =.25 µ and W M1 =.5 µ?
Ratioed CMOS SR Latch Sizing Issues W 3 L min is enough! Transient response Slide 18.45
Synchronized Cross-Coupled NAN Requires proper transitor sizing: ratioed design. Slide 18.46
Cross-Coupled NAN What is the corresponding truth table? For a given tp, which requires more area synchronized cross-coupled NOR or NAN? Slide 18.47
Generating Two-Phase Non-Overlapping Clock S R 1 Initial Values Slide 18.48
Generating Two-Phase Non-Overlapping Clock S 1 R 1 1 Time = t o Slide 18.49
Generating Two-Phase Non-Overlapping Clock S 1 1 R 1 1 Time = t o + d Slide 18.5
Generating Two-Phase Non-Overlapping Clock S 1 1 1 1 R 1 1 Time = t o + 2d Slide 18.51
Generating Two-Phase Non-Overlapping Clock S φ1 R φ2 φ1 φ2 Non-overlap Slide 18.52
CMOS Sequential References Circuits 1. RABAEY, J; CHANRAKASAN, A.; NIKOLIC, B. igital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, 23. ISBN: -13-9996-3. 2. WESTE, Neil; HARRIS, avid. CMOS VLSI esign: a circuits and systems perspective. Addison-Wesley, 4 th Edition, 21. ISBN 978-321547743. Slide 18.53