AN ABSTRACT OF THE THESIS OF Madhulatha Bonu for the degree of Master of Science in Electrical and Computer Engineering presented on November 8, 006. Title: Noise Coupling Techniques in Multi-Cell Delta-Sigma Modulators. Abstract approved: Gabor C. Temes High performance multi-cell delta-sigma modulators are a preferred choice in applications which require programmability. Multi-cell delta-sigma modulators with M unit cells provide 0log 0 (M) SNR improvement for the same thermal noise and bias power due to the uncorrelated quantization noises of the M unit ADCs. This concept is used in this thesis to illustrate novel third-order and fourth-order noise shaping structures using split ADC of second order, and hence providing higher-order noise shaping with the same thermal noise and bias power as that of a conventional second-order structure. The additional SNR improvement due to split ADC can be traded off with power. Switched capacitor implementations are also proposed to confirm that both third-order and fourth-order noise shaping structures require only two opamps by using self-enhancement technique in a second-order single stage. The novel third-order structure discussed in this thesis is compared to a conventional second-order, a single-stage third-order and a + MASH in terms of performance, stability and sensitivity to opamp non-idealities. Similar comparisons are done for the proposed fourth-order structure with a conventional second-order, a single-stage fourth-order and a + MASH ADC. Simulation results show that the novel noise shaping structures for third and fourth order are highly robust, and show performance similar to other existing structures for the same order of noise shaping.
Copyright by Madhulatha Bonu November 8, 006 All Rights Reserved
Noise Coupling Techniques in Multi-Cell Delta-Sigma Modulators by Madhulatha Bonu A THESIS submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science Presented November 8, 006 Commencement June 007
Master of Science thesis of Madhulatha Bonu presented on November 8, 006 APPROVED: Major Professor, representing Electrical and Computer Engineering Director of the School of Electrical Engineering and Computer Science Dean of the Graduate School I understand that my thesis will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my thesis to any reader upon request. Madhulatha Bonu, Author
ACKNOWLEDGEMENTS I want to express my deep gratitude to my research advisor, Dr. Gabor C. Temes who gave me an opportunity to work under his guidance. I had the opportunity to take his classes on switched capacitor circuits and delta sigma modulators and benefited a lot from them. I thank him for being very understanding and nice to me. I would like to thank Dr. Pavan Hanumolu for accepting to serve on my committee. I would like to thank him for being very helpful and friendly at all times. I would like to thank Dr. Albrecht Jander for accepting to serve on my committee. I also want to express my thanks to Dr. Harold R. Parks for accepting to serve as GCR for my defense. I also would like to mention that I am very grateful to Dr. Un-Ku Moon, who has kindly assisted me with funding for the whole of my first year at OSU. But for his help, I would not have been able to continue my studies at OSU. I thank him for all his kindness and help. I benefited from all the basic and advanced concepts of analog circuit design taught by him in his classes. I would like to thank Dr. Karti Mayaram from whose classes I learnt all the basics of analog and RF circuit design. I thank him for being very kind and nice whenever I approached him with any problem. I would like to thank Kye Hyung Lee with whom I worked and interacted a lot during the course of research work. I am very thankful for all the valuable technical discussions that I had with him. I want to thank Todd Brooks of BroadCom Corporation for giving me a wonderful internship opportunity under his guidance. I am thankful for all his valuable feedback and suggestions during the course of internship. I enjoyed every bit of time that I spent in his group. I am grateful to my mentor at BroadCom, Felix Cheung, who is a wonderful person and guide. He mentored me throughout the course of internship with lot of patience and taught me a lot. His valuable suggestions and feedback helped me to a great extent during the course of my research work at school.
I want to thank my friend Thirumalai Rengachari of Cyrrus Logic, who spent a lot of his time discussing with me many system level and circuit design details. His valuable suggestions helped me solve many problems in my research work. I want to express my deep gratitude to Jose Silva of Analog Devices Inc., for helping me with problems in switched capacitor circuits. I would like to thank Matt Miller of Freescale Semiconductor, for being very helpful and for all his technical guidance.i would like to thank Robert Batten and Napong for their help in debugging some problems during the course of my research work. I am thankful to Dr. Ferne Simendinger, graduate coordinator of EECS for being extremely helpful, patient in guiding me throughout my masters with all administration and masters program related questions. I appreciate all her help and advices. I would like to thank Dr. Bella Bose for being extremely kind and nice to me. I thank him for being very concerned and helpful at all times. I want to thank my friend, guide and a very important person in my life, Sudhakar who has helped me at all times throughout my masters with his constant support, encouragement, constructive criticism and care. I am thankful to God for helping me meet this wonderful person at this university. I want to thank my very good friend Sasikumar Arunachalam for being a true and reliable friend. I feel privileged to have a friend like him. I wish to express my gratitude to Gokul for being a good friend. I want to convey my thanks to Elizebeth, my best friend for all the moral support in good and bad times. I want to express my heartfelt thanks to my dad who is responsible for what I am today. He is a constant source of inspiration for me. But for him, I am nothing. I want to thank my mom and my sisters who took care of me and for having immense trust in my abilities. I thank them for being always supportive and encouraging.
TABLE OF CONTENTS Page. INTRODUCTION.. Motivation.. Contributions.3. Thesis Organization.. 3. BASICS OF OVER-SAMPLED DELTA-SIGMA 4.. Over-Sampled Data Converters 4.. Over-Sampled Data Converters with Noise Shaping 5.3. First Order Noise Shaping. 6.4. Second Order Noise Shaping 6 3. MULTI-CELL DELTA-SIGMA MODULATORS... 9 3.. Motivation.. 9 3.. Architecture 9 3.3. Simulation Conditions and results. 3 4. THIRD ORDER NOISE SHAPING.. 7 4.. Cross-enhanced -cell architecture.. 8 4... Simulation with ideal blocks... 0 4... Simulation with non-idealities included.. 4..3. Alternative implementations 3 4.. Self-enhanced -cell architecture.. 5 4... Simulation with ideal blocks... 6 4... Simulation with non-idealities included.. 6
TABLE OF CONTENTS (Continued) Page 4.3. uantization error injection mismatch. 9 4.3.. uantization injection error in cross-enhanced -cell.. 30 4.3.. uantization injection error in self-enhanced -cell. 3 4.3.3. Simulations with quantization injection error mismatch... 3 4.4. Self-enhanced -cell architecture.. 34 4.4.. Simulation with ideal blocks. 35 4.4.. Simulation with non-idealities included 36 4.5. Performance Comparison.. 37 4.5.. Stability Analysis.. 38 4.5.. Sensitivity to opamp DC gain.. 45 4.6. Multi-cell DSM with higher order noise shaping. 47 4.7. Cross-correlation of quantization errors... 49 4.8. Switched Capacitor Implementation 57 5. FOURTH ORDER NOISE SHAPING.. 63 5.. Cross-enhanced -cell architecture.. 64 5... Simulation with ideal blocks 66 5... Simulation with non-idealities included.. 69 5.. Self-enhanced -cell architecture.. 74 5... Simulation with ideal blocks.. 75 5... Simulation with non-idealities included 76 5..3. Alternative implementations...79 5.3. Self-enhanced -cell architecture.. 80
TABLE OF CONTENTS (Continued) Page 5.3.. Simulation with ideal blocks. 8 5.3.. Simulation with non-idealities included 8 5.4. uantization error injection mismatch. 84 5.4.. uantization injection error in cross-enhanced -cell.. 85 5.4.. uantization injection error in self-enhanced -cell. 86 5.4.3. Simulations with quantization injection error mismatch...87 5.5. Performance Comparison...88 5.5.. Stability Analysis.. 89 5.5.. Sensitivity to opamp DC gain... 96 5.6. Multi-cell DSM with fourth order noise shaping...97 5.7. Switched Capacitor Implementation. 97 6. CONCLUSIONS 0 6.. Multi-cell Delta-Sigma Modulators. 0 6.. Third order noise shaping structure. 03 6.3. Fourth order noise shaping structure 05 Bibliography 07 Appendices..08 Appendix. 09 Appendix. 6
LIST OF FIGURES Figure Page. Feedback loop for noise shaping... 5. Second-order modulator... 7.3 MASH architecture... 8 3. Multi-Cell Delta-Sigma Modulator... 0 3. -Cell Delta-Sigma Modulator... 3 3.3 -Cell DSM with the same circuit errors and thermal noise... 5 3.4 -Cell DSM with different circuit errors and thermal noise... 6 4. Split ADC architecture... 7 4. Cross-enhanced -cell ADC for third order noise shaping... 8 4.3 Cross-enhanced vs. unenhanced second-order ADC (ideal)... 4.4 Cross-enhanced -cell vs. unenhanced second-order ADC (non-ideal)... 3 4.5 Cross-enhanced -cell: alternative implementation... 4 4.6 Self-enhancement for third order noise shaping... 5
LIST OF FIGURES (Continued) Figure Page 4.7 Self-enhanced -cell vs. unenhanced second-order ADC (ideal)... 6 4.8 Self-enhanced -cell vs. unenhanced second-order ADC (non-ideal)... 8 4.9 Cross-enhanced -cell structure with gain mismatch... 9 4.0 Self-enhanced -cell structure... 34 4. Self-enhanced -cell vs. unenhanced second-order (ideal)... 35 4. Self-enhanced -cell vs. unenhanced second-order (non-ideal)... 37 4.3 SNR vs. amplitude of cross-enhanced & self-enhanced -cell (ideal)... 38 4.4 SNR vs. amplitude of cross-enhanced & self-enhanced -cell (non-ideal)... 4 4.5 SNR vs. amplitude of various ideal structures... 4 4.6 SNR vs. amplitude of various non-ideal structures... 44 4.7 SNDR vs. Opamp DC gain... 46 4.8 Cross-enhanced 4-cell DSM... 47 4.9 Self-enhanced 4-cell DSM... 48
LIST OF FIGURES (Continued) Figure Page 4.0 Cross-enhanced -cell with circuit errors and thermal noise... 49 4. Self-enhanced -cell with circuit errors and thermal noise..50 4. Self-enhanced -cell with ideal blocks... 5 4.3 Self-enhanced -cell with no circuit errors and with thermal noise... 5 4.4 Self-enhanced -cell with amplifier gain errors... 53 4.5 Self-enhanced -cell with coefficient errors... 54 4.6 Self-enhanced -cell with coupling gain errors... 55 4.7 Self-enhanced -cell with DAC errors... 56 4.8 Z domain block diagram for implementation... 57 4.9 Switched capacitor circuit diagram for second order DSM... 59 4.30 Switched capacitor circuit added for third order noise shaping... 60 4.3 Timing Diagram for the clock phases for third order noise shaping... 6 4.3 FFT of the simulation result from SWITCAP (ideal)... 6 5. Higher-order noise coupling structure... 63
LIST OF FIGURES (Continued) Figure Page 5. Cross-enhanced -cell structure. 65 5.3 Cross-enhanced -cell vs. unenhanced second-order (ideal)... 67 5.4 Cross-enhanced -cell vs. single-stage fourth order (ideal)... 68 5.5 Cross-enhanced -cell vs. unenhanced second-order ADC (non-ideal)... 70 5.6 Cross-enhanced -cell vs. Single-stage fourth order CIFF (non-ideal)... 73 5.7 Self-enhanced -cell structure... 74 5.8 Self-enhanced -cell vs. unenhanced second-order ADC (ideal)... 75 5.9 Self-enhanced -cell vs. unenhanced second-order ADC (non-ideal)... 77 5.0 Self-enhanced -cell vs. single-stage fourth-order CIFF (non-ideal)... 78 5. Alternative implementation: cross-enhanced -cell... 79 5. Self-enhanced -cell for fourth order noise shaping... 80 5.3 Self-enhanced -cell vs. unenhanced second-order (ideal)... 8 5.4 Self-enhanced -cell vs. unenhanced second-order (non-ideal)... 83 5.5 Self-enhanced -cell vs. single-stage CIFF structure (non-ideal)... 84
LIST OF FIGURES (Continued) Figure Page 5.6 SNR vs. amplitude of noise-coupled ADCs (ideal)... 89 5.7 SNR vs. amplitude of noise-coupled ADCs (non-ideal)... 9 5.8 SNR vs. amplitude of various ideal structures... 9 5.9 SNR vs. amplitude of various non-ideal structures... 95 5.0 SNDR vs. Opamp DC gain... 96 5. Z domain block diagram for implementation... 98 5. Switched capacitor circuit for fourth order noise shaping... 99 5.3 Timing Diagram of the clock phases for fourth order noise shaping... 00 5.4 Simulation result from SWITCAP for fourth-order noise shaping(ideal)... 0
LIST OF TABLES Table Page. Non-idealities included in -cell ADC... 4. Non-idealities in cross-enhanced -cell for third order noise shaping... 3. Non-idealities in self-enhanced -cell for third order noise shaping... 7 4. Cross-enhanced and self-enhanced -cell with gain mismatch... 33 5. Non-idealities in self-enhanced -cell for third order noise shaping... 36 6. Non-idealities in cross-enhanced and self-enhanced -cell structures... 39 7. Non-idealities in the third-order structures... 43 8. Finite opamp gain in third order noise shaping structures... 43 9. Non-idealities in cross-enhanced -cell for fourth order noise shaping... 69 0. Non-idealities in cross-enhanced -cell and single-stage structures...7. Non-idealities in self-enhanced -cell for fourth order noise shaping 76. Non-idealities in self-enhanced -cell for fourth order noise shaping 8
LIST OF TABLES (Continued) Table Page 3. Noise-coupled -cell ADCs with gain mismatch...88 4. Non-idealities in cross-enhanced and self-enhanced -cell structures... 90 5. Non-idealities in the fourth-order structures... 93 6. Finite opamp gain in fourth order noise shaping structures... 94
Noise Coupling Techniques in Multi-Cell Delta-Sigma Modulators. INTRODUCTION High resolution and high bandwidth are the requirements in many high-performance delta-sigma analog-to-digital converters. In order to increase the bandwidth of operation, the over-sampling ratio in a delta sigma modulator can be reduced, but this would result in lower resolution. In this thesis, a technique to achieve considerable improvement in the performance of lower order modulators with low OSR and hence enabling low power, high resolution implementations is discussed... Motivation Over-sampled delta sigma converters are effective in audio and other applications where low frequency and high resolution is important. But, in applications where high bandwidth is required, low OSR is needed but it would result in lower dynamic range. In order to solve the problem of low resolution, multi-bit quantization can be used to increase the signal to noise ratio (SNR) and to even improve the stability of the modulator. But this imposes a constraint on the linearity of the DAC as any nonlinearity in the DAC would degrade the performance. Conventional techniques like DEM can be used to remove the effect of the DAC nonlinearities but at low OSR DEM is ineffective. Another choice is to use a higher order modulator, but this would result in stability issues.
This thesis deals with two techniques to improve the resolution without increasing the order of the modulator. The two techniques are multi-cell delta sigma modulators and enhanced noise shaping... Contributions The four main contributions presented in this thesis are done on the concept proposed earlier in []. Extensive study and analysis of the structure proposed in [] for third order noise shaping using second-order delta sigma modulator. The different architectures have been studied for stability and sensitivity to opamp DC gain with non-idealities included. The structures are also compared to an unenhanced second-order CIFF structure, + MASH and a CIFF single- stage third-order structure. Simulation results are provided wherever possible. The concept of third order noise shaping by second-order modulator is extended to fourth order noise shaping using second-order modulator as in []. Extensive study is done on these structures for stability and sensitivity to opamp finite DC gain in comparison to an unenhanced second-order CIFF structure, + low-distortion MASH, a CIFF single-stage fourth-order structure. Simulation results are provided wherever possible. Switched capacitor implementations for third order noise shaping and fourth order noise shaping using second-order modulator are presented. These implementations prove that higher order noise shaping can be achieved without using extra opamps.
3.3. Thesis Organization In chapter, following this introduction, basics of over-sampled delta-sigma ADC, the concept of noise shaping, first-order and second-order noise shaping principles are explained in brief. MASH structure is also discussed in brief. Chapter 3 discusses multi-cell delta-sigma modulators, the performance improvement obtained for the same thermal noise and bias power consideration, and the cost of implementation involved. Chapter 4 describes the scheme for third order noise shaping proposed in [] and discusses the performance of the structure under ideal conditions and with nonidealities present. The third-order structure is compared with a few other third order noise shaping structures in terms of stability, sensitivity to opamp DC gain, simplicity and robustness of the structure. Switched capacitor implementation is proposed for the third order noise shaping structure and simulation results are provided. In Chapter 5, the scheme for fourth order noise shaping by second-order modulator as proposed in [] is discussed. Extensive simulations and analysis are done to illustrate the performance improvement obtained. Sensitivity to opamp non-idealities and stability are studied and compared with other fourth order noise shaping structures. Switched capacitor implementation of the fourth order noise shaping structure along with timing diagrams, and SWITCAP simulation results are provided. Finally, chapter 6 concludes the thesis and summarizes the benefits of the novel noise shaping structures discussed in chapters 4 and 5.
4. BASICS OF OVER-SAMPLED DELTA-SIGMA An analog to digital converter converts an analog input signal into the digital equivalent of the signal by quantizing the input signal amplitude to the nearest discrete signal level. The quantization error introduced in this process can be assumed to be white noise and that it has a uniform distribution between ±V LSB / provided the input signal varies rapidly. V LSB is the quantization step. Using this white noise assumption for quantization error, the quantization noise power is V LSB and the maximum SNR calculated using the quantization noise power is 6.0N+.76 db for an N-bit quantizer... Over-Sampled Data Converters Higher resolution can be obtained by over-sampling a signal which is band limited to f 0, by a sampling rate Fs which is much higher than the Nyquist rate. The quantization noise power is spread over a larger frequency range due to over sampling. The signals of interest remain within the band and the quantized signal is filtered to remove any quantization noise along with all other signals outside the band of interest. Due to this principle, the quantization noise power is reduced by the factor of OSR which is F S. The SNR is given by 6.0N +.76 + 0log0( OSR). It can be f 0 inferred from this equation that doubling the OSR gives an improvement of 3dB in SNR. In order to achieve required accuracy, say with a -bit A/D converter to attain 96dB SNR with f 0 of 5 khz, the sampling frequency required is 54000GHz which
5 is impractical. Hence, a method to achieve higher resolution with reasonable OSR is required... Over-Sampled Data Converters with Noise Shaping u H(z) q v [4] Figure.: Feedback loop for noise shaping The concept of noise shaping is explained intuitively using Figure. and also z domain equations can be written for the same. The Signal Transfer function (STF) and Noise Transfer function (NTF) of the system are H ( z) and + H ( z) + H ( z) respectively. By observing the two expressions, it is clear than in order to make the NTF equal to 0 in the band of interest, H(z) should have a very gain in the band of interest as poles of H(z) are zeroes of NTF(z). STF(z) is close to unity for high values of H(z). Due to the high pass transfer function for NTF(z), if the gain of the opamps is high in the band of interest, the quantization noise is pushed out due to the feedback loop action. The high frequency noise is removed with further filtering as it is not reduced due to insufficient gain of the opamps at high frequencies.
6.3. First Order Noise Shaping Z For first order noise shaping, H(z) in Figure. is chosen as. Hence, Z STF( Z) = Z NTF( Z) = Z By integrating the power spectral density of the quantization error, the in-band noise power can be calculated and hence the SNR resulting from that calculation is SNR = 6.0N +.76 5.7 + 30 log( OSR) max It can be observed from the equation that with doubling of OSR, the SNR improvement is 9dB..4. Second Order Noise Shaping The concept of noise shaping is extended to higher order. Figure. realizes a second-order noise shaping structure if the loop filter transfer functions are chosen in a correct way. If H( Z) = Z Z H ( Z) = Z STF( Z ) = Z NTF( Z) = ( Z ). By Linear analysis in Z domain,
7 u H (z) H (z) q v Figure.: Second-order modulator By integrating the power spectral density of the quantization error, the in-band noise power can be calculated and hence the SNR resulting from that calculation is SNR = 6.0N +.76.9 + 50log( OSR). It can be observed from the equation max that with doubling of OSR, the SNR improvement is 5 db. Noise shaping can be extended to higher order but higher order modulators face the problem of stability. MASH is introduced to avoid the stability problem in higher order modulators as each loop in a MASH is of a lower order but the performance obtained is of higher order. Each of the unit ADCs in the MASH is of lower order and order of for each unit, guarantees stability when multiples loops are cascaded. In this structure, the quantization error of the first stage is fed as input to the next stage and so on, and using digital error cancellation logic, the quantization error of all the stages except the last is cancelled. Figure.3 illustrates MASH architecture.
8 u ADC (STF, NTF ) v q ADC v (STF, NTF ) Digital Error Cancellation Logic v v n ADC n v n q n- (STF n, NTF n ) [4] Figure.3: MASH architecture The last stage quantization error is shaped by the transfer function which is the product of all the noise transfer functions NTF until NTF n. Hence the performance obtained is of n th order noise shaping structure.
9 3. MULTI-CELL DELTA-SIGMA MODULATORS In this chapter, multi-cell delta-sigma modulators are discussed in terms of the performance improvement obtained and the cost of implementation involved. This chapter introduces concepts which will prove useful in Chapters 4 and 5 for higher order noise shaping using split ADC of second order. 3.. Motivation The increasing need for robust and programmable ADCs for applications in which complete failure of the device is hazardous is the main reason for the introduction of multi-cell delta-sigma modulators. In applications like implanted pacemakers or defibrillators, in the case of a catastrophic failure of one or two units, the device still needs to be functional. Hence multi-cell delta sigma modulators with programmability prove useful in such scenarios. Even if one or few units fail, the device still works with decreased accuracy and when full accuracy is not required, a few units can be turned off. Hence a trade-off between accuracy and power dissipation is seen. 3.. Architecture The concept of multi-cell ADC and the cost of implementation are discussed in [3]. In multi-cell delta-sigma modulators, multiple unit ADCs are connected in parallel. The same input is applied to each unit ADC and the digital output codes from the unit
0 ADCs are averaged to generate the output of the ADC. The structure of a multi-cell ADC is shown in Figure 3.. v q u q M V v M- M- q M- v M M q M Figure 3.: Multi-Cell Delta-Sigma Modulator Due to the M unit ADCs in M-cell ADC, it would appear as if the power dissipation and chip area are increased compared to a single ADC. This is not true and is explained in [3]. The overhead involved in the implementation of a multi-cell ADC is very little. In order to meet a SNR requirement, say an N-bit ADC is designed for specific power, chip area and bandwidth requirements. The following equations can be written for the single N-bit ADC:
g ft = b C P = pg σ x m m kt = n C where f σ are the band-width, power dissipation and noise power of the T, P, x single ADC. The constants b, p, n are circuit parameters [3]. In M-cell ADC, when output codes are averaged, the thermal noise powers add as the square root of the sum of the thermal noise powers, whereas the signals add linearly. The resulting SNDR improvement due to thermal noise powers is 0log0(M). Hence for the same SNDR performance as that of a single ADC, the capacitance value in each unit ADC can be reduced by a factor of M. In order to keep the band-width of each unit ADC as f T, which is the bandwidth of the single ADC as mentioned earlier, g m of each unit ADC can be reduced by a factor of M. Hence the bias current and the device sizes in each unit ADC are reduced by a factor of M. For M unit cells, the total power and capacitance area remain the same. Due to reduction in the size of capacitance in each unit of the M-cell ADC by a factor of M, the thermal noise power in each unit increases by the factor M, but when thermal noise powers of the M units are averaged at the output of the M-cell ADC, the factor of M is cancelled. Hence, there is no change in the total thermal noise power. To summarize, the following equations can be written.
f P T s s g m = b M = f C M g m = Mp = P M T As shown in the equations, in each of the unit cells in M-cell ADC, the capacitance area is /M times the area of the capacitance in a single ADC. There will be a little overhead involved when a single ADC is split into M unit ADCs as M quantizers and M DACs are required. Hence, it can be concluded that for the same thermal noise and bias power, splitting is almost free. The resolution improvement in a M-cell implementation is due to stochastic nature of the quantization errors in the M unit ADCs. Statistical independence is assumed between the quantization errors of the unit ADCs. This assumption is valid, as inherent mismatches among the element values and thermal noise present in the unit ADCs help to de-correlate the quantization errors of the unit ADCs in M-cell ADC. The simulation results are provided in Section 3.3 to support the assumption. Due to the statistical independence of the quantization errors, when M output codes are averaged, M output signals add linearly, and the quantization noises from the M unit ADCs add as square root of the sum of the noise powers at the output. Due to this, the improvement in SNR of the overall output is 0logM db when compared to the SNR of single ADC without splitting for the same thermal noise and bias power. This improvement in SNR due to the uncorrelated quantization errors can be traded off for reduced number of quantizer levels in the unit ADCs of the M-cell ADC. Hence, trade off between power and accuracy can be obtained.
3 3.3. Simulation Conditions and results A -cell DSM shown in Figure 3. is used to illustrate the SNR improvement due to uncorrelated quantization noises from the unit ADCs. H and H are second order loop filters in the two halves of the split DSM. The non-idealities that are included in the simulation are listed in Table. q u H v v c DAC DAC u H v q Figure 3.: -Cell Delta-Sigma Modulator
4 Non-ideality Gain of st / nd integrator Value 70 db/65 db opamps (channel ) Gain of st / nd integrator 65 db/60 db opamps (channel ) Number of Levels in quantizer 9 DAC linearity Sampling capacitor at the 9 bits pf input of st integrator Coefficient errors 0.3% RMS Table : Non-idealities included in -cell ADC Figure 3.3 shows the simulated performance of the -cell ADC with the same circuit errors and thermal noise in the unit ADCs (by using same random noise generator). The SNDR performance is 78.9 db @ -3dBFS input. With different circuit errors and different thermal noise in the unit ADCs (by using different random noise generators) the SNDR performance, as shown in Figure 3.4 was 8.6 db. Hence this simulation illustrates the improvement in SNDR due to addition of uncorrelated quantization noise powers at the output.
5 0 [ SNDR multicell -units = 78.9 db ] -0 Power spectral densities(db) -40-60 -80-00 -0-40 -60 0-3 0-0 - Frequency, f / f s Figure 3.3: -Cell DSM with the same circuit errors and thermal noise
6 0 [ SNDR multicell -units = 8.6 db ] -0 Power spectral densities(db) -40-60 -80-00 -0-40 -60 0-3 0-0 - Frequency, f / f s Figure 3.4: -Cell DSM with different circuit errors and thermal noise
7 4. THIRD ORDER NOISE SHAPING In this chapter, extensive analysis was done on the structure proposed in [] for third order noise shaping. Switched capacitor implementation was also proposed for third order noise shaping structure in this chapter. Simulations were done to illustrate the robustness of the structure and performance was compared with other third order noise shaping structures in terms of stability and sensitivity to opamp DC gain variation. Split ADC was used to illustrate third order noise shaping with a second-order modulator using cross coupling of quantization errors. Figure 4. illustrates split ADC architecture. q u H v v c DAC DAC u H v v d q Figure 4.: Split ADC architecture
8 4.. Cross-enhanced -cell architecture The concept of split ADC was introduced in [3], and it uses a single ADC split into two symmetrical halves as shown in Figure 4.. The same signal u is applied as input to both the halves and output codes from each of the two halves V and V are added and averaged to generate the output V c of the ADC. The difference of the output codes from the two halves V d is used for background calibration [3]. The cost of implementation for a split ADC is almost as much as a single ADC and this is explained in chapter 3. In the new scheme proposed in [], split ADC architecture of second order was used along with the novel technique for third order noise shaping. u H v v c z - DAC DAC u H z - v v d Figure 4.: Cross-enhanced -cell ADC for third order noise shaping
9 As shown in Figure 4., the quantization error from each half of the split ADC is fed to the input of the quantizer in the other half with one full delay. H and H are second order loop filters. All the integrators used in the loop filters H and H are full delaying integrators. The quantization errors in the two halves and are assumed to be uncorrelated due to inherent mismatches and thermal noise of the two halves. Using linear model analysis, the following Z domain equations can be written. V V = U + NTF ( z ) = U + NTF ( z ) NTF, NTF are the noise transfer functions and, are the quantization errors of the two halves of the split ADC. The output of the ADC is V C = U + NTF ( z ) ( + ) NTF = NTF = NTF is assumed. It can be inferred from this derivation that if a second order modulator is used as the unit ADC, with cross coupling of quantization noises, the final output of the ADC will be third order noise shaped. For the same thermal noise and bias power, 3dB improvement in SNR was also seen due to the addition of uncorrelated quantization errors at the output of the cross-enhanced -cell ADC. The additional improvement in resolution can be traded off with power by reducing the number of quantizer levels in each half of the split ADC.
0 4... Simulation with ideal blocks MATLAB and SIMULINK were used for system level modeling and simulation. The following conditions were used in most of the simulations unless otherwise specified. Input signal amplitude : -3dBFS OSR : 3 Levels in quantizer : 9 Band-width : khz. Order of unit ADC : All the simulation results were plotted for the new noise shaping structure along with an unenhanced second-order wideband low-distortion ADC [4]. The comparison was done with unenhanced second-order ADC as the new structure was derived by addition of a delay block for third order noise shaping in the second-order structure. Figure 4.3 shows performance improvement of 4.6 db in a cross-enhanced -cell ADC when compared to a second-order ADC.
[ SNDR unenhanced second-order = 79. db, SNDR cross-enhanced -cell = 93.8 db] 0 Power spectral densities(db) -50-00 -50-00 -50 unenhanced second-order cross-enhanced -cell 0-3 0-0 - Frequency, f / f s Figure 4.3: Cross-enhanced vs. unenhanced second-order ADC (ideal) 4... Simulation with non-idealities included Table lists the non-idealities included in the unenhanced second-order and cross-enhanced -cell ADCs.
Non-ideality Unenhanced second-order Cross-enhanced -cell Gain of st / nd integrator 65 db/65 db 70 db/65 db opamps (channel ) Gain of st / nd integrator 65 db/60 db opamps (channel ) Number of Levels in quantizer 9 9 Coupling gain error g = 0.95, g = 0.9 DAC linearity 9 bits 9 bits Sampling capacitor at the pf pf input of st integrator Coefficient errors 0.3% RMS 0.3% RMS Table : Non-idealities in cross-enhanced -cell for third order noise shaping In Table, g and g refer to the gains of injected quantization errors in the two halves of the cross-enhanced -cell structure. Thermal noise included in the two halves is different (different random noise generators were used in SIMULINK model) so that the quantization errors of the two halves are decorrelated. When cross-coupling was used in the split -cell structure (with same thermal noise and bias power as that of a single-stage second-order ADC), the SNDR improvement was about 9. db due to cross-coupling and 3 db due to addition of uncorrelated quantization noises in the
3 two halves. The total improvement in SNDR performance was. db as shown in Figure 4.4. [ SNDR unenhanced second-order = 79.0 db, SNDR cross-enhanced -cell = 9. db] 0-0 Power spectral densities(db) -40-60 -80-00 -0-40 -60 unenhanced second-order cross-enhanced -cell 0-3 0-0 - Frequency, f / f s Figure 4.4: Cross-enhanced -cell vs. unenhanced second-order ADC (non-ideal) 4..3. Alternative implementations There are various kinds of alternative implementations possible for third order noise shaping, and all of them are equivalent to the structure in Figure 4. in terms of simulated performance. Instead of feeding the quantization error of one half of the
4 split ADC to the input of the quantizer in the other half, it can be fed to the input of the second integrator in the other half. Figure 4.5 illustrates the block diagram for this modified structure. H and H are delaying integrators. q u H z z w z DAC v v c DAC u H z z w z v v d q Figure 4.5: Cross-enhanced -cell: alternative implementation The simulated performance of this structure was similar to that of structure in Figure 4.. It was observed that this structure cannot be implemented with just two opamps and might require an additional opamp for enhanced noise shaping which makes this structure unattractive for further analysis. Hence, this structure was not used in further sections.
5 4.. Self-enhanced -cell architecture Another possible implementation for third order noise shaping is shown in Figure 4.6. In this structure, instead of feeding the quantization error of one half of the split ADC to the input of the quantizer in the other half, it can be fed to the input of the quantizer in the same loop, which will be referred in this thesis as self-enhanced -cell implementation. q u H v v c z - DAC DAC u H z - v v d q Figure 4.6: Self-enhancement for third order noise shaping Using self-enhanced architecture in a -cell ADC, the performance was similar to that of cross-enhanced -cell when ideal blocks are used as shown in figure 4.7.
6 4... Simulation with ideal blocks [ SNDR unenhanced second-order = 79. db, SNDR self-enhanced -cell = 93.8 db] 0 Power spectral densities(db) -50-00 -50-00 -50 unenhanced second-order self-enhanced -cell 0-3 0-0 - Frequency, f / f s Figure 4.7: Self-enhanced -cell vs. unenhanced second-order ADC (ideal) 4... Simulation with non-idealities included structure. The non-idealities listed in Table 3 are included in self-enhanced -cell
7 Non-ideality Unenhanced second-order Self-enhanced -cell Gain of st / nd integrator 65 db/65 db 70 db/65 db opamps (channel ) Gain of st / nd integrator 65 db/60 db opamps (channel ) Number of Levels in quantizer 9 9 Coupling gain error g = 0.95, g = 0.9 DAC linearity 9 bits 9 bits Sampling capacitor at the input of st integrator pf pf Table 3: Non-idealities in self-enhanced -cell for third order noise shaping The SNDR improvement in self-enhanced -cell structure over an unenhanced second order structure was about. db and Figure 4.8 shows the performance.
8 [ SNDR unenhanced second-order = 79.0 db, SNDR self-enhanced -cell = 9. db] 0-0 Power spectral densities(db) -40-60 -80-00 -0-40 -60 unenhanced second-order self-enhanced -cell 0-3 0-0 - Frequency, f / f s Figure 4.8: Self-enhanced -cell vs. unenhanced second-order ADC (non-ideal)
9 4.3. uantization error injection mismatch u H v v c g z - DAC DAC u H g z - v v d Figure 4.9: Cross-enhanced -cell structure with gain mismatch The quantization error from one loop is fed to the input of the quantizer in the other loop with a delay and a gain of in ideal conditions. Any mismatch in the gain of the injected quantization error will change the location of the NTF zeroes and hence the effect of such mismatches is studied in this section. Let g and g be the gains of the injected quantization errors in the two halves of the cross-enhanced -cell structure as shown in Figure 4.9. Linear model analysis using Z domain equations is shown in sections 4.3. and 4.3..
30 4.3.. uantization injection error in cross-enhanced -cell assuming, ;, N N N N N N = + = By substituting for N and N, and neglecting the terms N Z N Z N Z N Z,,, as they are second-order small, the following equation is derived. The error in the quantization noise in the output of the ADC V c, is given by ] ) ( [ ] ) ( [,, ) ( ) ( ) ( ) ( ) ( N Z N Z NOUT N NTF N NTF g g assume NTF Z g NTF Z g u u V V NTF Z g u V NTF Z g u V + + + = = = + = + = + + + = + + = + = ) )( ( ) ]( [ + + + = Z N N Z NOUT ) )( ( + Z N
3 Substituting for N, the error in the quantization noise at the output is ) )( )( ( 4 + Z N N. At low frequencies, it is ) )( ( N N. Hence, the extra RMS noise is rms N N. 4.3.. uantization injection error in self-enhanced -cell assuming, ;, N N N N N N = + = By substituting for N and N, and neglecting the terms N Z N Z N Z N Z,,, as they are second-order small, the following equation is derived. ] ) ( [ ] ) ( [,, ) ( ) ( ) ( ) ( ) ( N Z N Z NOUT N NTF N NTF g g assume NTF Z g NTF Z g u u V V NTF Z g u V NTF Z g u V + + + = = = + = + = + + + = + + = + =
3 NOUT = [ + ]( Z ) N + N ( )( Z ) The error in the quantization noise in the over all output of the ADC V c is N ( )( Z ) Substituting for N, the error in the quantization noise at the output is ( N N )( )( Z ). 4 At low frequencies, it is zero. Hence it can be concluded from the linear model analysis that self-enhanced -cell structure is better in performance than a crossenhanced -cell structure when mismatch is present in quantization error injection. 4.3.3. Simulations with quantization injection error mismatch The cross-enhanced -cell and self-enhanced -cell structures were simulated with mismatch in quantization error injection, and the SNDR degradation was not more than 3 db even with mismatch up to 0 percent. The simulation results prove that the two structures are quite robust and insensitive to mismatch in quantization error injection.
33 g g SNDR(dB) Cross-enhanced -cell SNDR(dB) Self-enhanced -cell 90. 9. 0.99.0 89.5 90 0.98.0 90. 90. 0.97.03 90.4 89.7 0.95.05 89.3 89.4 0.9. 90. 89.6 0.85.5 89.3 89.4 0.8. 88.4 87.8. 0.9 89.4 89.7 0.8 88. 89. 0.95 0.9 90.6 89.4 Table 4: Cross-enhanced and self-enhanced -cell with gain mismatch From the simulation results listed in Table 4, it can be seen that both the structures show similar performance under mismatch in quantization error injection. The simulation results are not in agreement with the conclusion made in linear model analysis that self-enhanced -cell is better than cross-enhanced -cell structure.
34 4.4. Self-enhanced -cell architecture The self-enhancement noise shaping technique can be implemented with just single loop instead of split -cell architecture as shown in Figure 4.0. In this structure, the quantization error of the loop is fed to the input of the quantizer in the same loop. Third order noise shaping can be obtained by using two opamps instead of three. Due to single loop, SNR improvement that is seen in a -cell structure cannot be seen and this is expected. The thermal noise and bias powers remain the same as in a selfenhanced -cell structure and there is no need for two quantizers and two DACs. u H q v z - DAC Figure 4.0: Self-enhanced -cell structure The performance when simulated with ideal blocks is expected to be same as ideal self-enhanced -cell structure, however in a non-ideal simulation, self-enhanced -cell should show 3 db better performance than self-enhanced -cell due to the noncorrelation of quantization errors when thermal noise and mismatches are introduced.
35 4.4.. Simulation with ideal blocks [ SNDR unenhanced second-order = 79. db, SNDR self-enhanced -cell = 93.8 db] 0-0 P ower spectral densities(db) -40-60 -80-00 -0-40 -60 unenhanced second-order self-enhanced -cell 0-3 0-0 - Frequency, f / f s Figure 4.: Self-enhanced -cell vs. unenhanced second-order (ideal) The SNDR improvement is 4.6dB when compared to a second order structure and the performance is similar to a self-enhanced -cell ideal structure as expected.
36 4.4.. Simulation with non-idealities included structure. The non-idealities listed in Table 5 are included in self-enhanced -cell Non-ideality Unenhanced Self-enhanced Gain of st / nd second-order -cell 65 db/65 db 65dB/65 db integrator opamps Number of Levels in quantizer 9 9 DAC linearity 9 bits 9 bits Sampling capacitor at the input of st integrator pf pf Coefficient errors 0.3% RMS 0.3% RMS Table 5: Non-idealities in self-enhanced -cell for third order noise shaping Figure 4. illustrates the simulated performance.
37 [ SNDR unenhanced second-order = 79.0 db, SNDR self-enhanced -cell = 89.7 db] 0-0 Power spectral densities(db) -40-60 -80-00 -0-40 -60 unenhanced second-order self-enhanced -cell 0-3 0-0 - Frequency, f / f s Figure 4.: Self-enhanced -cell vs. unenhanced second-order (non-ideal) 4.5. Performance Comparison The performance of the cross-enhanced -cell and self-enhanced -cell structures was next compared to single-stage third-order structure, conventional + MASH ADC and a low distortion + MASH ADC as they all provide third order noise shaping. Performance comparison was also done with an unenhanced second-order structure as the novel structures were derived from this structure.
38 Stability of the new structures and sensitivity to opamp DC gain are studied in further sections. 4.5.. Stability Analysis Ideal self-enhanced -cell and cross-enhanced -cell structures were compared for stability by plotting the SNR for both structures when the amplitude of the input signal was swept from 50 db to 0dB. 00 Ideal cross-coupled and self-coupled -cell 80 60 SNR[dB] 40 0 0-0 cross-enhanced -cell self-enhanced -cell -40-50 -40-30 -0-0 0 AMPLITUDE [dbfs] Figure 4.3: SNR vs. amplitude of cross-enhanced & self-enhanced -cell (ideal)
39 No difference is seen in the performance as both the structures are identical under ideal conditions. The non-idealities listed in Table 6 were included in crossenhanced and self-enhanced -cell structures and the performance was simulated. Non-ideality Cross-enhanced -cell Self-enhanced -cell Gain of st / nd integrator opamps (channel ) Gain of st / nd integrator opamps (channel ) Number of Levels in quantizer 70 db/65 db 70 db/65 db 65 db/60 db 65 db/60 db 9 9 Coupling gain error g = 0.95, g = 0.9 g = 0.95, g = 0.9 DAC linearity 9 bits 9 bits Sampling capacitor at the pf pf input of st integrator Coefficient errors 0.3% RMS 0.3% RMS Table 6: Non-idealities in cross-enhanced and self-enhanced -cell structures Just after powering up, the two halves in cross-enhanced -cell structure will be identical. But after a few clock periods, the quantization noises in the two halves become uncorrelated and hence the quantization error that is fed from one half to the input of the quantizer in the other half acts as a dither and is uncorrelated with the quantization error in the other half. This non-correlation between the quantization errors of the two halves is proved by simulation and is shown in section 4.7.
40 In a self-enhanced -cell structure, since the quantization error in one half is fed to the input of the quantizer in the same half, the signal that is being fed could be more correlated to the quantization error of the same loop and hence could result in instability as time progresses in the simulation although, the delay block that was introduced for third order noise shaping is expected to provide de-correlation between the quantization error of the loop and the quantization error that is being injected for extra order of noise shaping. The simulation results are shown in Figure 4.4. It can be observed that the cross-enhanced -cell structure is stable up to -dbfs whereas self-enhanced -cell is stable till -dbfs and the SNDR drops at a faster rate for input amplitudes closer to -.5 dbfs in the self-enhanced -cell structure. The cross-enhanced -cell structure shows minimum deterioration in the performance even at amplitudes larger than - dbfs. This shows that the cross-enhanced -cell structure is a little better in terms of stability than a self-enhanced -cell structure as expected.
4 0 00 Non-ideal Structures self-enhanced -cell cross-enhanced -cell 80 SNR[dB] 60 40 0 0-50 -40-30 -0-0 0 Amplitude [dbfs] Figure 4.4: SNR vs. amplitude of cross-enhanced & self-enhanced -cell (non-ideal) The stability of two noise-coupled structures was compared with the stability of other third order noise shaping structures. Single-stage third-order ADC used in this study was a feed forward structure with an ideal SNDR performance of 98.5dB @ - 4dBFS. This structure was unstable for amplitudes beyond -4dBFS. Low distortion + MASH ADC was designed with low-distortion feed-forward structure in both the stages. Inter-stage gain of 4 was used. The performance obtained under ideal conditions was 4.5dB @ -0.5dBFS. Conventional - MASH was designed with a stable range up to -dbfs and the performance obtained was.9db @ -dbfs. Low distortion wide band topology for second order noise shaping under ideal conditions gives SNDR of 80 db and the structure was stable up to -dbfs. All the
4 structures that are used in this comparison study were designed with emphasis on an optimized structure. 0 Ideal Structures 00 80 SNR[dB] 60 40 cross-enhanced second-order self-enhanced second-order 0 single-stage second-order conventional - mash 0 low distortion - mash single-stage third-order -50-40 -30-0 -0 0 Amplitude [dbfs] Figure 4.5: SNR vs. amplitude of various ideal structures Figure 4.5 shows the performance of all the third order noise shaping structures under ideal conditions. From the plot, it can be observed that low distortion + MASH ADC and single-stage second-order structure are stable up to a wide range of amplitudes. The single stage third order loop s performance degrades around -4dBFS as the order of the modulator is high. Self-enhanced -cell and cross-enhanced -cell structure show stability range similar to an unenhanced second-order structure. Hence, it can be concluded that the two novel third order noise enhancement structures are
43 more stable than a single stage third order structure. All the third order noise shaping structures were studied with non-idealities shown in Table 7 and Table 8. Non-ideality Value Number of Levels in quantizer 9 Coupling gain error g = 0.95, g = 0.9 DAC linearity Sampling capacitor at the input of st integrator Coefficient errors 9 bits pf 0.3% RMS Table 7: Non-idealities in the third-order structures Finite opamp gain (db) Channel (db) Channel (db) Unenhanced second-order, Self enhanced -cell, Single-stage third-order, 65 (for all opamps) Conventional / Low-distortion + MASH ADCs Cross-enhanced / Selfenhanced -cell ADCs 70/65 65 /60 Table 8: Finite opamp gain in third order noise shaping structures
44 Table 7 lists all the non-idealities included in all the third order noise shaping structures except for finite opamp gain. Table 8 lists the finite opamp gain details and Figure 4.6 shows the simulation result. 0 Non-ideal Structures 00 80 SNR[dB] 60 40 0 0 unenhanced second-order single-stage third-order self-enhanced -cell self-enhanced -cell cross-enhanced -cell conventional - mash low distortion - mash -50-40 -30-0 -0 0 Amplitude [dbfs] Figure 4.6: SNR vs. amplitude of various non-ideal structures Single stage second order structure was very robust and when non-idealities were present, the performance did not degrade much. Single stage third order performance also was not affected much with non-idealities. Cross-enhanced and selfenhanced -cell structures exhibit similar performance as a single stage of third order. Conventional + MASH ADC was quite sensitive to non-idealities in the loop and showed degraded performance. Low distortion + MASH ADC performance was