High-Speed Serial Iterface Circuit ad Sytem Lect. 4 Phae-Locked Loop (PLL) Type 1 (Chap. 8 i Razavi)
PLL Phae lockig loop A (egative-feedback) cotrol ytem that geerate a output igal whoe phae (ad frequecy) i related to the phae (ad frequecy) of a iput referece igal wikipedia Applicatio Frequecy Sythei - Clock for digital ytem - LO i RF ytem Clock recovery Modulatio/Demodulato
PLL Buildig Block Referece Phae Detector Loop Filter Voltage Cotrolled Ocillator Output Diviio by M Output igal i phae-locked to referece igal: Cotat phae relatiohip f out = M x f Referece
PLL Block Diagram Referece Phae Detector Loop Filter Voltage Cotrolled Ocillator Output Diviio by M Referece?
Phae-trackig by PLL Ditace time Camerama ca oly cotrol the accelerator (velocity) Ditace: Itegral of velocity Cotrol of velocity i order to lock the ditace After lockig, ditace ad velocity hould be the ame
Phae-trackig by PLL Referece Phae Detector Loop Filter Voltage Cotrolled Ocillator Output Abolute phae Diviio by M time PLL achieve phae-lockig by chagig VCO frequecy
Baic PLL Operatio PD (Phae Detector): Compare phae of iput ad output igal ad covert the phae differece to voltage igal LPF (Low Pa Filter): Take a average level of PD output voltage igal PD ca be realized with a multiplier i( t)i( t ) i out 1 co[( i out ) ] co[( i out ) ] t t
Baic PLL Operatio i( t)i( t ) i out 1 co[( i out ) ] co[( i out ) ] t t Aumig i = out Approximately liear for = - / Filtered out by LPF
Baic PLL Operatio VCO (Voltage Cotrolled Ocillator): Frequecy-tuable ocillator Output frequecy i a fuctio of cotrol voltage (V C )
Baic PLL Operatio Phae trackig of PLL ω i =ω out Iitially, V out i locked to V i With Phae jump i V i here V i V out V PD
Baic PLL Operatio Frequecy trackig of PLL ω i ω out V out i locked to V i With Frequecy jump i V i here V i V out V PD
Baic PLL Operatio XOR gate ca be ued a PD for digital igal A B V PD A B V PD Locked (π/ phae offet) A B V PD A 0 0 0 B B later tha A 0 1 1 V PD 1 0 1 1 1 0 A B B earlier tha A V PD
Baic PLL Operatio Phae trackig of PLL ω i =ω out V out i locked to V i (π/ phae offet) Phae jump i V i here V i V out V PD DC level V C
Frequecy trackig of PLL ω i ω out Baic PLL Operatio V out i locked to V i Frequecy jump i V i here V i V out V PD
Frequecy Sythei with PLL
Frequecy Demodulatio with PLL (FM igal) (PLL output) (Recovered meage)
PLL Dyamic: Liear Model Liear approximatio for PD characteritic LPF: Firt order with pole at = - p V PD T( ) V V C PD ( ) ( ) p p i out ) V PD () = K PD x ()
PLL Dyamic: Liear Model For implicity let 0 =0 Sice d/dt = out () = (1/) K VCO x V C ()
PLL Dyamic: Liear Model PLL Block Diagram Liear Model for out () / i () PD LPF VCO
PLL Dyamic: Liear Model Ope loop gai: G () K K PD VCO p ( ) p H() Cloed loop gai K p PD VCO out () G () ( p ) i() 1 G ( ) p 1 KPDKVCO ( p ) K K K PD VCO p K K p PD VCO p d order LPF!
PLL Dyamic: Liear Model H() () K K out PD VCO p i() pkpdkvco p H out () i Note that iput ad output are phae (Aumig two real pole)
Magitude Repoe v Phae Repoe I LPF, H V V () out i LPF
Magitude Repoe v Phae Repoe I PLL, PD LPF VCO Vi Vout H out () i t t Vi Vout t PLL t Vi Vout t t
Secod-Order Sytem H() () K K out PD VCO p i() pkpdkvco p PD LPF VCO d order ytem H( ) ( / Q) H( ) PD VCO KPDKVCOP Q P K K 1 1 P Q K K PD VCO Where are the pole? > 1: Over damped 1: Uder damped 1: Critically damped
Secod-Order Sytem H() () out i() PD LPF VCO Frequecy Repoe Maximally flat coditio? d order Butterworth filter 1 ω = π ξ = 0.1 ξ = 0.3 ξ = 0.7 ξ = 1 ξ = 1.5
Secod-Order Sytem H() () out i () PD LPF VCO out () () i out () () i Step repoe: i() t u () t exp t PLL
() out i() Secod-Order Sytem Step repoe: i() t u () t PD LPF VCO ω = π ξ = 0.1 ξ = 0.3 ξ = 0.7 ξ = 1 ξ = 1.5
Secod-Order Sytem PD LPF VCO H() () out i() - Trafer fuctio for phae error? H () e 1 H ( ) - Phae error due to phae tep? i() t u () t () i e( t ) lim He( ) 0 - No teady-tate phae error
Secod-Order Sytem PD LPF VCO H() () out i() H e () - Phae error due to frequecy tep? i() t u () t i() () i ( t ) e lim He( ) 0 K K PD VCO