International Journal of Eletronis and Computer Siene Engineering 817 Available Online at www.ijese.org ISSN- 2277-1956 A Duly Synhronized, Straightforward Approah For Realizing the General Charateristis of JK Flip Flop and Master Slave JK Flip Flop in terms of Charateristi Equation of Cloked SR Lath Madhu Sudan Chakraborty 1, Sandip Kumar Sao 2 1 2 Department of Computer Siene 1 Asst. Professor, Indas Mahavidyalaya, P.O.- Indas, Dist.- Bankura, PIN-722205 2 Leturer, J. K. College, P.O. & Dist.- Purulia, PIN- 723101 E-mail: 1 e_madhus@rediffmail.om 2 mail2prlsandip@gmail.om Abstrat In this paper we propose a duly synhronized, straightforward approah for realizing the general harateristis of JK flip flop and master slave JK flip flop in terms of the harateristi equation of loked SR lath. Although, in this onnetion, the traditional approah requires exerising all possible external input ombinations one by one on onerned logi diagrams until aquiring stable states; the proposed approah does not require the same. Also, it duly treats loked SR lath as the basi 1 bit ell of stati RAM. The proposed approah is more effiient than the traditional approah, not only as a tool of analysis and design of omplex sequential iruits; but also as a tool of teahing. Keywords Duly synhronized, Straightforward approah, JK flip flop, Master Slave JK flip flop, SR lath, Stable State, Stati RAM, Complex sequential iruit I. INTRODUCTION Sequential iruit is an important hapter of digital fundamentals, whih is overed as a full paper or a part of some paper at under graduate level ourses in physis, eletronis, omputer siene, eletrial engineering and all related branhes of siene and engineering. As per study materials, students must learn lath first, then flip flop and at last master slave flip flop. In ommon textbooks the harateristis of different lathes and flip flops are firstly explained on the basis of exerising all possible external input ombinations one by one on onerned logi diagrams until aquiring stable states. For realizing ordinary JK flip flop and master slave JK flip flop the logi diagrams are given either in terms of loked SR lathes/ flip flop(s) with logi gates for feedbak onnetion [1], [2], [3], [4], [5], [6], [7], [8], [9] or simply at the gate level [10], [11], [12], [13] and only thereafter their harateristi equations an be represented. In this onnetion, we identify some problems in the traditional approah as presented in the said books: When the logi diagram of ordinary JK flip flop or master slave JK flip flop is given in terms of loked SR lath(s), we need to exerise all possible external input ombinations one by one with referene to the harateristi table of loked SR lath, though, the general harateristi of loked SR lath is known as a single harateristi equation and may be useful in this ontext. Alternatively, when the logi diagram of ordinary JK flip flop or master slave JK flip flop is given in terms of ordinary logi gates, it even does not omply with the fat that loked SR lath is the basi 1 bit ell of stati RAM. Thus, the traditional method not only seems to be ineffiient for analysis and design of omplex sequential iruits, it is also observed that this type of problems make traditional teahing approah ineffiient, beause, in information tehnology most knowledge has ertain relationship with others [14]. For resolving the said problems, in aordane with a method speified in [3], in this paper we attempt to establish the general harateristis of an ordinary JK flip flop and master slave JK flip flop in terms of harateristi equation of loked SR lath in a duly synhronized, straightforward manner. ISSN 2277-1956/V2N2-0817-822
A Duly Synhronized, Straightforward Approah For Realizing the General Charateristis of JK Flip Flop and Master Slave JK Flip Flop in terms of Charateristi Equation of Cloked SR Lath II. PROPOSED APPROACH A. Realizing General Charateristi of JK Flip Flop in terms of Charateristi Equation of Cloked SR Lath: JK flip flop, as shown in figure 1, is a refinement of loked SR lath in whih all external input ombinations are allowed i.e. the indeterminate state of SR type is defined in the JK type. Here, PT denotes the transition on positive edge of the lok pulse. In onnetion to speifying the harateristi of JK flip flop, we reall the funtioning of an SR lath. When there is no lok pulse (CP), the lath remains in store mode. When the lok pulse arrives at time t n, the external inputs R n and S n of the n th interval are applied to the lath with urrent state Q n. After the pulse is gone, the (n+1) th interval starts with state Q n+1. Aordingly, the harateristi equation of loked SR lath is given by: Q n+1 = S n + R n. Q n, provided that R n. S n = 0 (1) Equation (1) also holds for SR flip flop, although, flip flop is edge triggered, whereas, lath is level sensitive. For realizing the general harateristi, inter interval feedbak relationship in JK flip flop is shown in figure 2, where, the dashed line is used to relate inputs and states of the flip flop in two onseutive intervals. As shown in figure 2, during n th interval, the external inputs to the internal SR flip flop are denoted as: R n, and S n. Sine the state of RS flip flop after (n 1) th interval i.e. Q n appears as an input to the same flip flop during n th interval, the inputs to the internal SR flip flop are given by: R n = K n. Q n. PT, S n = J n. Q n. PT.. (2) So, using equation (1) and (2) harateristi equation of a JK flip flop is given by: Q n+1 = J n. Q n. PT + (K n + Q n + PT ). Q n = J n. Q n. PT + (K + PT ) Q n.. (3) Also note that, now, R n S n = (K n.j n ). (Q n Q n ). PT = 0, holds impliitly in JK flip flop and so there is no need to assign the ondition expliitly. Further, it means that all possible external input ombinations are allowed in JK flip flop. n
IJECSE, Volume 2,Number 2 Madhu Sudan Chakraborty and Sandip Kumar Sao 819 From equation (3) we get that the general harateristi of positive edge triggered JK flip flop as: J n. Q n + K n Q n, on the positive edge of the lok pulse Q n+1 =.. (4) Q n, otherwise The state of JK flip flop is initialized by applying asynhronous input CLEAR (or PRESET and CLEAR). B. Realizing General Charateristi of Master Slave JK Flip Flop in terms of Charateristi Equation of Cloked SR Lath : A master slave flip flop is onstruted from two separate lathes, onneted in asade. One lath serves as master and the other as slave and the overall iruit is referred to as a master slave flip flop. As shown in the figure 3, in a negative edge triggered master slave FF, the master is set aording to the external inputs when the lok is high; the ontents of the master are then shifted into the slave when the lok goes low. The objetive is to break the feedbak loop and reating a delay so that the output hanges only one per lok yle. In some textbooks the logi iruit diagram of master slave JK flip flop is shown as in figure 3 (or almost the same) and in some other textbooks using the ordinary logi gates only. But, in this paper we are not interested to sequential logi iruits ompletely based on ordinary logi gates, beause, it does not omply with the fat that SR lath is the basi 1 bit ell of stati RAM.
A Duly Synhronized, Straightforward Approah For Realizing the General Charateristis of JK Flip Flop and Master Slave JK Flip Flop in terms of Charateristi Equation of Cloked SR Lath The output of the master at the end of positive lok pulse ats as the input to the slave during the next negative lok pulse, following the negative edge transition. During negative lok pulse the master is inative and the slave is ative. The output of slave at the end of negative lok pulse ats as the input to the master during the next positive lok pulse, following the positive edge transition. For realizing the general harateristi inter interval feedbak relationship between master and slave is shown in figure 4, where, the dashed line is used to relate the inputs and states of master and slave in onseutive intervals. As shown in figure 4, during n th interval, the inputs to the master and slave are denoted as: MR n, MS n and SR n, SS n respetively. Also, during nth interval, the state of the master and slave are denoted as: MQ n and SQ n respetively. Sine the state of the slave lath after (n 1) th interval i.e. SQ n appears as an input to the master lath during nth interval, for the master, we have: MR n = K n. SQ n. CP, MS n = J n. SQ n. CP, where, CP denotes the lok pulse. (5) Obviously, using equation (1) and (5) the harateristi equation of the master is given by: MQ n+1 = J n. SQ n. CP + (K n + SQ n + CP ). MQ n (6) Also, note that, now, MR n MS n = (K n.j n ). (SQ n SQ n ). CP = 0, holds impliitly in master and so there is no need to assign the ondition expliitly. Further, it means that all possible external input ombinations are allowed in master slave JK flip flop. Sine, the state of the master after nth interval i.e. MQ n+1 appear as an input to the slave during nth interval, for the slave, we have: SR n = MQ n+1. CP, SS n = MQ n+1. CP.... (7) Obviously, using equation (1) and (7) the harateristi equation of the slave is given by: SQ n+1 = MQ n+1. CP + (MQ n+1 + CP) SQ n (8) Also, note that, now, SR n. SS n = MQ n+1. MQ n+1. CP = 0, holds impliitly in slave and so there is no need to assign the ondition expliitly. From equation (6) we get, J n. SQ n + (K n + SQ n ) MQ n, when CP = 1 MQ n+1 =. (9) MQ n, when CP = 0 Also, from equation (8) we get, SQ n, when CP = 1 SQ n+1 = (10) MQ n+1, when CP = 0 Sine, the master is ative when CP = 1 and the slave is ative when CP = 0, equation (10) implies that the state of the slave after (n 1) th interval is same as the state of the master after (n 1) th interval and aordingly we have: SQ n = MQ n. (11) Then, the relation (9) an be re written as: J n. MQ n + K n.mq n, when CP = 1 MQ n+1 =.. (12) MQ n, when CP = 0 This shows that the master ats as ordinary JK flip flop when CP = 1. Now, using equation (10) and (12) we an onlude that in the logi iruit diagram shown in figure 3 the master slave priniple is followed. Master Slave JK flip flop is initialized by applying asynhronous inputs CLEAR (or PRESET and CLEAR) to both master and slave simultaneously. 5
IJECSE, Volume 2,Number 2 Madhu Sudan Chakraborty and Sandip Kumar Sao 821 III. COMPARATIVE STUDY On the basis of omparative study of traditional approah and proposed approah as below, using figure 5.1 and figure 5.2, it is established that the proposed approah is superior to the traditional approah.
A Duly Synhronized, Straightforward Approah For Realizing the General Charateristis of JK Flip Flop and Master Slave JK Flip Flop in terms of Charateristi Equation of Cloked SR Lath IV. CONCLUSION In this paper it is shown that we an diretly establish the general harateristis of ordinary JK flip flop and master slave JK flip flop in a synhronized manner using only the harateristi equation of loked SR lath, omplying with the fat that loked SR lath is the basi 1 bit ell of stati RAM. The approah presented in this paper is suh that there is no more need to exerise all possible external input ombinations to realize the general harateristis of suh omplex iruits. Obviously, the approah presented in this paper an be used to analyze and design omplex sequential iruits more effiiently and also it is appropriate for inluding in the digital logi paper (or part) at the under graduate level ourses onerned. V. REFERENCE [1] E. Lipiansky, Eletrial, Eletronis and Digital Hardware Essentials for Sientists and Engineers, Ebook, First ed., John Wiley and Sons, 2012. [2] K. A. Krishnamurthy and M. R. Raghuveer, Eletrial, Eletronis and Computer Engineering for Sientist and Engineers, Seond ed., New Age International, 2011. [3] D. P. Leah, A. P. Malvino and G. Saha, Digital Priniples and Appliations, SIE, Seventh ed., MgGraw- Hill, pp 293-296, 2010. [4] S. P. Dandamudi, Fundamentals of Computer Organization and Design, Sixth Indian Reprint, First ed., Springer (India), 2009. [5] L. L. Kinney and J. D. Roth, Fundamentals of Logi Design, Sixth, Ed., CL Engineering, 2009. [6] M. J. Murdoa and V. P. Heuring, Computer Arhiteture and Organization: An Integrated Appraoh, First ed., John Wiley and Sons, 2007. [7] J. F. Wakerly, Digital Design: Priniples and Praties, Fourth ed., Prentie Hall, 2005. [8] D. A. Hodges, H. G. Jakson and R. Saleh, Analysis and Design of Digital Integrated Ciruits, Third ed., MGraw Hill, 2003. [9] D. C. Green, Digital Eletronis, Fifth ed., Pearson, 1998. [10] M. Morris Mano and C. R. Kime, Logi and Computer design Fundamentals, Fourth ed., Prentie Hall, 2007. [11] V. Rajaraman and T. Radhakrishnan, Computer Organization and Arhiteture, First ed., PHI, 2007. [12] T. L. Floyd and R. P. Jain, Digital Fundamentals, Eighth ed., Pearson, 2005. [13] B. Holdsworth and C. Woods, Digital Logi Design, Ebook, Fourth ed., Newnes, 2002. [14] S. Wang, R. Han, M. Zhang, X. Fan and S. Zhang, "Improving Teahing Effiieny with Heuristi Teahing Method in Information Tehnology," in Proeedings of Advanes in Information Tehnology and Eduation, Part I, pp 454-458, Qingdao, China, July 2011, Springer - Verlag Berlin Heidelberg.