NTMFDCN PowerPhase, Dual N-Channel SOFL V, High Side A / Low Side 9 A Features Co Packaged Power Stage Solution to Minimize Board Space Minimized Parasitic Inductances Optimized Devices to Reduce Power Losses These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant Applications DC DC Converters System Voltage Rails Point of Load V (BR)DSS R DS(ON) MAX I D MAX Q Top FET V Q Bottom FET V. m @ V. m @. V. m @ V. m @. V D (,, 9) A 9 A () G () S SW (,, ) () G EFFICIENCY (%) 9 9 Figure. Typical Application Circuit V IN = V V OUT =. V V GS = V F SW = khz T A = C LOAD CURRENT (A) Figure. Typical Efficiency Performance POWERPHASEGEVB Evaluation Board D D S G CN A Y W ZZ PIN CONNECTIONS 9 D S (Bottom View) DFN CASE CR S () MARKING DIAGRAM = Specific Device Code = Assembly Location = Year = Work Week = Lot Traceability ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. SW SW SW G CN AYWZZ Semiconductor Components Industries, LLC, February, Rev. Publication Order Number: NTMFDCN/D
NTMFDCN Table. MAXIMUM RATINGS (TJ= C unless otherwise stated) Parameter Symbol Value Units Drain to Source Voltage Q V DSS V Gate to Source Voltage Q V GS ± V Continuous Drain Current R θja (Note ) Power Dissipation R θja (Note ) T A = C Power Dissipation Steady R θja s (Note ) State T A = C Q Q T A = C Q I D. A T A = C. T A = C Q 9 T A = C. Q P D.9 W Continuous Drain Current R θja s (Note ) T A = C Q I D. A Continuous Drain Current R θja (Note ) Power Dissipation R θja (Note ) T A = C Q T A = C. T A = C Q 9. T A = C. Q P D. W Q T A = C Q I D. A T A = C. T A = C Q 9. T A = C. Q P D. W Q P W Continuous Drain Current Q I D A R θjc Q Power Dissipation TC = C R θjc Q D Pulsed Drain Current T A = C tp = s Q Q I DM A Q Operating Junction and Storage Temperature Q T J, T STG to + C Source Current (Body Diode) Q I S A Q Q Drain to Source DV/DT dv/dt V/ns Single Pulse Drain to Source Avalanche Energy (T J = C, V DD = V, V GS = V, L =. mh, R G = ) I L = 9 A pk Q EAS. mj I L = A pk Q EAS Lead Temperature for Soldering Purposes (/ from case for s) T L C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Surface mounted on FR board using sq in pad, oz Cu.. Surface mounted on FR board using the minimum recommended pad size of mm.
NTMFDCN Table. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Units Junction to Ambient Steady State (Note ) R θja. C/W Junction to Ambient Steady State (Note ). Junction to Ambient (t s) (Note ). Junction to Case (bottom) Steady State Q R θjc. C/W Junction to Case (bottom) Steady State Q.. Surface mounted on FR board using sq in pad, oz Cu. Surface mounted on FR board using the minimum recommended pad size of mm Table. ELECTRICAL CHARACTERISTICS (T J = C unless otherwise specified) Parameter Symbol FET Test Condition Min Typ Max Units OFF CHARACTERISTICS Drain to Source Breakdown V (BR)DSS Q V Voltage V GS = V, I D = A Q Drain to Source Breakdown V (BR)DSS / T J Q 9 mv/ C Voltage Temperature Coefficient Q Zero Gate Voltage Drain Current I DSS Q T J = C A V GS = V, V DS = V T J = C Q T J = C Gate to Source Leakage Current I GSS Q V DS = V, na Q V GS = V ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) Q.. V V GS = V DS, I D = A Q.. Negative Threshold Temperature Coefficient V GS(TH) / T J Q. mv/ C Q. Drain to Source On Resistance R DS(on) Q V GS = V I D = A.. m V GS =. V I D = A.. Q V GS = V I D = A.. V GS =. V I D = A.9. CAPACITANCES Input Capacitance C ISS Q 9 pf Q Output Capacitance C OSS Q V GS = V, f = MHz, V DS = V Q Reverse Capacitance C RSS Q Q Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. Pulse Test: pulse width s, duty cycle %. Switching characteristics are independent of operating junction temperatures
NTMFDCN Table. ELECTRICAL CHARACTERISTICS (T J = C unless otherwise specified) Parameter Symbol FET Test Condition CHARGES & GATE RESISTANCE Total Gate Charge Q G(TOT) Q nc Q. Threshold Gate Charge Q G(TH) Q. Q. V GS =. V, V DS = V; I D = A Gate to Source Charge Q GS Q. Q Gate to Drain Charge Q GD Q. Q. Total Gate Charge Q G(TOT) Q nc V GS = V, V DS = V; I D = A Q 99. Gate Resistance R G Q. T A = C Q. SWITCHING CHARACTERISTICS (Note ) Turn On Delay Time t d(on) Q. ns Q 9. Rise Time t r Q Q V GS =. V, V DS = V, Turn Off Delay Time t d(off) Q I D = A, R G =. Q Fall Time t f Q. Q SWITCHING CHARACTERISTICS (Note ) Turn On Delay Time t d(on) Q. ns Q. Rise Time t r Q. Q V GS = V, V DS = V,. Turn Off Delay Time t d(off) Q I D = A, R G =. Min Q Fall Time t f Q. DRAIN SOURCE DIODE CHARACTERISTICS Forward Voltage V SD Q V GS = V, I S = A Typ Q. Q V GS = V, I S = A Max Units T J = C. V T J = C. T J = C. T J = C. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. Pulse Test: pulse width s, duty cycle %. Switching characteristics are independent of operating junction temperatures
NTMFDCN Table. ELECTRICAL CHARACTERISTICS (T J = C unless otherwise specified) Parameter Symbol FET Test Condition DRAIN SOURCE DIODE CHARACTERISTICS Reverse Recovery Time t RR Q Min Q Charge Time ta Q Q V GS = V, dis/dt = A/ s, Discharge Time tb Q I S = A Q Typ Max Units ns Reverse Recovery Charge Q RR Q nc Q Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. Pulse Test: pulse width s, duty cycle %. Switching characteristics are independent of operating junction temperatures
NTMFDCN TYPICAL CHARACTERISTICS Q I DS, DRAIN CURRENT (A). V V. V T J = C V GS =. V. V. V. V. V I DS, DRAIN CURRENT (A) V DS = V C. V. V... C C...... V GS, GATE TO SOURCE VOLTAGE (V) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE (m ) 9 V GS, GATE VOLTAGE (V) Figure. On Resistance vs. Gate to Source Voltage T J = C I D = A 9 R DS(on), DRAIN TO SOURCE RESISTANCE (m ) T J = C V GS =. V V GS = V I D, DRAIN CURRENT (A) Figure. On Resistance vs. Drain Current and Gate Voltage. R DS(on) (Normalized to C)........ V GS = V I D = A C, CAPACITANCE (pf) C ISS C OSS C RSS V GS = V T J = C f = MHz T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature Figure. Capacitance Variation
NTMFDCN TYPICAL CHARACTERISTICS Q t, TIME (ns) V GS = V V DS = V I D = A 9 T J = C t d(off) t f t r t d(on) I S, SOURCE CURRENT (A).......9 R G, GATE RESISTANCE ( ) Figure 9. On Region Characteristics V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Forward Voltage vs. Current V GS, GATE TO SOURCE VOLTAGE (V) Q T Q GS Q GD V GS = V V DS = V I D = A T J = C 9 I DSS, LEAKAGE (na).e+.e+.e+.e+.e+.e+ V GS = V T J = C T J = C T J = C Q G, TOTAL GATE CHARGE (nc) Figure. Gate to Source and Drain to Source Voltage vs. Total Charge I D, DRAIN CURRENT (A).. V GS V Single Pulse T C = C RDS(on) Limit Thermal Limit Package Limit Figure. Drain to Source Leakage Current vs. Voltage s s ms ms dc Figure. Maximum Rated Forward Biased Safe Operating Area
NTMFDCN TYPICAL CHARACTERISTICS Q R(t) ( C/W). % Duty Cycle % % % % %. Single Pulse PCB Cu Area mm PCB Cu thk oz....... PULSE TIME (sec) Figure. Thermal Characteristics
NTMFDCN TYPICAL CHARACTERISTICS Q I DS, DRAIN CURRENT (A). V V V GS =. V T J = C. V. V. V I DS, DRAIN CURRENT (A) V DS = V... C C C.... V GS, GATE TO SOURCE VOLTAGE (V) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE (m )............... V GS, GATE VOLTAGE (V) Figure. On Resistance vs. Gate to Source Voltage T J = C I D = A 9 R DS(on), DRAIN TO SOURCE RESISTANCE (m )........ T J = C V GS =. V V GS = V I DS, DRAIN CURRENT (A) Figure. On Resistance vs. Drain Current and Gate Voltage R DS(on) (Normalized to C).......... V GS = V I D = A C, CAPACITANCE (pf), 9 V GS = V T J = C f = MHz C ISS C OSS C RSS T J, JUNCTION TEMPERATURE ( C) Figure 9. On Resistance Variation with Temperature Figure. Capacitance Variation 9
NTMFDCN TYPICAL CHARACTERISTICS Q t, TIME (ns) V GS, GATE TO SOURCE VOLTAGE (V) V GS = V V DS = V I D = A R G, GATE RESISTANCE ( ) Figure. On Region Characteristics Q GS Q T Q GD Q G, TOTAL GATE CHARGE (nc) Figure. Gate to Source and Drain to Source Voltage vs. Total Charge t d(off) 9 T J = C t f t r t d(on) V GS = V V DS = V I D = A T J = C I DSS, LEAKAGE (na) I S, SOURCE CURRENT (A).E+.E+.E+.E+.E+.E+..E+.... V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Forward Voltage vs. Current V GS = V T J = C T J = C T J = C Figure. Drain to Source Leakage Current vs. Voltage. I D, DRAIN CURRENT (A).. V GS V Single Pulse T C = C RDS(on) Limit Thermal Limit Package Limit Figure. Maximum Rated Forward Biased Safe Operating Area s s ms ms dc
NTMFDCN TYPICAL CHARACTERISTICS Q R(t) ( C/W). % Duty Cycle % % % % %. Single Pulse PCB Cu Area mm PCB Cu thk oz....... PULSE TIME (sec) Figure. Thermal Characteristics Ordering Information NTMFDCNTG NTMFDCNTG Device Package Shipping DFN (Pb Free) DFN (Pb Free) / Tape & Reel / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D.
NTMFDCN PACKAGE DIMENSIONS DFN x,.p PowerPhase FET CASE CR ISSUE C D D X. C A B X. C NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, 99.. CONTROLLING DIMENSION: MILLIMETERS.. DIMENSIONS b AND b APPLY TO PLATED TERMINAL AND ARE MEASURED BETWEEN. AND. MM FROM THE TIPS.. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.. SEATING PLANE IS DEFINED BY THE TERMINALS. A IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. PIN ONE IDENTIFIER NOTE. C. C X L ÉÉ TOP VIEW SIDE VIEW E E A C SEATING PLANE DETAIL A NOTE X b. M C A B. M C NOTE X b c DETAIL A D X h A. M C A B E. M C A B MILLIMETERS DIM MIN MAX A.9. A.. b.. b.. c.. D. BSC D.9. D..9 D.9. E. BSC E.. E.. E.. E.. e. BSC G. BSC G. BSC h L..9 L..9 E L e/ e BOTTOM VIEW G G E D SUPPLEMENTAL BOTTOM VIEW RECOMMENDED SOLDERING FOOTPRINT*... X PITCH............ X.9.. DIMENSION: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
NTMFDCN ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 9 9 Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: http:///orderlit For additional information, please contact your local Sales Representative NTMFDCN/D