42nd ESSDERC, Bordeaux, France, 17-21 Sept. 2012 A2L-E, High Mobility Devices, 18 Sept. Study of Carrier Transport in Strained and Unstrained SOI Tri-gate and Omega-gate Si Nanowire MOSFETs M. Koyama 1,4, M. Cassé 1, R. Coquand 1,2,3, S. Barraud 1, H. Iwai 4, G. Ghibaudo 2, and G. Reimbold 1 1 CEA LETI, 2 IMEP-LAHC INPG-MINATEC, 3 STMicroelectronics, 4 FRC, Tokyo Institute of Technology
Introduction - Si nanowire MOSFETs FD-SOI/high-k/mid-gap MG (Undoped channel) Higher mobility Reduction of random dopant fluctuation (RDF) No poly-depletion Almost symmetrical Id-Vg curve for N- and PMOS Source Gate Gate Mid-gap MG High-k Undoped Si FD-SOI FET Drain Drain BOX Application Si nanowire MOSFETs High immunity to short channel effect (SCE) and drain induced barrier lowering (DIBL) Better electrostatic control Lower off-current (I OFF ) Steeper subthreshold slope (SS) Gate Source BOX Si Tri-gate NWFET Source BOX Si Drain Omega-gate NWFET Advantages in downscaling and power consumption 2
Issues and challenges Quantum confinement of carriers Downscaled cross-section of NW below 20nm 20nm Contributions of different crystallographic orientation Tri-gate: top surface and side-walls Ω-gate, GAA: rounded (omega-shaped, cylindrical) surface Stress engineering Improvement of device performance Promising solution to further scaling of CMOS technology Combination of NW architecture and stress 3
Purpose Understanding of carrier transport in SOI and ssoi Tri-gate and Omega-gate SiNW MOSFETs Influence on carrier transport - Channel shape Tri-gate vs Omega-gate - Width dimensions NW down to 10nm - Uniaxial tensile strain H Gate W Si Source BOX Si Drain Gate Si Source BOX Si Drain Measurement Carrier mobility on N- and PMOS NW FETs down to low temperature 4
Measured Si nanowires Gate stack: HfSiON(2nm)/ALD-TiN(5nm)/poly-Si(50nm) SOI and ssoi wafer Unstrained and strained NW - 50 channels NWs - Long channel transistors with Lg=10µm R.Coquand et al., Symp. VLSI Tech., p.13 (2012). Effective mobility extraction by conventional split C-V technique 5
Basic characteristics: Id-Vg curves I d /W tot (µa/µm) 10 3 10 0 10-3 10-6 Vd=0.9V Vd=40mV W=10nm H=11nm Tri-gate Vd=40mV Vd=0.9V Ω gate Vd=40mV Vd=0.9V 10-9 -1.5-1.0-0.5 0.0 0.5 1.0 1.5 V g (V) No I ON difference Vd=0.9V Vd=40mV W=23nm H=10nm Unstrained TG vs ΩG NWs 10 3 10 0 10-3 10-6 Vd=0.9V Vd=40mV ssoi-tg Vd=40mV Vd=0.9V SOI-TG Vd=40mV Vd=0.9V 10-9 -1.5-1.0-0.5 0.0 0.5 1.0 1.5 V g (V) Vd=0.9V Vd=40mV Vt shift Strained TG W=16nm H=10.5nm Unstrained vs strained TGNWs NMOS: I ON enhancement Vt shift ~ 40mV PMOS: I ON deterioration Subthreshold slope (SS) ~ 70mV/dec: Well behaved characteristics 6
Scattering-limited mobility in MOSFET Effective mobility, µ eff Coulomb scattering Low Surface roughness Phonon scattering scattering High Temperature Total mobility S.Takagi et al., Trans. Electron Dev., 41, 2357 (1994). Inversion charge density, Phonon scattering (PS) depends on temperature (T) Coulomb scattering (CS) Surface roughness scattering (SRS) T independent Carrier transport is limited by 3 scattering mechanisms 7
Temperature dependent mobility <TGNW vs Wide FET> Effective Mobility (cm²/vs) 1400 1 0 800 600 400 NMOS TGNW: W=10nm T=20K T=300K 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ( 10 13 cm -2 ) TGNW Wide FET Wide FET Effective Mobility (cm²/vs) 600 500 400 300 Wide FET: W=10µm PMOS 250 150 50 K 300K ( 10 13 cm -2 ) TGNW Wide FET K @ High 0.6 0.7 0.8 0.9 1.0 T=50K T=300K 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Tri-gate NW NMOS: Mobility deterioration @ high PMOS: Small mobility improvement @ high Maximum peak position shift to lower 8
Contribution of surface orientation to effective mobility Maximum mobility in unstrained wide FET Si surface orientation Top surface () Side-walls (110) µ eff_max (cm 2 /Vs) in SOI Electron (NMOS) 330 190 Hole (PMOS) 119 158 Gate [110] Source BOX Si Drain Top Si() Side-wall Si(110) Advantage Si()//[110] (top surface): electron transport Si(110)//[110] (side-walls): hole transport H.Irie et al., IEDM Tech. Dig., 225 (4). Electron mobility degradation Hole mobility enhancement as the width decreases Nanowire: Increasing the contribution of (110)-oriented side-walls 9
Extracted top and surface mobility in Tri-gate NW Effective Mobility (cm²/vs) 0 900 800 700 600 500 400 300 ~µ C TGNW: W=10nm µ top µ side-wall 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Tri-gate NW ( 10 13 cm -2 ) NMOS ~µ SR_top T=K µ ~µ SR_side-wall total eff Effective Mobility (cm²/vs) = W top() 2H µ eff + W + 2H W + 2H µ 450 400 350 300 250 150 50 µ top µ side-wall 0 0.0 0.2 0.4 0.6 0.8 1.0 ( 10 13 cm -2 ) Larger contribution of (110) side-wall PMOS ~µ SR_side-wall ~µ SR_top side wall(110) eff T=K Maximum mobility (Coulomb and Phonon) Surface roughness-limited mobility 10
Temperature dependent mobility <TGNW vs ΩGNW> TGNW: W=30nm ΩGNW: W=23nm Effective Mobility (cm²/vs) 1600 1400 1 0 800 600 400 NMOS ΩGNW TGNW T=20K T=300K 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Effective Mobility (cm²/vs) 800 700 600 500 400 300 T=20K T=300K 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 N 13-2 inv ( 10 13 cm -2 ) ( 10 13 cm -2 ) PMOS ΩGNW TGNW ΩG N- and PMOS Maximum mobility enhancement @ low T Lower Coulomb scattering due to H 2 anneal process 11
Stress effect on carrier transport along [110] (b) lateral strain relaxation s-si [110] [110] BOX BoX Biaxial vs uniaxial stress (~1.4GPa) - Biaxial tensile stress (in () plane) - Uniaxial stress along channel direction (Lateral strain relaxation) Mobility enhancement (degradation) from strain effect - Repopulation of Si conduction valleys - Reduction of intervalley phonon scattering Strain NMOS PMOS (transport //[110]) () (110) () (110) no strain 0-0 + biaxial tensile + - / = uniaxial tensile // [110] ++ ++ -- - Uniaxial tensile stress along [110] direction: Improving electron mobility 12
Top width (W top ) dependent effective mobility <TG vs WG> µ eff (cm 2 /Vs) @ High 500 400 300 Tri-gate +55% =1.0 10 13 cm -2 +70% 0.01 0.1 1 10 NW Wide W top (µm) ssoi SOI NMOS µ eff (cm 2 /Vs) @ High 500 400 300 Ω-gate +50% +65% 0.01 0.1 1 10 NW Wide W top (µm) Electron mobility degradation as the width narrowing =0.9 10 13 cm -2 ssoi SOI Uniaxial strained NW with ~50% gain in µ eff Still enhanced TG and ΩG devices exhibit almost the same mobility improvement - Strain relaxation - Piezoresistive properties Same in both geometries 13
Top width (W top ) dependent effective mobility <TG vs WG> µ eff (cm 2 /Vs) @ High 140 120 80 60 Tri-gate -30% =1.0 10 13 cm -2 ssoi SOI 0.01 0.1 1 10 W top (µm) PMOS Ω-gate TG and ΩGNW represent roughly the same mobility Strained NWs; No mobility improvement as W top decreases µ eff (cm 2 /Vs) @ High -25% =0.8 10 13 cm -2 ssoi SOI 0.01 0.1 1 10 W top (µm) Uniaxial tensile strain for PMOS Counterbalance of better mobility in unstrained Si(110) Large mobility degradation for Si() top surface 140 120 80 60 Agreement with NMOS 14
Temperature dependent mobility <SOI vs strained-soi> µ eff (cm 2 /Vs) @ High NMOS 3000 0 ~µ SR_wide Unstrained =0.8 10 13 cm -2 Strained Tri-gate Ω-gate Tri-gate Ω-gate W=10nm W=10µm W=23nm W=10µm W=16nm W=10µm W=33nm W=10µm 20 300 20 300 Temperature (K) Wide FET 3000 0 ~µ SR_wide ~µ SR_NW ~µ SR_NW Temperature (K) T>K T<K Phonon-limited mobility: Improvement from strain effect Mobility saturation from surface roughness scattering (SRS) SR-limited mobility: Small enhancement by strain effect Roughly same properties in both TG and ΩG geometries 15
Temperature dependent mobility <SOI vs strained SOI> µ eff (cm 2 /Vs) @ High PMOS 500 50 ~µ SR_NW ~µ SR_wide Unstrained Wide FET 500 =0.7 10 13 cm -2 Strained Tri-gate Ω-gate Tri-gate Ω-gate W=30nm W=10µm W=23nm W=10µm W=36nm W=10µm W=33nm W=10µm 20 300 50 20 300 Temperature (K) ~µ SR_wide ~µ SR_NW Temperature (K) Whole T range Stress influence to mobility (Phonon- and SR-limited) Enhancement: Wide FETs Degradation: TG and ΩG NWs Same in both NWs Biaxial stress (wide FET): Improvement Uniaxial stress (both NWs): Deterioration 16
Temperature dependent maximum mobility Influence of phonon scattering µ max ~ µ phonon T γ Values of power law exponent γ Tri-gate Wide (10µm) NMOS SOI ssoi 0.95 0.64 PMOS SOI ssoi 1.00 1.18 w/o H 2 anneal NW 0.94 0.63 0.98 1.25 Ω-gate Wide (10µm) 1.05 0.69 1.03 1.07 with H 2 anneal NW 1.05 0.41 1.12 1.13 Larger stress influence for NMOS Phonon-limited mobility Dependent on the strain effect Independent on channel shape width dimension 17
Conclusions Carrier transport in strained and unstrained TG and ΩG NWs i) Transport properties in TGNWs (down to 10nm 10nm section) Agreement with the contribution of different orientation Larger Si(110) side-wall contribution ii) ΩGNWs (down to W top-view of 23 nm) Roughly same mobility behavior as TGNWs Lower Coulomb scattering iii) Uniaxial strain in both nanowire geometries Enhancing NMOS performance Diminishing PMOS performance Phonon-limited and SR-limited mobility No significant difference from the channel shape 18
Modifiez les styles du texte du masque Deuxième niveau > Troisième niveau Thank you for Merci de votre your kind attention attention E-mail: masahiro.koyama@cea.fr 19
Backup slides 20
Temperature dependent mobility <TGNW vs ΩGNW> TGNW: W=10nm W=30nm ΩGNW: W=23nm Effective Mobility (cm²/vs) 1600 1400 1 0 800 600 400 NMOS ΩGNW TGNW (30nm) T=20K T=300K 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Effective Mobility (cm²/vs) 1600 1400 1 0 800 600 400 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 N 13-2 inv ( 10 13 cm -2 ) ( 10 13 cm -2 ) NMOS ΩGNW TGNW (10nm) T=20K T=300K ΩG NMOS Maximum mobility enhancement @ low T Lower Coulomb scattering due to H 2 anneal process 21
Temperature dependent mobility <TGNW> TGNW: W=10nm vs W=30nm Effective Mobility (cm²/vs) 1 0 800 600 400 NMOS T=20K T=300K 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ( 10 13 cm -2 ) W=10nm W=30nm Larger contribution of (110) side-wall 300K 250K K 150K K 50K 20K Maximum mobility (Coulomb and Phonon) Surface roughness-limited mobility 22
Temperature dependent mobility <SOI vs strained SOI> µ eff (cm 2 /Vs) @ High NMOS 3000 0 3000 0 20 300 20 300 Tri-gate W=10nm W=30nm W=10µm Unstrained Ω-gate W=23nm W=10µm Wide FET ~µ SR_NW ~µ SR_NW =0.8 10 13 cm -2 Tri-gate W=16nm W=36nm W=10µm Strained Ω-gate W=33nm W=10µm Difference between W top =10nm & 30nm TGNWs Contribution of (110) side-walls 23
Extraction of µ top and µ side-wall contribution for Tri-gate NW Contribution of surface orientation to effective mobility µ µ total eff = W top() 2H µ eff + W + 2H W + 2H µ side wall(110) eff = α µ total eff W µ 2H top() eff side wall(110) eff W + 2H α = 2H J. Chen et al., Symp., VLSI Tech., p.32 (8). R. Coquand et al., Proc., ULIS conf. (2012). Si surface orientation Top surface () Side-walls (110) Electron (NMOS) + - µ eff (cm 2 /Vs) Hole (PMOS) - + H Gate [110] W Source BOX Si Drain Top Si() Side-wall Si(110) Scattering behavior on µ top and µ side-wall? 24
Scattering influence in µ top and µ side-wall of Tri-gate NW Effective Mobility (cm²/vs) 0 900 800 700 600 500 400 300 ~µ C NMOS T=K T=300K 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ( 10 13 cm -2 ) ~µ SR_top ~µ SR_side-wall µ top µ side-wall µ Si(110) TGNW: W=10nm µ side-wall ~ referential µ Si(110) Mobility limit Scattering mechanism Coulomb (µ C ) Surface roughness (µ SR ) µ top () Strong Weak µ side-wall (110) Weak Strong 25
Scattering influence in µ top and µ side-wall of Tri-gate NW Effective Mobility (cm²/vs) 550 500 450 400 350 300 250 150 50 ~µ C ~µ SR_side-wall ~µ SR_top 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 ( 10 13 cm -2 ) PMOS T=K T=300K µ top µ side-wall µ Si(110) TGNW: W=30nm µ side-wall ~ µ Si(110) @ high Mobility limit Scattering mechanism Coulomb (µ C ) Surface roughness (µ SR ) µ top () No difference µ side-wall (110) Similar slope 26
H 2 anneal impact in wide device Effective Mobility (cm²/vs) 1600 1400 1 0 800 600 400 Wide FET NMOS Wide FET: W=10µm 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ( 10 13 cm -2 ) 300K 250K K 150K K 50K 20K Enhancement Coulomb-limited mobility SR-limited mobility 500 450 400 350 300 250 150 50 ΩG_with H 2 (W=10µm) TG_w/o H 2 (W=10µm) PMOS 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 ( 10 13 cm -2 ) 300K 250K K 150K K 50K 20K Enhancement Coulomb-limited mobility 27
Mobility improvement from strain effect Mobility gain in Strained-Si nmosfet (tensile) Increase of the 2-fold valley occupancy (population) with lower conductivity mass Decrease the phonon scattering rate between the 2-fold and the 4-fold valleys (intervalley scattering) Strain effect for hole (tensile) Breking of the valence band degeneracy Reduction of conductivity mass 28
Fablication process Undoped FD-SOI wafer (Mesa isolation) - with or w/o biaxial tensile stress of ~1.4 GPa NW patterning (DUV lithography) - with or w/o H 2 anneal HfSiON(2nm)/ALD TiN(5nm)/poly-Si(50nm) gate stack Gate patterning Spacer 1 formation S/D epitaxy (T Si =18nm) LDD implantation Spacer 2 formation HDD implantation Silicidation Back-end 29
Basic characteristics: Id-Vg curves I d /W tot (µa/µm) 10 2 10 0 10-2 10-4 Vd=40mV NMOS 2.5 2.0 1.5 1.0 10 1 10-1 10-3 10-5 Vd=-40mV PMOS 1.0 0.8 0.6 0.4 Tri-gate Omega-gate strained-tg strained-ωg 10-6 0.5 10-7 0.2 I d /W tot (µa/µm) 0.0 0.5 1.0 0.0 1.5 10 3 40 10-8 10 1 32 10-1 10-3 Vd=0.9V 24 16 d tot 10-9 0.0-0.5-1.0 0.0-1.5 10 2 10 10 0 8 10-2 10-4 Vd=-0.9V 6 4 Tri-gate Omega-gate strained-tg strained-ωg 10-5 8 10-6 2 10-7 0 0.0 0.5 1.0 1.5 V g (V) 10-8 0.0-0.2-0.4-0.6-0.8-1.0-1.2-1.4 V g (V) 0 30