Matched N-Channel JFET Pairs N// PRODUCT SUMMARY Part Number V GS(off) (V) V (BR)GSS Min (V) g fs Min I G Typ (pa) V GS V GS Max (mv) N. to 7. N. to 7. N. to 7. FEATURES BENEFITS APPLICATIONS Two-Chip Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low Noise: nv Hz @ Hz Good CMRR: 7 db Minimum Parasitics Tight Differential Match vs. Current Improved Op Amp Speed, Settling Time Accuracy Minimum Input Error/Trimming Requirement Insignificant Signal Loss/Error Voltage High System Sensitivity Minimum Error with Large Input Signals Maximum High Frequency Performance Wideband Differential Amps High-Speed, Temp-Compensated, Single-Ended Input Amps High-Speed Comparators Impedance Converters Matched Switches DESCRIPTION The N// are matched pairs of JFETs mounted in a TO-7 package. This two-chip design reduces parasitics for good performance at high frequency while ensuring extremely tight matching. This series features high breakdown voltage (V (BR)DSS typically > V), high gain (typically > 9 ms), and < mv offset between the two die. The hermetically-sealed TO-7 package is available with full military processing (see Military Information). For similar products see the low-noise U/SST series, and the low-leakage N9/97/98/99 data sheets. TO-7 S G D D G S Top View ABSOLUTE MAXIMUM RATINGS Gate-Drain, Gate-Source Voltage............................... V Gate-Gate Voltage............................................ 8 V Gate Current................................................. ma Lead Temperature ( / from case for sec.).................. C Storage Temperature................................... to C Document Number: 7 S- Rev. E, -Jan- Operating Junction Temperature.......................... to C Power Dissipation : Per Side a........................ mw Total b........................... mw Notes a. Derate. mw/ C above C b. Derate. mw/ C above C
N// SPECIFICATIONS ( UNLESS OTHERWISE NOTED) Static Limits N N N Parameter Symbol Test Conditions Typ a Min Max Min Max Min Max Unit Gate-Source Breakdown Voltage Gate-Source Cutoff Voltage V (BR)GSS I G = A, V DS = V V GS(off) V DS = V, I D = na... Saturation Drain Current b I DSS V DS = V, V GS = V ma Gate Reverse Current I GSS T A = C na V GS = V, V DS = V pa Gate Operating Current c I G na V DG = V, I D = ma pa Drain-Source On-Resistance r DS(on) V GS = V, I D = ma Gate-Source Voltage c V GS V DG = V, I D = ma. Gate-Source Forward Voltage Dynamic Forward Transconductance Output Conductance V GS(F) I G = ma, V DS = V.7 g fs g os V DS = V, I D = ma f = khz V Forward Transconductance d g DS = V, I D = ma fs f = MHz C Input Capacitance iss V DS = V, I D = ma f = MHz Reverse Transfer C rss Capacitance Equivalent Input Noise Voltage e n V DS = V, I D = ma f = Hz 9 7.. 7.. 7.. ms S 8. 7 7 7 ms. Noise Figure NF R G = M db Matching Differential Gate-Source Voltage Gate-Source Voltage Differential Change with Temperature V GS V GS V DG = V, I D = ma mv V GS V GS T V DG = V, I D = ma T A = to C V V pf nv Hz V/ C Saturation Drain Current Ratio c I DSS I DSS V DS = V, V GS = V.98.9.9.9 Transconductance Ratio g fs g fs V DS = V, I D = ma f = khz.98.9.9.9 Common Mode Rejection Ratio c CMRR V DG = to V I D = ma 7 db Notes a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NCBD b. Pulse test: PW s duty cycle %. c. This parameter not registered with JEDEC. d. Not a production test. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 7 S- Rev. E, -Jan-
N// TYPICAL CHARACTERISTICS ( UNLESS OTHERWISE NOTED) rds(on) Drain-Source On-Resistance ( ) rds(on) Drain-Source On-Resistance ( ) gfs Forward Transconductance 8 8 On-Resistance and Drain Current vs. Gate-Source Cutoff Voltage r DS @ ID = ma, V GS = I DSS @ V DS = V, V GS = r DS I DSS 8 V GS(off) Gate-Source Cutoff Voltage (V) Forward Transconductance and Output Conductance vs. Gate-Source Cutoff Voltage g fs and g os @ V DS = V V GS = V, f = khz On-Resistance vs. Temperature I D = ma r DS changes.7%/ C 8 T A Temperature ( C) g fs g os 8 I DSS Saturation Drain Current (ma) gos Output Conductance ( S) rds(on) Drain-Source On-Resistance ( ) Switching Time (ns) Switching Time (ns) 8 8 On-Resistance vs. Drain Current t r t d(on) @ I D = ma Turn-On Switching t r approximately independent of I D V DG = V, R G = V GS(L) = V t d(on) @ I D = ma 8 V GS(off) Gate-Source Cutoff Voltage (V) t d(off) Turn-Off Switching t d(off) independent of device V GS(off) V DG = V, V GS(L) = V t f 8 8 V GS(off) Gate-Source Cutoff Voltage (V) Document Number: 7 S- Rev. E, -Jan-
N// TYPICAL CHARACTERISTICS ( UNLESS OTHERWISE NOTED) Drain Current (ma) I D 8 V GS(off) =. V Output Characteristics.7 V 8 V DS Drain-Source Voltage (V) V GS = V. V. V. V. V. V. V Drain Current (ma) I D 8 C C Transfer Characteristics T A = C V DS = V..8.. V GS Gate-Source Voltage (V) Output Characteristics V GS = V V GS(off) =. V. V. V. V Capacitance vs. Gate-Source Voltage f = MHz V DS = V Drain Current (ma) I D. V. V. V.7 V.8 V Capacitance (pf) 8 C iss C rss.9 V....8 8 V DS Drain-Source Voltage (V) V GS Gate-Source Voltage (V) na na Gate Leakage Current I GSS @ C I D = ma Common-Gate Input Admittance V DG = V I D = ma g ig I G Gate Leakage pa pa ma ma ma I GSS @ C b ig pa. pa I G(on) @ I D 8 V DG Drain-Gate Voltage (V). Document Number: 7 S- Rev. E, -Jan-
N// TYPICAL CHARACTERISTICS ( UNLESS OTHERWISE NOTED) Common-Gate Forward Admittance V DG = V I D = ma Common-Gate Reverse Admittance V DG = V I D = ma g fg b fg b rg g fg g rg +g rg... Common-Gate Output Admittance V DG = V I D = ma b og g og en Noise Voltage nv / Hz Noise Voltage vs. Frequency V DS = V I D = ma I D = ma. k k k f Frequency (Hz) Output Conductance vs. Drain Current V DS = V f = khz Transconductance vs. Drain Current V DS = V f = khz g os Output Conductance (µs) C T A = C C g fs Forward Transconductance C C T A = C.... maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http:///ppg?7. Document Number: 7 S- Rev. E, -Jan-
Notice Legal Disclaimer Notice Vishay Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. Document Number: 9 Revision: 8-Apr-