Self-shrinking Bit Generation Algorithm Based on Feedback with Carry Shift Register

Transcription

1 Advanced Studies in Theoretical Physics Vol. 8, 2014, no. 24, HIKARI Ltd, Self-shrinking Bit Generation Algorithm Based on Feedback with Carry Shift Register Borislav Stoyanov Department of Computer Informatics Faculty of Mathematics and Informatics Konstantin Preslavski University of Shumen, 9712 Shumen, Bulgaria Copyright c 2014 Borislav Stoyanov. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Abstract In this paper, we design a self-shrinking scheme which combines a feedback with carry shift register and the self-shrinking generator, based on A. Kanso PhD study. We calculated the period of the designed algorithm. The key gamma is statistically tested with NIST test suite. The result of the analysis shows that the properties of the output bits are like randomly generated physical phenomena. Subject Classification: a, Hh, Lt, Dd, c, r Keywords: Self-shrinking generator, feedback with carry shift register, pseudo-random bit generation scheme 1 Introduction Self-shrinking generators based on feedback with carry shift registers (FCSRs) are important part of the pseudorandom bit generator investigations. In [8] a self-shrinking rule is applied on FCSR. A new self-shrinking variant of pseudorandom bit generation is presented in [9]. In [10] a novel self-shrinking cryptographic generator is developed. New self-shrinking rule applied to p-adic feedback with carry shift register is constructed in [11], and improved cryptanalysis is presented in [7]. A novel FCSR-based generalized self-shrinking

2 1058 Borislav Stoyanov stream sequence generator is proposed in [3]. The cryptographic characteristics of the FCSR-based self-shrinking sequence are studied in [12]. In this paper, we design a self-shrinking scheme which combines a feedback with carry shift register and the self-shrinking generator, based on A. Kanso PhD study [4]. The result of the analysis shows that the properties of the output bits are like randomly generated physical phenomena. 2 Feedback with Carry Shift Registers In this section we refer to works of [2] and [5]. The feedback with carry shift register is a shift register with an additional memory m, Figure 1. Let us fix an odd positive integer q Z, called connection integer, and let r = log 2 (q + 1) (where denotes the integral part). We write q = q q q r 2 r 1 for binary representation of the integer q + 1 (so q r = 1). The feedback taps are given by the numbers from q 1 to q r. The shift array uses log 2 (r) additional bits of memory, denoted initially m n 1, and r elements, denoted by a n 1, a n 2,..., a n r+1, a n r. On every clock the shift array forms the integer sum σ n = r q k a n k + m n 1 (1) k=1 and shifts the contents one step to the right, outputting the rightmost bit a n r. Then it assigns a n = σ n (mod 2) into the leftmost cell of the shift register and replaces the memory integer m n 1 with m n = σ n /2. m n-1 a n-1 a n-2 a n-r+1 a n-r div 2 mod 2 Sum q 1 q 2 q r-1 q r Figure 1: Feedback with Carry Shift Register The output stream a = (a 0, a 1, a 2... ) is strictly periodic under the following conditions [5]: q is prime number of r + 1 bits. 2 is primitive root modulo q.

3 Self-shrinking bit generation algorithm based on FCSR 1059 q = 2d + 1, where d is a prime number. The Hamming weight of the binary representation of q is wt(q) > r/2. 3 Self-shrinking Bit Generation Algorithm Based on Feedback with Carry Shift Register The designed self-shrinking algorithm is inspired by the self-shrinking algorithm in A. Kanso PhD study [4]. In our scheme we substitute the linear feedback shift register with the advanced feedback with carry shift register, R 0. The proposed algorithm consists of the following steps: Step 1: The initial values q 1, q 2,..., q r, m r 1, and a bit stream limit L are determined. Step 2: The feedback with carry shift register R 0 is clocked for L 1 4r times. Step 3: The clock of the R 0 continues, and if the current output bit a i = 1, the bit a i+1 produces part of the output gamma. Step 4: Return to Step 3 until the bit stream limit L is reached. The designed bit generator is implemented in C++, using the following initial values: r = 129, q = [1], m r 1 = 0. 4 Security Analysis Let s = (s 0, s 1, s 2... ) is the key gamma generated from the proposed algorithm by using feedback with carry shift register with connection integer q = 2d + 1 under the conditions from Section 2. Because of the balanced output from R 0 the period of the key gamma is d. The NIST test suite [6] includes 15 statistical tests. 1, 000, 000, 000 bits were generated using the proposed pseudorandom bit generation algorithm. The results of the tests are given in Table 1. The minimum pass rate for the Random-excursion variant test is approximately The minimum pass rate for the other tests is approximately The entire NIST test suite is passed successfully.

4 1060 Borislav Stoyanov 5 Conclusion NIST Proposed Algorithm statistical test P-value Pass rate Frequency (monobit) Block-frequency Cumulative sums (Forward) Cumulative sums (Reverse) Runs Longest run of Ones Rank FFT Non-overlapping templates Overlapping templates Universal Approximate entropy Random-excursions Random-excursions Variant Serial Serial Linear complexity Table 1: NIST test suite results. We have designed pseudorandom generation algorithm based on self-shrinking principle and feedback with carry shift register. Based on the detailed analysis the novel scheme has perfect characteristics for cryptographic modules. Acknowledgements. This work is partially supported by the Scientific research fund of Konstantin Preslavski University of Shumen under the grant No. RD / References [1] F. Arnault, T. Berger, Design and properties of a new pseudorandom generator based on a filtered FCSR automaton, IEEE Transactions on Computers, 54 (2005), [2] F. Arnault, T. Berger, F-FCSR: design of a new class of stream ciphers, In Gilbert, H., Handshuh, H. (eds.) Fast Software Encryption 2005, Lecture Notes in Computer Science, 3557 (2005), [3] L. Dong, Y. Zeng, Y. Hu, F-GSS: A Novel FCSR-Based Keystream Generator, In International Conference on Information Science and Engineering, ICISE 2009,

5 Self-shrinking bit generation algorithm based on FCSR 1061 [4] A. Kanso, Clock Controlled Generators, PhD Thesis, Royal Holloway and Bedford New College, University of London, [5] A. Klapper, M. Goresky, Feedback Shift Registers, 2-adic Span, and Combiners with Memory, Journal of Cryptology, 10 (1997), [6] A. Rukhin, J. Soto, J. Nechvatal, M. Smid, E. Barker, S. Leigh, M. Levenson, M. Vangel, D. Banks, A. Heckert, J. Dray, and S. Vo, A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Application, NIST Special Publication , Revision 1a (Revised: April 2010), Lawrence E. Bassham III, 2010, [7] B. Stoyanov, Improved Cryptoanalysis of the Self-shrinking p-adic Cryptographic Generator, International Book Series, Supplement to International Journal Information Technologies and Knowledge, Advanced Studies in Software and Knowledge Engineering, 4 (2008), [8] B. Stoyanov, M. Kolev, A. Nachev, Design of a New Self-Shrinking 2-adic Cryptographic System with Application to Image Encryption, European Journal of Scientific Research, 78 (2012), [9] B. Stoyanov, K. Kordov, Pseudorandom Bit Generator with Parallel Implementation, In Large-Scale Scientific Computing 2013, Lecture Notes in Computer Science, 8353 (2014), [10] B. Stoyanov, A. Milev, A. Nachev, Research on the self-shrinking 2-adic cryptographic generator, Journal of Communication and Computer, 7 (2010), [11] Z. Tasheva, B. Bedzhev, B. Stoyanov, Self-Shrinking p-adic Cryptographic Generator, In International Scientific Conference on Information, Communication and Energy Systems and Technologies, ICEST 2005, Ni s, Serbia and Montenegro, June 29 July 1, 2005, [12] H. Wang, Q. Wen, J. Zhang, The Properties of the FCSR-Based Self- Shrinking Sequence, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E96-A (2013), Received: October 6, 2014; Published: November 3, 2014