Characterization of Dielectric Relaxation and Reliability of High-k MIM Capacitor Under Constant Voltage Stress

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.1, NO.5, OCTOBER, 01 Charactrization of Dilctric Rlaxation and Rliability of High-k MIM Capacitor Undr Constant Voltag Strss Ho-Young Kwak 1, Sung-Kyu Kwon 1, Hyuk-Min Kwon 1, Sung-Yong Sung 1, Su Lim, Choul-Young Kim 1, Ga-Won L 1, and Hi-Dok L 1,* Abstract In this papr, th dilctric rlaxation and rliability of high capacitanc dnsity mtal-insulatormtal (MIM) capacitors using Al O 3 -HfO -Al O 3 and SiO -HfO -SiO sandwichd structur undr constant voltag strss (CVS) ar charactrizd. Ths rsults indicat that although th multilayr MIM capacitor provids high capacitanc dnsity and low dissipation factor at room tmpratur, it inducs gratr dilctric rlaxation lvl (in ppm). It is also shown that dilctric rlaxation incrass and lakag currnt dcrass as functions of strss tim undr CVS, bcaus of th charg trapping ffct in th high-k dilctric. Indx Trms MIM (Mtal-Insulator-Mtal), AHA (Al O 3 -HfO -Al O 3 ), SHS (SiO -HfO -SiO ), charg trapping ffct, dilctric rlaxation I. INTRODUCTION Mtal-Insulator-Mtal (MIM) capacitors ar widly usd for in intgratd circuit applications, such as analogto-digital (A/D) convrtrs, digital-to-analog (D/A) convrtrs, and rsonators, du to thir low parasitic capacitanc, and low sris rsistanc [1, ]. Rcntly, th MIM capacitors hav gnratd grat attntion in Manuscript rcivd May. 8, 01; accptd Sp. 1, 01 A part of this work was prsntd in Koran Confrnc on Smiconductors, Soul in Kora, Fb Dpt. of Elctronics Enginring, Chungnam National Univrsity, Dajon , Kora Dongbu HiTk Smiconductor Inc., Buchon, Gyonggi 0-71, Kora hdl@cnu.ac.kr, Tl : silicon intgratd circuit (IC) applications as passiv componnts, bcaus th total ara of passiv dvics, capacitors in particular, usually consums a larg portion of th whol chip siz. Thrfor, MIM capacitors with a high capacitanc dnsity hav bn rquird in ordr to incras th circuit dnsity and rduc th systm cost [3]. Silicon dioxid (SiO, ~3.9) and silicon nitrid (Si 3 N, ~7) ar commonly usd as insulator matrials in convntional MIM capacitors. Although ths convntional dilctric matrials hav good voltag linarity and low tmpratur cofficints, thir capacitanc dnsity has bn limitd, owing to thir low dilctric constant. Achiving high capacitanc dnsity by rducing th thicknss of convntional dilctric matrials, silicon dioxid (SiO ) and silicon nitrid (Si 3 N ), has ld to high lakag currnt and rliability issus []. Thrfor, th us of high-k dilctric matrials, such as HfO (~5), Al O 3 (~9), ZrO (~0), Ta O 5 (~5), and TiO (~80), is ncssary to incras th capacitanc dnsity and rduc th lakag currnt. Du to outstanding proprtis, such as high capacitanc dnsity, good thrmal stability, and high band gap, hafnium-oxid basd MIM capacitors ar widly usd for nxt gnration capacitors [5]. Howvr, MIM capacitor with singl high-k dilctric shows high lakag currnt. In th last fw yars, laminat or sandwichd structurs of MIM capacitor by adding Al O 3 or SiO layrs hav bn studid to rduc th lakag currnt. Howvr, it is known that MIM capacitors with high-k dilctric hav many dfcts in th mtal-insulator intrfac, which implis that th injctd chargs in th intrfac of high-k dilctric induc gratr chang of capacitor charactristics than thos in th intrfac of convntional

2 5 HO-YOUNG KWAK t al : CHARACTERIZATION OF DIELECTRIC RELAXATION AND RELIABILITY OF HIGH-K MIM dilctric matrials do [6]. Ths caus a larg dpndnc of capacitanc prformanc on applid voltag and tmpratur. Also, it is shown that prformanc of MIM capacitors dgrads by lctrical strss [7]. Dilctric rlaxation (DR) is on of th rlatd phnomna, du to th trapping and d-trapping mchanism in th high-k dilctric [8]. DR can dgrad th prformanc, lik analogu and digital convrtrs (ADC) and voltag controlld oscillators (VCO) linarity [9]. Howvr, thr has bn littl study of lctric strss associatd with DR. In this papr, rliability and dilctric rlaxation of MIM capacitors, in particular, of advancd capacitors with Al O 3 - HfO - AlO 3 (AHA) and SiO -HfO -SiO (SHS) sandwichd structur ar analyzd undr constant voltag strss (CVS). Opn S1 Clos S1 (a) CUT S tim II. EXPERIMENT Fig. 1 shows th procss flow by which th MIM capacitors usd in this xprimnt wr fabricatd, with sandwichd dilctric structur of Al O 3 /HfO /Al O 3 and SiO /HfO /SiO. MIM capacitors wr fabricatd on 8- inch p-typ silicon substrats. TiN layr was usd as th bottom lctrod. Aftr that, th stackd dilctric layrs with Al O 3 ( nm), HfO (11 nm), and Al O 3 ( nm) and SiO (3 nm), HfO ( nm), and SiO (3 nm) wr squntially dpositd using th atomic layr dposition (ALD) mthod at 300. Finally, TiN layr was dpositd and pattrnd, to form th top lctrod. A convntional MIM capacitor with Si 3 N was also fabricatd using PE-CVD mthod for comparison. An Al-Cu layr was usd as th bottom lctrod and a TiN layr was usd as th top lctrod. TiN film was dpositd as bottom lctrod Dilctric film dpositd using ALD at 300 (SHS : 3//3nm, AHA : /11/nm) TiN film was dpositd as top lctrod Annaling procss at 0, 30min Fig. 1. Procss flow for fabrication of MIM capacitor with sandwichd structur. Opn S Clos charg discharg (b) masurmnt CVS is applid using an Agilnt 156C smiconductor paramtr analyzr. Th DR charactristic was valuatd using th masurmnt systm shown in Fig. (a). Fig. (b) shows th clock signals applid to switchs for masurmnt of dilctric rlazation. In th charg priod, switch 1 is closd and switch is opnd. During th discharg priod, switch 1 is opnd and switch is closd, vic vrsa. Finally, in th masurmnt priod, switch 1 and switch ar opnd. III. RESULT AND DISCUSSION tim Fig.. (a) Masurmnt systm of dilctric rlaxation charactristic for MIM capacitor, (b) timing diagram of th switchs. DR is a carrir absorption/rlaxation phnomnon btwn th lctrods and th intrfac of dilctric. Thr ar two mthods to masur DR charactristic in th tim domain. On is th rcovry voltag tchniqu [10] and th othr is th discharg currnt mthod [11]. For th accurat valuation of DR charactristic, w usd

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.1, NO.5, OCTOBER, V CUT (V) charg Dilctric rlaxation Tim (sc) Dilctric Rlaxation [ppm] Si3N SHS AHA Dilctric Matrial discharg Fig. 3. Normalizd voltag across th MIM capacitor during masurmnt of dilctric rlaxation. th first mthod. Fig. 3 shows th chang of capacitor voltag with masurmnt tim. Th positiv rcovry voltag is masurd from ngativ voltag potntial bcaus th charging voltag is applid to th bottom lctrod. Th top plat may b groundd or lft floating, and th bottom plat may b groundd or bing chargd. Capacitor is chargd for a long tim thn momntarily shortd th capacitor for a short tim. Finally, th capacitor rmaind floating stat and th voltag at th trminals is masurd ovr tim. At a givn applid charging voltag, traps in th intrfac of th dilctric bcom gradually filld ovr tim. Du to th dtrappd chargd from ths trap sits in th dilctric, th voltag of th capacitor riss slowly aftr th floating priod. Fig. shows th dilctric rlaxation lvl (in ppm), with various dilctric matrials of th MIM capacitor. It shows that MIM capacitor with high-k dilctric has a highr DR lvl than that with a convntional dilctric matrial, bcaus th high-k dilctrics hav mor traps in th dilctric than convntional dilctric matrials, such as SiO, and Si 3 N. Fig. 5 shows th incras of DR valu aftr CVS for 000 sc. W applid th sam ffctiv lctric fild (E ff ) to th MIM capacitors for an accurat comparison of th dilctric rlaxation charactristics. W normalizd th thicknss of th dilctric layr in trms of HfO quivalnt as dfind blow. Thrfor, th normalizd thicknsss (t ff ) ar dfind as (1) and (). Fig.. Dilctric rlaxation charactristic of th MIM capacitor with dilctric matrial. D Dilctric Rlaxation [%] D Dilctric Rlaxation [%] Strss tim : 000sc CVS:5V(AHA), 7.9V(SHS), 1V(Si3N) Si3N SHS AHA Dilctric Matrial (a) AHA (CVS : 5V) SHS (CVS : 7.9V) Si 3 N (CVS : 1V) Strss Tim [sc] (b) Fig. 5. Tim volution of dilctric rlaxation undr CVS according to th dilctric matrial (a) during 000 sc, (b) lik NBTI strssing for 000 sc. t = t + t () HfO ff. SHS HfO SiO SiO Thn, th ffctiv lctric fild is dfind as (3). t = t + t (1) HfO ff. AHA HfO AlO3 AlO3 E ff V V AHA SHS Si3 N º = = (3) tff. AHA tff. SHS tff. Si3N V

4 56 HO-YOUNG KWAK t al : CHARACTERIZATION OF DIELECTRIC RELAXATION AND RELIABILITY OF HIGH-K MIM Sampling Currnt [ma/cm ] Sampling Currnt [ma/cm ] Strss tim [sc] Strss tim [sc] ACKNOWLEDGMENTS This work (rsarch) is financially supportd in part by th Ministry of Knowldg Economy (MKE) and Kora Institut for Advancmnt of Tchnology (KIAT) through th Workforc Dvlopmnt Program in Stratgic Tchnology. This work was also partially supportd by th IT R&D program of MKE/KEIT. [ , Dvlopmnt of -NVM (mbddd Non- Volatil Mmory) Analog mixd signal-basd Convrgnc procss tchnology & IP]. Fig. 6. Charactristic of lakag currnt with strss tim undr CVS. Th applid voltag for CVS of AHA, SHS, and Si 3 N dilctrics wr 5V, 7.9V, and 1V, rspctivly. Fig. 5 indicats that th high-k dilctrics show a grat incras of DR than convntional dilctric matrial. Th largst variation of DR occurs in th AHA structur. This is bcaus HfO has th largst prfactor among th various high-k dilctric matrials, rlatd to th charg losss in DRAMs and V T -shift in MOSFETs [1]. Figs. 5(a) and (b) show a similar incras in DR valu. Fig. 6 shows that th lakag currnt dcrass during CVS for SHS structur. It is causd by th gnration of traps and lctron trapping in th dilctric. At th initial stat undr CVS, th rduction of lakag is grat, bcaus th gnration of traps occurs mainly nar th intrfac of dilctric and th lctrod. Figs. 5 and 6 indicat that th charg trapping ffct with CVS causs th variation of dilctric rlaxation valu. IV. CONCLUSIONS In this papr, w analyzd th dilctric rlaxation charactristics and rliability of MIM capacitors with Al O 3 /HfO /Al O 3 and SiO/HfO /SiO sandwichd structurs undr constant voltag strss. It is shown that a MIM capacitor with high-k dilctric has a highr dilctric rlaxation (DR) lvl, and gratr incras of DR valu uncr constant voltag str (CVS) than dos convntional dilctric matrial. Th lakag currnt dcrass with strss-tim undr CVS. Th charg trapping ffct in th dilctric contributs to th variation of th variation of th capacitor paramtrs. REFERENCES [1] C. C Huang, C. H. Chng, A. Chin, and C. P. Chou, Lakag Currnt Improvmnt of Ni/TiNiO/TaN Mtal-Insulator-Mtal Capacitors using Optimizd N + Plasma Tratmnt and Oxygn Annaling, Elctrochmical and Solid-Stat Lttrs, Vol.10, No.10, pp.h87-h90, Jul [] V. Mikhlashvili, G. Eisnstin, and A. Lahav, High capacitanc dnsity mtal-insulator-mtal structur basd on Al O 3 -HfTiO nanalaminat stacks, Appl. Phys. Ltt., Vol.90, No.1, pp (1-3), Jan [3] H. Hu, C. Zhu, Y. F. Lu, Y. H. Wu, T. Liw, M. F. Li, B. J. Cho, W. K. Choi, and N. Yakovlv, Physical and lcrical charactrization of HfO mtal-insulator-mtal capacitors for Si analog circuit applications, J. Appl. Phys, Vol.9, No.1, pp , Jul [] T. Rmml, R. Ramprasad, and J. Walls, Lakag Bhavior and Rliability Assssmnt of Tantalum Oxid Dilctric MIM Capacitors, Proc. Int. Rliability Physics Symp., pp.77-81, Mar [5] X. Yu, C. Zhu, H. Hu, A. Chin, M. F. Li, B. J. Cho, D. L. Kwong, P. D. Foo, and M. B. Yu, A highdnsity MIM capacitor (13fF/µm ) using ALD HfO dilctrics, IEEE Elctron Dvic Ltt., Vol., No., pp.63-65, Fb, 003. [6] J. Babcock, S. Balstr, A. Pinto, C. Dirnckr, P. Stinmann, R. Jumprtz, and B. El-Karh, Analog charactristics of mtal-insulator-mtal capacitors using PECVD nitrid dilctrics, IEEE Elctron Dvic Ltt., Vol., No.5, pp.30-3, May, 001. [7] H. Y. Kwak, H. M. Kwon, Y. J. Jung, S. K. Kwon,

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.1, NO.5, OCTOBER, J. H. Jang, W. I Choi, M. L. Ha, J, I, L, S. J. L and H. D. L, Charactrization of Al O 3 -HfO - Al O 3 sandwichd MIM capacitor undr DC and AC strsss, SSE, Vol.79, pp.18-, Jan, 013. [8] Z. Ning, H. Casir, R. Gillon, H.X. Dlcourt, D. Tack, E. D. Vyldr, P. V. Torr and D. Hgstd, Analog charactrization of dilctric rlaxation of MIM capacitor using an improvd rcovry voltag tchniqu, IEEE Intnational Confrnc on Microlctronic Tst Structurs (ICMTS), pp , Mar [9] A. Zanchi, F. Tsay, and I. Papantonopoulos, Impact of Capacitor Dilctric Rlaation on a 1- bit 70-MS/s piplin ADC in 3-V BiCMOS, IEEE Jonrnal of Solid-Stat Circuits, Vol.38, No.1, pp , Dc, 003. [10] J. C. Kunn and G. M. Mijr, Masurmnt of dilctric absorption of capacitors and analysis of its ffcts on VCOs, IEEE Tras. on Instrumntation nad Masurmnt, Vol.5, No.1, pp.89-97, Fb [11] Z. Xu, L. Pantisano, A. Krbr, R. Dgrav, E. Cartir, S. D Gndt, M. Hyns and G. Grosnkn, A study of rlaxation currnt in high-k dilctric stacks, IEEE Trans Elctron Dvics, Vol. 51, No.3, pp.0-08, Mar. 00. [1] H. Risingr, G. Stinlsbrgr, S. Jakschik, M. Gutsch, T. Hcht, M. Lonhard, U. Schrodr, H. Sidl, and D. Schumann, A comparativ study of dilctric rlaxation losss in altrnativ dilctrics, in IEDM tch. Dig., pp , Dc Ho-Young Kwak was born in Dajon. Kora in H rcivd B.S. and M.S. dgrs in lctronics nginring fron Chung-nam National Univrsity, Dajon. Kora. in 011 and 013, rspctivly. His major rsarch intrsts includ charactrization and rliability of high-k dilctrics of CMOS dvics for analog mixd-signal applications. Sung-Kyu Kwon rcivd th B.S. dgr and M.S. dgr in lctronics nginring from th Chungnam National Univrsity, Dajon, Kora in 011 and 013. Sinc 013, h has bn a Ph.D. studnt in lctronics nginring from th Chungnam National Univrsity, Dajon, Kora. His main rsarch intrsts includ rliability and low frquncy nois charactristics of nano-cmos dvics for analog mixd signal application. Hyuk-Min Kwon Hyuk-Min Kwon rcivd th B.S., M.S., and Ph.D. dgrs from Chungnam National Univrsity, Dajon, Kora, in 007, 009, and 01, rspctivly, all in lctronics nginring. H has bn with SEMATECH, Austin, TX, USA, as a Visiting Rsarch Scholar, sinc 013. H is currntly involvd in nanoscal CMOS tchnology, rliability physics, tst pattrn for matching, RF CMOS modling, and low-frquncy nois for nano-cmos, G/III V quantum wll MOSFETs and Fin-FETs. Sung-Yong Sung rcivd B.S. and M.S. dgrs in lctronics nginring fron Chungnam National Univrsity, Dajon. Kora. in 01 and 01, rspctivly. His main rsarch intrsts includ charactrization and rliability of nano-scal CMOS dvic and EDMOS for analog mixd-signal applications. Su Lim rcivd th B.S. and M.S. dgrs in lctronics nginring from Chungnam National Univrsity, Dajon, Kora, in 00 and 00, rspctivly. Sinc 00, h joind Dongbu HiTk Smiconductor Inc., Buchon, Kora, whr h has bn involvd in dvloping mixd signal products of 0.18μm CMOS tchnology. Sinc 010, h has bn dvloping dvics charactrization and masurmnt mthodology of CMOS/BCD tchnologis.

6 58 HO-YOUNG KWAK t al : CHARACTERIZATION OF DIELECTRIC RELAXATION AND RELIABILITY OF HIGH-K MIM Choul-Young Kim (S 0) rcivd th B.S. dgr in lctrical nginring from Chungnam National Univrsity (CNU), Dajon, Kora, in 00 and M.S. and Ph.D dgrs in lctrical nginring from Kora Advancd Institut of Scinc and Tchnology (KAIST), Dajon, Kora, in 00 and 008, rspctivly. From March 009 to Fbruary 011, h was a Postdoctoral Rsarch Fllow at th dpartmnt of lctrical and computr nginring at th Univrsity of California, San Digo (UCSD). H is assistant profssor of lctronics nginring at Chungnam National Univrsity, Dajon, Kora. His rsarch intrsts includ mm-wav intgratd circuits and systms for short rang radar and phasd-array antnna applications. Ga-Won L rcivd th B.S., M.S., and Ph.D. dgrs in lctrical nginring from th Kora Advancd Institut of Scinc and Tchnology, Dajon, Kora, in 199, 1996, and 1999, rspctivly. In 1999, sh joind Hynix Smiconductor Ltd. as snior rsarch nginr, whr sh was involvd in th dvlopmnt of μm, 0.09-μm DDRII DRAM tchnologis. Sinc 005, sh has bn in Chungnam National Univrsity, Dajon, Kora, as a Profssor with th Dpartmnt of Elctronics Enginring. Hr main rsarch filds ar flash mmory, flxibl display tchnology including fabrication, lctrical analysis and modling. Hi-Dok L rcivd a B.S., M.S., and Ph.D. dgrs in Elctrical Enginring from th Kora Advancd Institut of Scinc and Tchnology (KAIST), Dajon, Kora, in 1990, 199, and 1996, rspctivly. In 1993, h joind th LG Smicon Company, Ltd. (currntly SK Hynix Smiconductor Ltd.), Chongju, Choongbuk, Kora, whr h has bn involvd in th dvlopmnt of μm, 0.5-μm, and 0.18-μm CMOS tchnologis, rspctivly. H was also rsponsibl for th dvlopmnt of 0.15-μm and 0.13-μm CMOS tchnologis. Sinc 001, h has bn with Chungnam National Univrsity, Dajon, Kora, with th Dpartmnt of Elctronics Enginring. From 006 to 008, h was with th Univrsity of Txas, Austin, and SEMATECH, Austin, as a Visiting Scholar. His rsarch intrsts ar in nanoscal CMOS tchnology and its rliability physics, silicid tchnology, and Tst Elmnt Group dsign. His rsarch intrsts also includ dvlopmnt of high prformanc analog and high voltag MOSFETs, and high fficint silicon solar clls. Dr. L is a mmbr of th Institut of Elctronics Enginrs of Kora.