HIGH-SPEED and high-resolution analog-to-digital converter

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1 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 4, APRIL Timing Mismatch Compensation in Time-Interleaved ADCs Based on Multichannel Lagrange Polynomial Interpolation Yue Xian Zou, Senior Member, IEEE, Shang Liang Zhang, Yong Ching Lim, Fellow, IEEE, and Xiao Chen Abstract In this paper, the timing mismatch compensation problem in the implementation of a time-interleaved analogto-digital converter (TIADC) is investigated. The investigation leads to a novel multichannel Lagrange polynomial interpolation timing-mismatch compensation algorithm (MLPI-TMCA). A multichannel Lagrange compensation filter (MLCF) in the form of a finite-impulse response (FIR) filter is also developed for real-time implementation. The design of the compensation system is done in three steps. First, the coefficients of the MLCF are computed based on the mismatch parameters of the TIADC. Second, an N th order FIR filtering process is performed for each sub-adc. Third, a multiplexer is used to combine the output of each compensation filter in an orderly manner into the final compensated output signal. The computational complexity of this timing mismatch compensation system is of order N. Computer simulation results showed that MLPI-TMCA is computationally efficient and not sensitive to timing mismatch fluctuations. The actual implementation of a four-channel 320-MHz 12-bit TIADC showed that the MLPI-TMCA is able to efficiently compensate the timing mismatch in a real-time manner and produced about 30-dB spurious-free dynamic range (SFDR) enhancement when the input signal frequency is 70 MHz, whereas the multirate filter banks compensation method produced about 19 db of SFDR enhancement under the same condition. Thus, the MLPI-TMCA and its multichannel filter implementation provides a good solution for TIADC real-time timing mismatch compensation and may be employed in TIADC chip design due to its implementation advantages. Index Terms Lagrange polynomial interpolation, multichannel filter, real-time compensation, spurious-free dynamic range (SFDR), time-interleaved analog-to-digital converter (TIADC) timing mismatch. I. INTRODUCTION HIGH-SPEED and high-resolution analog-to-digital converter (ADC) is a key component for many modern electronic systems, such as radars, communication systems, and medical instruments. For a given fabrication technology Manuscript received March 8, 2010; revised August 26, 2010; accepted August 29, Date of publication November 9, 2010; date of current version March 8, This work is supported by National Natural Science Foundation of China (NSFC, No ). The Associate Editor coordinating the review process for this paper was Dr. Jerome Blair. Y. X. Zou, S. L. Zhang, and X. Chen are with the Peking University Shenzhen Graduate School, Shenzhen , China ( zouyx@szpku.edu.cn; zhshli8324@gmail.com). Y. C. Lim is with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TIM and ADC word-length requirement, there is a limit to the maximum achievable sampling speed. To achieve a conversion speed higher than that achievable by a single ADC, Black and Hodges time-interleaved technique [1] that results in a timeinterleaved ADC (TIADC) may be considered. To achieve an overall sampling rate of f s, the TIADC is formed by using M identical parallel ADCs (channels), each with sampling rate of f s /M, as shown in Fig. 1(a). Each channel samples the input signal in turn, and the outputs are combined into one output signal. Ideally, all the M parallel channels are assumed to be linear and identical. They should have the same gain and the same sampling interval T s =1/f s, and should be operating at the precise sampling time instants. However, due to the practical implementation constraints, the TIADC exhibits the following problems: each channel has a slightly different gain leading to a channel gain mismatch, a different bandwidth leading to a channel bandwidth mismatch, a different dc offset leading to a channel dc offset mismatch, and different clock generating circuits and transmission path leading to a timing mismatch. It is well known that the above mismatches severely reduce the spurious-free dynamic range (SFDR) of the TIADC [2]. Detailed discussions on mismatches can be found in [3] [6]. Many techniques have been proposed for compensating the timing mismatch [7] [9], [11], [16], [17]. Discrete-time fractional delay filters were employed in a filter-bank structure [7] to reconstruct a class of nonuniformly sampled signals of the TIADC system at the price of additional oversampling. A technique based on the digital interpolation using Neville s method, which estimates the correct output values from the output samples with timing mismatch, was developed in [8]. Research shows that Neville s method is essentially the Lagrange polynomial interpolation technique. In [10], a multirate-filter-bank architecture is used to model the nonuniform sampling (through the analysis bank) and to reconstruct a uniformly sampled sequence (through the synthesis bank). Recently, a flexible and scalable structure to compensate frequency-response mismatches has been developed in [12] by introducing a system model that establishes the relation between TIADCs and time-varying systems. One advantage of this technique is that it may be used to compensate time-varying frequency-response mismatches in TIADCs. In [13], a multichannel-filtering approach is used for the TIADC mismatch compensation, which is computationally less /$ IEEE

2 1124 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 4, APRIL 2011 Fig. 1. Conceptual illustration of the TIADC and the timing-mismatch effect. (a) Conceptual illustration of M-channel TIADC [13]. (b) Effect of the timing mismatch in a TIADC with M =4. complex and more robust than the filter-bank approach. Besides, several authors have proposed blind-compensation techniques [14], [15], which do not require the estimation of the timing-mismatch parameters. Compared with the offline timing-mismatch compensation techniques, blindcompensation techniques are, in general, less accurate and have much higher computational complexity. In this paper, we study on the time-mismatch compensation problem of the TIADC under the Nth order Lagrange polynomial interpolation framework. Our originality contribution lies in the development of a real-time implementation of the Nth order Lagrange polynomial interpolation using the TIADC output data with a lower computational complexity, a better numerical stability, and a favorable implementation structure, which can be easily reconfigured to fit in different TIADC structures. With the careful evaluation of the working rationale of the TIADC system and the mechanism of the timing mismatch, we noted that the polynomial interpolation may provide a good solution. For example, Selva studied a modified Lagrange interpolator for signal reconstruction from the nonuniform samples [18], and a so-called functionally weighted Lagrange interpolation algorithm has been derived. Experimental results showed that this method permits one to interpolate a given band-limited signal from its nonuniformly spaced samples with high accuracy. However, there is no result showing that this algorithm is able to provide a favorite online implementation structure for TIADC timing-mismatch compensation applications. The task of the TIADC sampling-time-mismatch compensation is to estimate the desired samples at the ideal sampling instants from actual samples, as shown in Fig. 1(b). In the polynomial interpolation, the unique N th order polynomial that fits N +1 data points and is used to compute intermediate values at arbitrary sampling instants. The Lagrange interpolation polynomial, which is a reformulation of the Newton polynomial that avoids the computation of divided differences, is an excellent candidate because of its low computational complexity. Let the N +1 distinct x i, where i =0, 1,...,N,bethe actual sampling instants with corresponding sampled signal values y i. The classical problem addressed here is that of finding polynomial f N (x) in the Nth order Lagrange polynomial form [19]. According to the Lagrange interpolation formula, Fig. 2. Block diagram of the proposed TIADC timing-mismatch compensation system. the interpolated signal value at any arbitrary sampling instant t is given by N f N (t) = h i (t)y i (1) where h i (t) = i=0 N j=0 j i t x j x i x j. (2) The entire TIADC system, together with the compensation network, is shown in Fig. 2. Our proposed system shown in Fig. 2 consists of two functional blocks, namely, (1) the calibration block and (2) the online processing block. The calibration block is composed of the channel-timing-mismatch measurement block and the computation of coefficients of compensation filters block, which is conducted during the calibration stage. A TIADC channel mismatch parameter measurement technique based on the sine-fitting method is employed to obtain the channel-timingmismatch parameter. Then, the coefficients of timing-mismatch compensation filters are calculated by using the TIADC timingmismatch compensation algorithm (TMCA) proposed in this paper. Details of the online processing algorithm will be presented in the sequel. The performance of the technique will be verified through computer simulations and an actual hardware implementation. This paper is organized as follows. The analysis of the timing-mismatch property of the output of the TIADC system is presented in Section II. The algorithm proposed in this paper, called multichannel Lagrange polynomial interpolation

3 ZOU et al.: TIMING MISMATCH COMPENSATION IN TIME-INTERLEAVED ADCs BASED ON MLPI 1125 Fig. 3. Illustration of the TIADC nonuniform sampling. TMCA (MLPI-TMCA), is described in detail in Section III. Computer simulation results are presented in Section IV. A field-programmable gate array (FPGA) implementation of a 4 80 mega samples per second (MS/s) 12-bit TIADC incorporating our proposed technique is presented in Section IV. The conclusion is drawn in Section V. II. TIMING-MISMATCH PROPERTIES OF THE TIADC Ideally, each subchannel of a TIADC samples the input signal uniformly at the rate of f s /M. However, as a result of the timing mismatch, the output of a TIADC exhibits nonuniform sampling characteristics, as illustrated in Fig. 3. In Fig. 3, T s is the ideal sampling interval of the TIADC system; x i denotes the ith actual sampling instant; t i is the ith ideal sampling instant; y i is the actual sampling output at time instant x i ; f N (t i ) is the desired output at time instant t i ; M is the number of channels of the TIADC system; and Δt m (m =0, 1,...,M 1) is the timing mismatch of the mth channel, i.e., the displacement in time between the ideal sampling instant and the actual sampling instant. Minimizing the SFDR due to the timing mismatch and developing an efficient implementation structure are our main concerns. Hence, in this paper, we shall ignore the random clock jitter, which may cause an increase in the noise floor in the TIADC output spectrum. Let (x i,y i ) represent the ith uncompensated TIADC output sample y i at the sampling instant x i. Thus x i = i T s +Δt i mod M (3) where mod is the modular operator. The ith ideal sampling instant denoted by t i is given by t i = t pm+m = i T s =(pm + m)t s, p =0, 1, 2,... (4) where m is the channel index (m =0, 1,...,M 1). t pm+m is the pth ideal sampling instant of the mth channel of the TIADC system. In Section III, (3) and (4) will be utilized in determining an efficient formulation of the N th order Lagrange polynomial, which can be used to interpolate the value f N (t i ) at the ideal sampling time instant t i. III. MLPI-TMCA Our technique can be applied to the TIADC with any number of channels using an arbitrary-order Lagrange polynomial. Nevertheless, in order to fix the idea, we consider compensating the timing mismatch of a four-channel TIADC using a secondorder Lagrange polynomial as an example to illustrate our approach. Since N =2, if three consecutive samples (x 0,y 0 ), (x 1,y 1 ), and (x 2,y 2 ) are given, f 2 (t i ) can be determined by using the Lagrange interpolation formula in (1) and (2). Let i =1,wehave f 2 (t 1 )= (t 1 x 1 )(t 1 x 2 ) (x 0 x 1 )(x 0 x 2 ) y 0 + (t 1 x 0 )(t 1 x 2 ) (x 1 x 0 )(x 1 x 2 ) y 1 We define h m,g (g =0, 1, 2) as follows: + (t 1 x 0 )(t 1 x 1 ) (x 2 x 0 )(x 2 x 1 ) y 2. (5) h m,0 = (t 1 x 1 )(t 1 x 2 ) (x 0 x 1 )(x 0 x 2 ) h m,1 = (t 1 x 0 )(t 1 x 2 ) (x 1 x 0 )(x 1 x 2 ) h m,2 = (t 1 x 0 )(t 1 x 1 ) (x 2 x 0 )(x 2 x 1 ) (6a) (6b) (6c) where m =(i mod M). For this example, m= (1mod4)=1. Thus, h m,0 = h 1,0, h m,1 = h 1,1, and h m,2 = h 1,2. Specifically, substituting (6) into (5), we have f 2 (t 1 )=h 1,0 y 0 + h 1,1 y 1 + h 1,2 y 2. (7) Similarly, if output samples (x 4,y 4 ), (x 5,y 5 ), and (x 6,y 6 ) are available, f 2 (t 5 ) can be determined by f 2 (t 5 )= (t 5 x 5 )(t 5 x 6 ) (x 4 x 5 )(x 4 x 6 ) y 4 + (t 5 x 4 )(t 5 x 6 ) (x 5 x 4 )(x 5 x 6 ) y 5 + (t 5 x 4 )(t 5 x 5 ) (x 6 x 4 )(x 6 x 5 ) y 6. (8) It is noted that the sampling instants of the M-channel TIADC system satisfies the following relations: t i+m = t i + MT s x i+m = x i + MT s. (9a) (9b)

4 1126 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 4, APRIL 2011 Fig. 4. Structure of a four-channel TIADC employing a second-order Lagrange polynomial. For the specific example where M is equal to 4, we have t 5 = t 1 +4T s x 4 = x 0 +4T s x 5 = x 1 +4T s x 6 = x 2 +4T s. Substituting (10) into (8), we get (10a) (10b) (10c) (10d) f 2 (t 5 )=h 1,0 y 4 + h 1,1 y 5 + h 1,2 y 6. (11) Evaluating (7) and (11), it can be seen that both f 2 (t 1 ) and f 2 (t 5 ) are determined by the same set of Lagrange polynomial coefficients h 1,0, h 1,1, and h 1,2, and they are the output samples of the sub-adc-1 (m =1)since the sampling instants t 1 and t 5 are associated with sub-adc-1. Generally, for this special case where M =4and N =2, the compensated output samples of the mth sub-adc can be determined by using h m,0, h m,1, h m,2 (m =0, 1,...,3). Representing h m,g in vector form, we have H 0 =[h 0,0 h 0,1 h 0,2 ] T (12a) H 1 =[h 1,0 h 1,1 h 1,2 ] T (12b) H 2 =[h 2,0 h 2,1 h 2,2 ] T (12c) H 3 =[h 3,0 h 3,1 h 3,2 ] T. (12d) The elements of H m are given by h m,g = m+5 j=m+3 j m+3+g t m+4 x j x m+3+g x j, m =0, 1,...,3,g =0, 1, 2 (13) where h m,g is the gth coefficient of the timing-mismatch compensation filter (or the gth Lagrange polynomial coefficient) for the m channel. The computational structure for f 2 (t 1 ), f 2 (t 2 ), f 2 (t 3 ), and f 2 (t 4 ) for the above example is shown in Fig. 4; it is an (N +1)-input M-output multichannel filter with the coefficients h m,g. The general expression for an M-channel TIADC employing the N th (assumed to be even)-order Lagrange interpolating polynomial is given by f N (t pm+m )=y T i H m, m=0, 1,...,M 1,p=0, 1, 2,... (14) where T is the transpose operator, H m is the mth Lagrange polynomial coefficient vector, and y i is the input sample vector for estimating f N (t i ) using (14). Assuming that N is even, y i is given by y i =[y i N/2,y i N/2+1,...,y i,...,y i+n/2 1,y i+n/2 ] T, i = N/2,N/2+1,... (15) The mth Lagrange polynomial coefficient vector H m given by H m =[h m,0 h m,1 h m,2,..., h m,n ] T, m =0, 1,...,M 1 (16) where h m,g is defined at the bottom of the next page. In (17), l is an integer given by ( ) N +1 l = ceil (18) 2M where ceil(x) is the smallest integer larger than x. Fromthe second equation in (17), we can see that h m,g is determined by M, T s, Δt m, and N. Equation (14) is the time-domain equation of an M-channel finite-impulse response (FIR) filter. The output f N (t pm+m ) is the compensated TIADC output at the ideal sampling instant t pm+m ; H m, and y i in (14) are the filter coefficient vector and the input signal vector, respectively. The general implementation structure is shown in Fig. 5. It has been reported in [20] that a higher-order Lagrange polynomial may perform worse than a lower-order polynomial toward the end of the interval for evenly spaced input data set; this is called the Runge phenomenon. The Runge phenomenon was not observed in our TIADC implementation since the is

5 ZOU et al.: TIMING MISMATCH COMPENSATION IN TIME-INTERLEAVED ADCs BASED ON MLPI 1127 Fig. 5. Schematic block diagram of the proposed MLPI timing-mismatch compensation system. instant of the ideal sample to be interpolated is close to the center of the interval of the input sample vector and the input sample is nonuniformly spaced. From our experience, the performance of our MLPI-TMCA improves with increasing N at the price of increasing implementation cost. The tradeoff between N and the accuracy of the interpolation process is an important issue in the hardware implementation. Without loss of generality, any particular channel of the TIADC may be used as a timing reference. Suppose that we choose the zeroth channel as a reference channel. Hence, we have Δt 0 =0. The timing mismatch Δt m (m =1, 2., M 1) of other sub-adcs is defined with reference to the timing of the zeroth channel. Hence, we have H 0 =[ ]. (19) Since no timing compensation is needed for the zeroth channel, the overall computational complexity of the MLPI-TMCA will be further reduced by a factor of about M. Neville s iteration method was adopted by Jin and Lee [8] for the TIADC compensation. The interpolation is based on the following iterative equation: y k,l = (t x k)y k 1,l 1 (t x k l )y k,l 1 (20) x k l x k where t, x k l, and x k are the appropriate time instants. The 2-D array y k,l represents the estimated output sample of the TIADC at time instant x k after l iterations (details can be found in [8]). Analysis shows that the algorithm described in (20) requires quite a high computational complexity. Using an N th order interpolation, (20) must be iteratively computed (N 1)N/2 times. Moreover, (20) is not in the form of a FIR filter. Its recursive computation renders the pipelined implementation difficultly [21] [24]. IV. SIMULATION AND FPGA IMPLEMENTATION RESULTS This section presents several computer simulation results for a four-channel TIADC system. The timing mismatches areassumedtobeδt 0 =0, Δt 1 =0.03/f s, Δt 2 =0.05/f s, and Δt 3 = 0.02/f s, respectively, where f s, which is the overall sampling frequency of the TIADC system, was 320 MHz. Since we focus on the timing-mismatch compensation technique in this paper, the modeling of other errors has not been addressed in this paper (readers can refer to [8] for more discussions). In the following simulation study, we assume the following: 1) the analog input of the TIADC is a pure sine wave; 2) the data length for processing is of samples; and 3) the modeling of the imperfection of the front-end circuits except the channel mismatches of the TIADC is represented by a Gaussian noise [8]. Hence, the output of the TIADC can be modeled as an ideally sampled sine wave with a timing mismatch plus a Gaussian noise. SNR is defined as the ratio of the power of the sine wave with timing mismatch to the power of the additive Gaussian noise in decibels in this paper. A. Computer Simulation Results Fig. 6(a) shows the computer simulated spectral plot for the TIADC output when the input is a 100-MHz sinusoid and the SNR is set as 78 db. The spurious frequencies due to timing mismatch can be easily seen. The largest spurious spur was db. Fig. 6(b) shows the output spectral plot of the TIADC output after the application of our proposed technique. It can be seen that the spurious spurs were significantly attenuated; the largest spurious spur was db. To evaluate the influence of the polynomial interpolation order N on the performance of the MLPI-TMCA at a different input frequency f in, we vary order N from2to60atastep h m,g = = lm+m+n/2 j=lm+m N/2 j lm+m N/2+g lm+m+n/2 j=lm+m N/2 j lm+m N/2+g t lm+m x j x lm+m N/2+g x j (lm + m j)t s Δt j mod M (lm + m N/2+g j)t s +Δt (lm+m N/2+g) modm Δt j mod M, (g =0, 1, 2,...,N,m=0, 1, 2,...,M 1) (17)

6 1128 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 4, APRIL 2011 Fig. 6. Normalized output spectrum of the TIADC system (the frequency of the analog input signal is 100 MHz, and SNR =78dB). (a) Without compensation. (b) After compensation using the MLPI-TMCA with N =60. Fig. 7. SFDR performance of the MLPI-TMCA versus the order of the interpolation under different input frequencies (the sampling frequency of TIADC is 320 MHz, and SNR =78dB). size of 2, and the frequencies of the input signal from 100 to 150 MHz spaced by 10 MHz. The SNR is also set as 78 db. The simulation results are shown in Fig. 7. Three conclusions can be drawn from the simulation results. First, for a given f in, the SFDR expressed in decibel improvement increases almost linearly with increasing N until a limit. Second, for a given N, the SFDR improvement decreases with increasing f in.in addition, we can see that the SFDR improvement is limited when the f in is approaching the Nyquist frequency. Third, the slope of the SFDR improvement versus order N decreases with increasing f in. Finally, the largest SFDR improvement is limited by the Gaussian noise. To evaluate the performance of the MLPI-TMCA under different timing mismatches Δt m,wevariedδt m from 0.005/f s to 0.2/f s at a step size of 0.005/f s. In this simulation study, only the channel timing mismatch is considered. The frequencies of the input signal were varied from 100 to 130 MHz at a step size of 10 MHz. The order of the interpolation polynomial was 60 (i.e., N =60). The simulation results are shown in Fig. 8. SFDR performance of the MLPI-TMCA versus different Δt m under different input frequency. Fig. 8. It can be seen from Fig. 8 that, for a given input frequency, the SFDR decreases with increasing max(δt m ). Moreover, the SFDR decreases with increasing the input frequency for all timing-mismatch cases. In order to investigate the effect of the Δt m drift on the performance of the proposed MLPI-TMCA, we shall suppose that Δt m has drifted to Δt m. Define the ratio, i.e., R t =Δt m/δt m. (21) The simulation parameters are the following: N =60; R t was varied from 0.5 to 1.5 at a step size of 0.05; the frequencies of the input signal were varied from 100 to 130 MHz at a step size of 10 MHz; and the SNR is set as 78 db. The simulation results are shown in Fig. 9. As expected, the SFDR deteriorates rapidly when R t deviates from unity. Similarly, in the investigation of its finite coefficient wordlength effect, we choose N =60and Δt 0 =0, Δt 1 =0.03/f s, Δt 2 =0.05/f s, and Δt 3 = 0.02/f s ; the frequencies of the input signal were varied from 100 to 130 MHz at a step size of 10 MHz, and the SNR is set as 78 db. The simulation results

7 ZOU et al.: TIMING MISMATCH COMPENSATION IN TIME-INTERLEAVED ADCs BASED ON MLPI 1129 Fig. 11. Developed four-channel 12-bit 320-MHz TIADC system. Fig. 9. SFDR versus R t under different input frequencies. TABLE I COMPUTED MLCF COEFFICIENTS (N =12, M =4, AND f s = 320 MHz) Fig. 10. Finite word-length effects on the performance of the MLPI-TMCA. are shown in Fig. 10. It can be seen from Fig. 10 that, when the coefficient word length is shorter than necessary, every bit reduction in the coefficient word length causes about 6 db of degradation in the SFDR. B. FPGA Implementation Results A4 80-MS/s 12-bit TIADC has been developed (as shown in Fig. 11), and our timing-mismatch compensation technique has been implemented in the FPGA. The ADC chip used in the TIADC system is AD9236 from Analog Devices, which is a monolithic single 30-V supply 12-bit 80-MS/s ADC, and its SFDR performance is 87.8 db to Nyquist. A TIADC channel-mismatch parameter measurement technique based on the sine-fitting method [25] is employed to obtain the channel-timing-mismatch parameter, which includes the following: 1) applying a sine wave with a specified frequency to the TIADC converter; 2) L samples of each sub- ADC output are recorded; 3) fitting a sine wave function to each sub-adc recorded data by using the least square criterion to minimize the sum of the squared difference between the sine function and the recorded data; and 4) choosing one of the sub-adcs as the reference channel (sub-adc-0 is selected in our study) and computing the relative parameter difference between the sub-adcs and the reference channel to get the mismatch parameters. The measured timing mismatches were Δt 0 =0, Δt 1 = /f s, Δt 2 = /f s, andδt 3 = /f s, respectively, where f s = 320 MHz. The order of the interpolation polynomial was 12. The multichannel Lagrange compensation filter (MLCF) coefficients were computed from (17) and shown in Table I. The compensation algorithm was implemented on a XUP Virtex-II Pro Development System with a 12-bit coefficient word length. The input test signal was a MHz sinusoid samples of the TIADC output were collected for spectral analysis. The uncompensated spectral plot is shown in Fig. 12(a). The spectral plots of the output-compensated result using our technique, the multirate-filter-bank technique suggested in

8 1130 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 4, APRIL 2011 Fig. 12. Spectral plots of a 12-bit 320-MS/s TIADC system (f in =70.01 MHz). (a) Without compensation. (b) With compensation by using the MLPI-TMCA with N =12. (c) With compensation by using approach [10] with a filter length of 12. (d) With compensation by using the technique reported in [12] (three cascade stages are used; six FIR filters are adopted to implement the compensation, which has the lengths of 11, 17,17, 21,21, and 21, respectively). [10], and the late technique reported in [12] are shown in Fig. 12(a) (d), respectively, for comparison purposes. In Fig. 12, the 9.99-, , and 150-MHz spurs were due to the timing mismatch. Comparing Fig. 12(b) with Fig. 12(c), it is clear that our technique is superior to that reported in [10]. Comparing Fig. 12(b) with Fig. 12(d), it is also clear to see that our technique has achieved the similar SFDR of that reported in [12] but at a lower computational complexity. V. C ONCLUSION A novel real-time compensation algorithm, called the MLPI- TMCA, and an efficient implantation structure for its implementation have been proposed in this paper. The coefficients of the filters have been determined by the timing mismatch Δt m, the overall sampling frequency f s, the number of the sub-adcs M, and the order N of the Lagrange polynomial employed at the calibration stage. Numerous experiments have been conducted to evaluate the SFDR performance of the MLPI-TMCA under different conditions. Our technique has been implemented on a 4 80-MS/s 12-bit TIADC on the FPGA, and experimental results have shown that the proposed algorithm is superior to the techniques reported in [10] and [12] at the similar computational complexity. REFERENCES [1] W. C. Black and D. A. Hodges, Time interleaved converter array, IEEE J. Solid-State Circuits, vol. SSC-15, no. 6, pp , Dec [2] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, Explicit analysis of channel mismatch effects in timeinterleaved ADC systems, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp , Mar [3] K. Dyer, D. H. Fu, P. Hurst, and S. Lewis, A comparison of monolithic background calibration in two time-interleaved analog-to-digital converters, in Proc. Int. Symp. Circuits Syst., May 1998, vol. 1, pp [4] J. Elbornsson, F. Gustafsson, and J. E. Eklund, Amplitude and gain error influence on time error estimation algorithm for time interleaved A/D converter system, in Proc. Int. Conf. Acoust., Speech, Signal Process., May 2002, vol. 2, pp

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Raymond, Numerical Methods for Engineers, Simplified Chinese Translation Edition. Beijing, China: Tsinghua Univ. Press, 2007, pp [20] L. Djerou, M. Batouche, N. Khelil, and A. Zerarka, Towards the best points of interpolation using particles swarm optimization approach, in Proc. IEEE Congr. Evol. Comput., Sep. 2007, pp [21] Y. C. Lim, A new pipelined vector reduction arithmetic unit for FIR filter implementation, Proc. Inst. Elect. Eng. E, Comput. Digit. Tech., vol. 134, no. 4, pp , Jul [22] Y. C. Lim and B. Liu, Pipelined recursive filter with minimum order augmentation, IEEE Trans. Signal Process., vol. 40, no. 7, pp , Jul [23] Y. C. Lim, Parallel and pipelined implementation of injected numerator lattice digital filters, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 7, pp , Jul [24] Y. C. Lim, A new approach for deriving scattered coefficients of pipelined IIR filters, IEEE Trans. Signal Process., vol. 43, no. 10, pp , Oct [25] IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Stand , Jun Yue Xian Zou (S 96 M 00 SM 08) received the Ph.D. degree from the University of Hong Kong, Shatin, Hong Kong, in She is an Associate Professor with Peking University, Shenzhen, China, and is the Director of the Advanced Digital Signal Processing Laboratory in the School of Computer and Information Engineering, Peking University Shenzhen Graduate School. Since 2005, she has been actively involved in the national and international academic activities. She serves as the Evaluation/Peer Review Expert for National Natural Science Foundation of China, Shenzhen Bureau of Science Technology and Information, and the Paper Reviewer for several IEEE journals and international conferences. She is currently working on a high-speed and high-resolution analog-to-digital converter research project. Her research work includes digital filter design, adaptive filtering, array signal processing, and video signal processing. Shang-Liang Zhang received the B.Eng. degree in weapon systems engineering from Nanjing University of Science and Technology, Nanjing, China, in He is working toward the M.Sc. degree in the School of Electronics Engineering and Computer Science, Peking University, Shenzhen, China. His research interests include high-speed data conversion and mixed-signal circuit and system design. Yong Ching Lim (S 79 M 82 SM 92 F 00) received the A.C.G.I. and B.Sc. degrees in electrical engineering in 1977 and the D.I.C. and Ph.D. degrees in electrical engineering in 1980 from Imperial College, University of London, London, U.K. From 1982 to 2003, he was with the Department of Electrical Engineering, National University of Singapore. From 1980 to 1982, he was a National Research Council Research Associate with the Naval Postgraduate School, Monterey, CA. Since 2003, he has been with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, where he is currently a Professor. His research interests include digital signal processing and very large scale integration circuits and system design. Dr. Lim also served as an Associate Editor for Circuits, Systems, and Signal Processing from 1993 to Xiao Chen received the B.Eng. degree in electronic information science and technology from Beijing University of Chemical Technology, Beijing, China, in 2004 and the M.Sc. degrees in microelectronics and solid-state electronics from Peking University, Shenzhen, China, in His research interests include time-interleaved analog-to-digital conversion and digital signal processing.