Quiet Series Octal D Flip-Flop with TRI-STATE Outputs

Transcription

1 574 54ACTQ 74ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs General Description The ACQ ACTQ574 is a high-speed low-power octal D- type flip-flop with a buffered Common Clock (CP) and a buffered common Output Enable (OE) The information presented to the D inputs is stored in the flip-flops on the LOW-to- HIGH clock (CP) traition ACQ ACTQ574 utilizes Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance FACT Quiet SeriesTM features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance The ACQ ACTQ574 is functionally identical to the ACTQ374 but with different pin-out Logic s IEEE IEC Features March 1993 Y ICC and I OZ reduced by 50% Y Guaranteed simultaneous switching noise level and dynamic threshold performance Y Guaranteed pin-to-pin skew AC performance Y Inputs and outputs on opposite sides of the package allowing easy interface with microprocessors Y Functionally identical to the ACQ ACTQ374 Y TRI-STATE outputs drive bus lines or buffer memory address registers Y Outputs source sink 24 ma Y Faster prop delays than the standard AC ACT574 Y 4 k minimum ESD immunity Y Standard Military Drawing (SMD) ACTQ Connection Diagrams Pin Assignment for DIP Flatpak and SOIC ACTQ 74ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs TL F TL F TL F Pin Names D 0 D 7 CP OE O 0 O 7 Description Data Inputs Clock Pulse Input TRI-STATE Output Enable Input TRI-STATE Outputs Pin Assignment for LCC TRI-STATE is a registered trademark of National Semiconductor Corporation FACTTM FACT Quiet SeriesTM and GTOTM are trademarks of National Semiconductor Corporation TL F C1995 National Semiconductor Corporation TL F RRD-B30M75 Printed in U S A

2 Functional Description The ACQ ACTQ574 coists of eight edge-triggered flipflops with individual D-type inputs and TRI-STATE true outputs The buffered clock and buffered Output Enable are common to all flip-flops The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) traition With the Output Enable (OE) LOW the contents of the eight flip-flops are available at the outputs When OE is HIGH the outputs go to the high impedance state Operation of the OE input does not affect the state of the flipflops Function Table Inputs Internal Outputs OE CP D Q O N Function H H L NC Z Hold H H H NC Z Hold H L L L Z Load H L H H Z Load L L L L L Data Available L L H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data H e HIGH oltage Level L e LOW oltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Traition NC e No Change Logic Diagram TL F Please note that this diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays 2

3 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specificatio Supply oltage ( CC ) b0 5 to a7 0 DC Input Diode Current (I IK ) I eb0 5 b20 ma I e CC a 0 5 a20 ma DC Input oltage ( I ) b0 5 to CC a 0 5 DC Output Diode Current (I OK ) O eb0 5 b20 ma O e CC a 0 5 a20 ma DC Output oltage ( O ) b0 5 to CC a 0 5 DC Output Source or Sink Current (I O ) g50 ma DC CC or Ground Current per Output Pin (I CC or I GND ) g50 ma Storage Temperature (T STG ) b65 Ctoa150 C DC Latch-Up Source or Sink Current g300 ma Junction Temperature (T J ) CDIP 175 C PDIP 140 C Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specificatio should be met without exception to eure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of FACTTM circuits outside databook specificatio Recommended Operating Conditio Supply oltage ( CC ) ACQ 2 0 to 6 0 ACTQ 4 5 to 5 5 Input oltage ( I ) 0to CC Output oltage ( O ) 0to CC Operating Temperature (T A ) ACTQ b40 Ctoa85 C 54ACTQ b55 Ctoa125 C Minimum Input Edge Rate D Dt ACQ Devices IN from 30% to 70% of CC CC m Minimum Input Edge Rate D Dt ACTQ Devices IN from 0 8 to 2 0 CC m Note All commercial packaging is not recommended for applicatio requiring greater than 2000 temperature cycles from b40 C toa125 C DC Electrical Characteristics for ACQ Family Devices CC () T A ea25 C Typ T A e b40 Ctoa85 C Guaranteed Limits Units Conditio IH Minimum High Level OUT e 0 1 Input oltage or CC b IL Maximum Low Level OUT e 0 1 Input oltage or CC b OH Minimum High Level I OUT eb50 ma Output oltage IN e IL or IH b12 ma I OH b24 ma b24 ma OL Maximum Low Level I OUT e 50 ma Output oltage IN e IL or IH ma I OL 24 ma ma All outputs loaded thresholds on input associated with output under test 3

4 DC Electrical Characteristics for ACQ Family Devices (Continued) I IN CC () T A ea25 C Typ T A e b40 Ctoa85 C Guaranteed Limits Units Conditio Maximum Input 5 5 g0 1 g1 0 ma I e CC GND Leakage Current (Note 1) I OLD Minimum Dynamic ma OLD e 1 65 Max I OHD Output Current 5 5 b75 ma OHD e 3 85 Min I CC Maximum Quiescent ma IN e CC Supply Current or GND (Note 1) I OZ Maximum TRI-STATE I (OE) e IL IH Leakage Current 5 5 g0 25 g2 5 ma I e CC GND O e CC GND OLP Quiet Output Figures Maximum Dynamic OL (Notes 2 3) OL IHD ILD Quiet Output Figures b0 6 b1 2 Minimum Dynamic OL (Notes 2 3) Minimum High Level Dynamic Input oltage Maximum Low Level Dynamic Input oltage (Notes 2 4) (Notes 2 4) Maximum test duration 2 0 ms one output loaded at a time Note 1 I IN and I CC 3 0 are guaranteed to be less than or equal to the respective limit 5 5 CC Note 2 Plastic DIP package Note 3 Max number of outputs defined as (n) Data inputs are driven 0 to 5 One output GND Note 4 Maximum number of data inputs (n) switching (nb1) inputs switching 0 to 5 ( ACQ) Input-under-test switching 5 to threshold ( ILD ) 0 to threshold ( IHD ) f e 1 MHz 4

5 DC Electrical Characteristics for ACTQ Family Devices CC () 74ACTQ 54ACTQ 74ACTQ T A ea25 C Typ T A e T A e Units b55 Ctoa125 C b40 Ctoa85 C Guaranteed Limits Conditio IH Minimum High Level OUT e 0 1 Input oltage or CC b 0 1 IL Maximum Low Level OUT e 0 1 Input oltage or CC b 0 1 OH Minimum High Level I OUT eb50 ma Output oltage IN e IL or IH b24 ma I OH b24 ma OL Maximum Low Level Output oltage I OUT e 50 ma IN e IL or IH ma I OL 24 ma I IN Maximum Input Leakage Current 5 5 g0 1 g1 0 g1 0 ma I e CC GND I OZ Maximum TRI-STATE Leakage Current 5 5 g0 25 g5 0 g2 5 ma I e IL IH O e CC GND I CCT Maximum I CC Input ma I e CC b 2 1 I OLD Minimum Dynamic ma OLD e 1 65 Max I OHD Output Current 5 5 b50 b75 ma OHD e 3 85 Min I CC OLP OL IHD ILD Maximum Quiescent ma IN e CC Supply Current or GND (Note 1) Quiet Output Figures Maximum Dynamic OL (Notes 2 3) Quiet Output Figures b0 6 b1 2 Minimum Dynamic OL (Notes 2 3) Minimum High Level Dynamic Input oltage Maximum Low Level Dynamic Input oltage All outputs loaded thresholds on input associated with output under test (Notes 2 4) (Notes 2 4) Maximum test duration 2 0 ms one output loaded at a time Note 1 I CC for 54ACTQ 25 C is identical to 74ACTQ 25 C Note 2 Plastic DIP package Note 3 Max number of outputs defined as (n) Data inputs are driven 0 to 3 One output GND Note 4 Max number of data inputs (n) switching (nb1) inputs switching 0 to 3 ( ACTQ) Input-under-test switching 3 to threshold ( ILD ) 0 to threshold ( IHD ) f e 1 MHz 5

6 AC Electrical Characteristics T CC T A ea25 C A eb40 C to a85 C () C L e 50 pf C L e 50 pf Min Typ Max Min Max f max Maximum Clock Frequency t PLH Propagation Delay t PHL CP to O n t PZH Output Enable Time t PZL t PHZ Output Disable Time t PLZ t OSHL Output to Output Skew t OSLH CP to O n Units MHz oltage Range 5 0 is 5 0 g0 5 oltage Range 3 3 is 3 3 g0 3 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction either HIGH to LOW (t OSHL ) or LOW to HIGH (t OSLH ) guaranteed by design AC Operating Requirements T CC T A ea25 C A eb40 C to a85 C () C L e 50 pf C L e 50 pf Typ Guaranteed Minimum t S Setup Time HIGH or LOW D n to CP t H Hold Time HIGH or LOW D n to CP t W CP Pulse Width HIGH or LOW oltage Range 5 0 is 5 0 g0 5 oltage Range 3 3 is 3 3 g0 3 Units 6

7 AC Electrical Characteristics 74ACTQ 54ACTQ 74ACTQ T CC T A ea25 C A eb55 C T A eb40 C to a125 C to a85 C Units () C L e 50 pf C L e 50 pf C L e 50 pf Min Typ Max Min Max Min Max f max Maximum Clock Frequency MHz t PLH Propagation Delay t PHL CP to O n t PZH t PZL t PHZ t PLZ t OSHL t OSLH Output Enable Time Output Disable Time Output to Output Skew CP to O n oltage Range 5 0 is 5 0 g0 5 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction either HIGH to LOW (t OSHL ) or LOW to HIGH (t OSLH ) guaranteed by design AC Operating Requirements t S t H t W Setup Time HIGH or LOW D n to CP Hold Time HIGH or LOW D n to CP CP Pulse Width HIGH or LOW oltage Range 5 0 is 5 0 g0 5 CC () 74ACTQ 54ACTQ 74ACTQ T A ea25 C C L e 50 pf Typ T A eb55 C T A eb40 C to a125 C to a85 C Units C L e 50 pf C L e 50 pf Guaranteed Minimum Capacitance Typ Units Conditio C IN Input Capacitance 4 5 pf CC e OPEN C PD Power Dissipation Capacitance 40 0 pf CC e 5 0 7

8 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests The following is a brief description of the setup used to measure the noise characteristics of FACT Equipment Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure 1 erify Test Fixture Loading Standard Load 50 pf 500X 2 Deskew the word generator so that no two channels have greater than 150 ps skew between them This requires that the oscilloscope be deskewed first Swap out the channels that have more than 150 ps of skew until all channels being used are within 150 ps It is important to deskew the word generator channels before testing This will eure that the outputs switch simultaneously 3 Terminate all inputs and outputs to eure proper loading of the outputs and that the input levels are at the correct voltage 4 Set CC to Set the word generator to toggle all but one output at a frequency of 1 MHz Greater frequencies will increase DUT heating and affect the results of the measurement TL F FIGURE 1 Quiet Output Noise oltage Waveforms Note A OH and OLP are measured with respect to ground reference Note B Input pulses have the following characteristics f e 1 MHz t r e 3 t f e 3 skew k 150 ps 6 Set the word generator input levels at 0 LOW and 3 HIGH for ACT devices and 0 LOW and 5 HIGH for AC devices erify levels with a digital volt meter OLP OL and OHP OH Determine the quiet output pin that demotrates the greatest noise levels The worst case pin will usually be the furthest from the ground pin Monitor the output voltages using a 50X coaxial cable plugged into a standard SMB type connector on the test fixture Do not use an active FET probe Measure OLP and OL on the quiet output during the HL traition Measure OHP and OH on the quiet output during the LH traition erify that the GND reference recorded on the oscilloscope has not drifted to eure the accuracy and repeatability of the measurements ILD and IHD Monitor one of the switching outputs using a 50X coaxial cable plugged into a standard SMB type connector on the test fixture Do not use an active FET probe First increase the input LOW voltage level IL until the output begi to oscillate Oscillation is defined as noise on the output LOW level that exceeds IL limits or on output HIGH levels that exceed IH limits The input LOW voltage level at which oscillation occurs is defined as ILD Next increase the input HIGH voltage level on the word generator IH until the output begi to oscillate Oscillation is defined as noise on the output LOW level that exceeds IL limits or on output HIGH levels that exceed IH limits The input HIGH voltage level at which oscillation occurs is defined as IHD erify that the GND reference recorded on the oscilloscope has not drifted to eure the accuracy and repeatability of the measurements FIGURE 2 Simultaneous Switching Test Circuit TL F

9 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74ACTQ 574 P C QR Temperature Range Family ecommercial 74ACTQeCommercial TTL-Compatible 54ACTQeMilitary TTL-Compatible Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) Special ariatio X e Devices shipped in 13 reels QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing shipped in tubes Temperature Range CeCommercial (b40 Ctoa85 C) MeMilitary (b55 Ctoa125 C) 9

10 Physical Dimeio inches (millimeters) 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 10

11 Physical Dimeio inches (millimeters) (Continued) 20-Lead Small Outline Integrated Circuit (S) NS Package Number M20B 20-Lead Plastic Dual-In-Line Package (P) NS Package Number N20B 11

12 574 54ACTQ 74ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs Physical Dimeio inches (millimeters) (Continued) Lit Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with itructio for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd Hong Kong Ltd Do Brazil Ltda (Australia) Pty Ltd 2900 Semiconductor Drive Livry-Gargan-Str 10 Sumitomo Chemical 13th Floor Straight Block Rue Deputado Lacorda Franco Building 16 P O Box D F4urstenfeldbruck Engineering Center Ocean Centre 5 Canton Rd 120-3A Business Park Drive Santa Clara CA Germany Bldg 7F Tsimshatsui Kowloon Sao Paulo-SP Monash Business Park Tel 1(800) Tel (81-41) Nakase Mihama-Ku Hong Kong Brazil Nottinghill Melbourne TWX (910) Telex Chiba-City Tel (852) Tel (55-11) ictoria 3168 Australia Fax (81-41) 35-1 Ciba Prefecture 261 Fax (852) Telex NSBR BR Tel (3) Tel (043) Fax (55-11) Fax (3) Fax (043) National does not assume any respoibility for use of any circuitry described no circuit patent licees are implied and National reserves the right at any time without notice to change said circuitry and specificatio