74ACQ273 54ACTQ 74ACTQ273 Quiet Series Octal D Flip-Flop

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1 273 54ACTQ 74ACTQ273 Quiet Series Octal D Flip-Flop General Description The AC ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock traition is traferred to the corresponding flip-flop s Q output All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device is useful for applicatio where the true output only is required and the Clock and Master Reset are common to all storage elements The ACQ ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic Logic s IEEE IEC March 1993 threshold performance FACT Quiet SeriesTM features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance Features Y ICC reduced by 50% Y Guaranteed simultaneous switching noise level and dynamic threshold performance Y Guaranteed pin-to-pin skew AC performance Y Improved latch-up immunity Y Buffered common clock and asynchronous master reset Y Outputs source sink 24 ma Y Faster prop delays than the standard AC ACT273 Y 4 k minimum ESD immunity Y Standard Military Drawing (SMD) ACTQ Connection Diagrams Pin Assignment for DIP Flatpak and SOIC ACTQ 74ACTQ273 Quiet Series Octal D Flip-Flop TL F TL F TL F Pin Names D 0 D 7 MR CP Q 0 Q 7 Description Data Inputs Master Reset Clock Pulse Input Data Outputs Pin Assignment for LCC FACTTM FACT Quiet SeriesTM and GTOTM are trademarks of National Semiconductor Corporation TL F C1995 National Semiconductor Corporation TL F RRD-B30M75 Printed in U S A

2 Mode Select-Function Table Operating Mode Inputs Outputs MR CP D n Q n Reset (Clear) L X X L Load 1 H L H H Load 0 H L L L H e HIGH oltage Level L e LOW oltage Level X e Immaterial L e LOW-to-HIGH Traition Logic Diagram TL F Please note that this diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays 2

3 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specificatio Supply oltage ( CC ) b0 5 to a7 0 DC Input Diode Current (I IK ) I eb0 5 b20 ma I e CC a 0 5 a20 ma DC Input oltage ( I ) b0 5 to CC a 0 5 DC Output Diode Current (I OK ) O eb0 5 b20 ma O e CC a 0 5 a20 ma DC Output oltage ( O ) b0 5 to CC a 0 5 DC Output Source or Sink Current (I O ) g50 ma DC CC or Ground Current per Output Pin (I CC or I GND ) g50 ma Storage Temperature (T STG ) b65 Ctoa150 C DC Latch-up Source or Sink Current g300 ma Junction Temperature (T J ) CDIP 175 C PDIP 140 C Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specificatio should be met without exception to eure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of FACT circuits outside databook specificatio DC Characteristics for ACQ Family Devices CC () Typ Recommended Operating Conditio Supply oltage ( CC ) ACQ 2 0 to 6 0 ACTQ 4 5 to 5 5 Input oltage ( I ) 0to CC Output oltage ( O ) 0to CC Operating Temperature (T A ) (Note 2) ACTQ b40 Ctoa85 C 54ACTQ b55 Ctoa125 C Minimum Input Edge Rate D Dt ACQ Devices IN from 30% to 70% of CC CC m Minimum Input Edge Rate D Dt ACTQ Devices IN from 0 8 to 2 0 CC m Note All commercial packaging is not recommended for applicatio requiring greater than 2000 temperature cycles from b40 C toa125 C T A e b40 Ctoa85 C Guaranteed Limits Units Conditio IH Minimum High Level OUT e 0 1 Input oltage or CC b IL Maximum Low Level OUT e 0 1 Input oltage or CC b OH Minimum High Level I OUT eb50 ma Output oltage IN e IL or IH b12 ma I OH b24 ma b24 ma OL Maximum Low Level I OUT e 50 ma Output oltage I IN IN e IL or IH ma I OL 24 ma ma Maximum Input 5 5 g0 1 g1 0 ma I e CC GND Leakage Current (Note 1) All outputs loaded thresholds on input associated with output under test Note 1 I IN and I CC 3 0 are guaranteed to be less than or equal to the respective limit 5 5 CC 3

4 DC Characteristics for ACQ Family Devices (Continued) CC () Typ T A e b40 Ctoa85 C Guaranteed Limits Units Conditio I OLD Minimum Dynamic ma OLD e 1 65 Max I OHD Output Current 5 5 b75 ma OHD e 3 85 Min I CC OLP OL IHD ILD Maximum Quiescent ma IN e CC Supply Current or GND (Note 1) Quiet Output Figures Maximum Dynamic OL (Notes 2 3) Quiet Output Figures b0 6 b1 2 Minimum Dynamic OL (Notes 2 3) Minimum High Level Dynamic Input oltage Maximum Low Level Dynamic Input oltage All outputs loaded thresholds on input associated with output under test (Notes 2 4) (Notes 2 4) Maximum test duration 2 0 ms one output loaded at a time Note 1 I IN and I CC 3 0 are guaranteed to be less than or equal to the respective limit 5 5 CC Note 2 Plastic DIP package Note 3 Max number of outputs defined as (n) Data inputs are driven 0 to 5 One output GND Note 4 Max number of Data Inputs (n) switching (n b 1) Inputs switching 0 to 5 ( ACQ) Input-under-test switching 5 to threshold ( ILD ) 0 to threshold ( IHD )fe1 MHz DC Characteristics for ACTQ Family Devices 74ACTQ 54ACTQ 74ACTQ CC T A e T A e () b55 Ctoa125 C b40 Ctoa85 C Typ Guaranteed Limits Units Conditio IH Minimum High Level OUT e 0 1 Input oltage or CC b 0 1 IL Maximum Low Level OUT e 0 1 Input oltage or CC b 0 1 OH Minimum High Level I OUT eb50 ma Output oltage IN e IL or IH I OH b24 ma b24 ma OL Maximum Low Level Output oltage I OUT e 50 ma I IN I CCT Maximum Input Leakage Current Maximum I CC Input IN e IL or IH I OL 24 ma ma 5 5 g0 1 g1 0 g1 0 ma I e CC GND ma I e CC b 2 1 All outputs loaded thresholds on input associated with output under test Maximum test duration 2 0 ms one output loaded at a time 4

5 DC Characteristics for ACTQ Family Devices (Continued) 74ACTQ 54ACTQ 74ACTQ CC T A e T A e () b55 Ctoa125 C b40 Ctoa85 C Typ Guaranteed Limits Units Conditio I OLD Minimum Dynamic ma OLD e 1 65 Max I OHD Output Current 5 5 b50 b75 ma OHD e 3 85 Min I CC OLP OL IHD ILD Maximum Quiescent ma IN e CC Supply Current or GND (Note 1) Quiet Output Figures Maximum Dynamic OL (Notes 2 3) Quiet Output Figures b0 6 b1 2 Minimum Dynamic OL (Notes 2 3) Minimum High Level Dynamic Input oltage Maximum Low Level Dynamic Input oltage (Notes 2 4) (Notes 2 4) Maximum test duration 2 0 ms one output loaded at a time Note 1 I CC for 54ACTQ 25 C is identical to 74ACTQ 25 C Note 2 Plastic DIP package Note 3 Max number of outputs defined as (n) n b 1 Data inputs are driven 0 to 3 one output GND Note 4 Max number of Data Inputs (n) switching (n b 1) Inputs switching 0 to 3 ( ACTQ) Input-under-test switching 3 to threshold ( ILD ) 0 to threshold ( IHD )fe1 MHz AC Electrical Characteristics T CC A eb40 C to a85 C () C L e 50 pf C L e 50 pf Min Typ Max Min Max f max Maximum Clock Frequency t PLH Propagation Delay CP to Q n t PHL Propagation Delay CP to Q n t PHL Propagation Delay MR to Q n t OSHL Output to Output t OSLH Skew oltage Range 5 0 is 5 0 g0 5 oltage Range 3 3 is 3 3 g0 3 Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device The specification applies to any outputs switching in the same direction either HIGH to LOW (t OSHL ) or LOW to HIGH (t OSLH ) guaranteed by design Not tested Units MHz 5

6 AC Operating Requirements T CC A eb40 C to a85 C () C L e 50 pf C L e 50 pf Typ Guaranteed Minimum t s Setup Time HIGH or LOW D n to CP t h Hold Time HIGH or LOW D n to CP t w Clock Pulse Width HIGH or LOW t w MR Pulse Width HIGH or LOW t w Recovery Time MR to CP Units oltage Range 5 0 is 5 0 g0 5 oltage Range 3 3 is 3 3 g0 3 AC Electrical Characteristics f max t PHL t PLH t PHL t OSHL t OSLH Maximum Clock Frequency Propagation Delay Clock to Output Propagation Delay MR to Output Output to Output Skew Data to Ouput CC () 74ACTQ 54ACTQ 74ACTQ T A eb55 C T A eb40 C to a125 C to a85 C Units C L e 50 pf C L e 50 pf C L e 50 pf Min Typ Max Min Max Min Max MHz oltage Range 5 0 is 5 0 g0 5 Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device The specification applies to any outputs switching in the same direction either HIGH to LOW (t OSHL ) or LOW to HIGH (t OSLH ) guaranteed by design Not tested 6

7 AC Operating Requirements t s t h t w t w t rec Setup Time HIGH or LOW Data to CP Hold Time HIGH or LOW Data to CP Clock Pulse Width HIGH or LOW MR Pulse Width HIGH or LOW Recovery Time MR to CP oltage Range 5 0 is 5 0 g0 5 CC () 74ACTQ 54ACTQ 74ACTQ C L e 50 pf Typ T A eb55 C T A eb40 C to a125 C to a85 C Units C L e 50 pf C L e 50 pf Guaranteed Minimum b Capacitance Typ Units Conditio C IN Input Capacitance 4 5 pf CC e OPEN C PD Power Dissipation Capacitance 40 0 pf CC e 5 0 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests The following is a brief description of the setup used to measure the noise characteristics of FACT Equipment Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure 1 erify Test Fixture Loading Standard Load 50 pf 500X 2 Deskew the word generator so that no two channels have greater than 150 ps skew between them This requires that the oscilloscope be deskewed first Swap out the channels that have more than 150 ps of skew until all channels being used are within 150 ps It is important to deskew the word generator channels before testing This will eure that the outputs switch simultaneously 3 Terminate all inputs and outputs to eure proper loading of the outputs and that the input levels are at the correct voltage 4 Set CC to Set the word generator to toggle all but one output at a frequency of 1 MHz Greater frequencies will increase DUT heating and affect the results of the measurement TL F FIGURE 1 Quiet Output Noise oltage Waveforms Note A OH and OLP are measured with respect to ground reference Note B Input pulses have the following characteristics f e 1 MHz t r e 3 t f e 3 skew k 150 ps 6 Set the word generator input levels at 0 LOW and 3 HIGH for ACT devices and 0 LOW and 5 HIGH for AC devices erify levels with a digital volt meter 7

8 FACT Noise Characteristics (Continued) OLP OL and OHP OH Determine the quiet output pin that demotrates the greatest noise levels The worst case pin will usually be the furthest from the ground pin Monitor the output voltages using a 50X coaxial cable plugged into a standard SMB type connector on the test fixture Do not use an active FET probe Measure OLP and OL on the quiet output during the HL traition Measure OHP and OH on the quiet output during the LH traition erify that the GND reference recorded on the oscilloscope has not drifted to eure the accuracy and repeatability of the measurements ILD and IHD Monitor one of the switching outputs using a 50X coaxial cable plugged into a standard SMB type connector on the test fixture Do not use an active FET probe First increase the input LOW voltage level IL until the output begi to oscillate Oscillation is defined as noise on the output LOW level that exceeds IL limits or on output HIGH levels that exceed IH limits The input LOW voltage level at which oscillation occurs is defined as ILD Next increase the input HIGH voltage level on the word generator IH until the output begi to oscillate Oscillation is defined as noise on the output LOW level that exceeds IL limits or on output HIGH levels that exceed IH limits The input HIGH voltage level at which oscillation occurs is defined as IHD erify that the GND reference recorded on the oscilloscope has not drifted to eure the accuracy and repeatability of the measurements FIGURE 2 Simultaneous Switching Test Circuit TL F Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 74ACTQ 273 P C QR Temperature Range Family Special ariatio e Commercial X e Device shipped in 13 reels 74ACTQ e Commercial TTL-Compatible QR e Commercial grade device 54ACTQ e Military TTL-Compatible with burn-in Device Type QB e Military grade device with environmental and burn-in Package Code processing shipped in tubes P e Plastic DIP Temperature Range D e Ceramic DIP C e Commercial (b40 Ctoa85 C) F e Flatpak M e Military (b55 Ctoa125 C) L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline Package (SOIC) 8

9 Physical Dimeio inches (millimeters) 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 9

10 Physical Dimeio inches (millimeters) (Continued) 20-Lead Small Outline Integrated Circuit (S) NS Package Number M20B 20-Lead Plastic Dual-In-Line Package (P) NS Package Number N20B 10

11 11

12 273 54ACTQ 74ACTQ273 Quiet Series Octal D Flip-Flop Physical Dimeio inches (millimeters) (Continued) Lit Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with itructio for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd Hong Kong Ltd Do Brazil Ltda (Australia) Pty Ltd 2900 Semiconductor Drive Livry-Gargan-Str 10 Sumitomo Chemical 13th Floor Straight Block Rue Deputado Lacorda Franco Building 16 P O Box D F4urstenfeldbruck Engineering Center Ocean Centre 5 Canton Rd 120-3A Business Park Drive Santa Clara CA Germany Bldg 7F Tsimshatsui Kowloon Sao Paulo-SP Monash Business Park Tel 1(800) Tel (81-41) Nakase Mihama-Ku Hong Kong Brazil Nottinghill Melbourne TWX (910) Telex Chiba-City Tel (852) Tel (55-11) ictoria 3168 Australia Fax (81-41) 35-1 Ciba Prefecture 261 Fax (852) Telex NSBR BR Tel (3) Tel (043) Fax (55-11) Fax (3) Fax (043) National does not assume any respoibility for use of any circuitry described no circuit patent licees are implied and National reserves the right at any time without notice to change said circuitry and specificatio

54AC 74AC138 54ACT 74ACT138 1-of-8 Decoder Demultiplexer

54AC 74AC138 54ACT 74ACT138 1-of-8 Decoder Demultiplexer General Description The AC ACT138 is a high-speed 1-of-8 decoder demultiplexer This device is ideally suited for high-speed bipolar memory chip