Outputs 74VHC245 74VHCT245. Octal Bidirectional Transceiver with TRI-STATE Outputs
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1 October HC245 74HCT245 Octal Bidirectional Traceiver with TRI-STATE Outputs General Description The HC HCT245 is an advanced high speed CMOS octal bus traceiver fabricated with silicon gate CMOS technology It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation The HC245 is intended for bidirectional asynchronous communication between data busses The direction of data tramission is determined by the level of the T R input The enable input can be used to disable the device so that the busses are effectively isolated All inputs are equipped with protection circuits agait static discharge Commercial Package Number Features High Noise Immunity HC NIH e NIL e 28% CC (Min) HCT IH e 2 0 IL e 0 8 Power Down Protection HC Inputs Only HCT Inputs and Outputs Low Noise HC OLP e 0 9 (typ) HCT OLP e 1 1 (typ) Low Power Dissipation I CC e 4 ma (Max) T a e 25 C Balanced Propagation Delays tplh j t phl Pin and Function Compatible with 74HC HCT245 Package Description 74HC245M M20B 20 Lead Molded JEDEC SOIC 74HC245SJ M20D 20 Lead Molded EIAJ SOIC 74HC245MSC MSC20 20 Lead Molded EIAJ Type 1 SSOP 74HC245MTC MTC20 20 Lead Molded JEDEC Type 1 TSSOP 74HC245N N20A 20 Lead Molded DIP 74HCT245M M20B 20 Lead Molded JEDEC SOIC 74HCT245SJ M20D 20 Lead Molded EIAJ SOIC 74HCT245MTC MTC20 20 Lead Molded JEDEC Type 1 TSSOP 74HCT245N N20A 20 Lead Molded DIP 74HC245 74HCT245 Octal Bidirectional Traceiver with TRI-STATE Outputs Note Surface mount packages are also available on Tape and Reel Specify by appending the suffix letter X to the ordering code EIAJ Type 1 SSOP available on Tape and Reel only order MSCX Logic IEEE IEC Connection Diagram Pin Assignment for DIP SSOP TSSOP and SOIC Pin Names OE T R A 0 A 7 B 0 B 7 Pin Description Description Output Enable Input Tramit Receive Input Side A Inputs or TRI-STATE Outputs Side B Inputs or TRI-STATE Outputs TL F TRI-STATE is a registered trademark of National Semiconductor Corporation TL F Truth Table OE Inputs T R Outputs L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State H e HIGH oltage Level X e Immaterial L e LOW oltage Level C1995 National Semiconductor Corporation TL F RRD-B30M125 Printed in U S A
2 Absolute Maximum Ratings (Note 1) Supply oltage ( CC ) DC Input oltage ( IN ) (T R OE) DC Output oltage ( OUT ) HC HCT Input Diode Current (I IK ) (T R OE) Output Diode Current (I OK ) (HC) (HCT) DC Output Current (I OUT ) DC CC GND Current (I CC ) Storage Temperature (T STG ) Lead Temperature (T L ) (Soldering 10 seconds) OUT l CC only if output is in H or Z state b0 5 to a7 0 b0 5 to 7 0 b0 5 to CC a 0 5 b0 5 to 7 0 b20 ma g20 ma b20 ma g25 ma g75 ma b65 Ctoa150 C 260 C DC Characteristics for HC Family Devices CC () 74HC Note 1 Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired The databook specificatio should be met without exception to eure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation outside databook specificatio Recommended Operating Conditio Supply oltage ( CC ) HC 2 0 to 5 5 HCT 4 5 to 5 5 Input oltage ( IN )(T R OE) 0 to 5 5 Output oltage ( OUT ) 0to CC Operating Temperature (T OPR ) 74 HC HCT b40 Ctoa85 C Input Rise and Fall Time (t r t f ) CC e 3 3 g0 3 (HC only) 0 E 100 CC e 5 0 g0 5 0 E 20 74HC T T A e 25 C A eb40 C to a85 C Min Typ Max Min Max IH High Level Input oltage CC 0 7 CC IL Low Level Input oltage CC 0 3 CC Units Conditio OH High Level Output IN e IH I OH eb50 ma oltage or IL I OH eb4ma I OH eb8ma OL Low Level Output IN e IH I OL e 50 ma oltage or IL I OL e 4mA I OL e 8mA I OZ TRI-STATE Output Off- IN e CC or GND State Current 5 5 g0 25 g2 5 ma OUT e CC or GND IN OE e IH or IL I IN Input Leakage Current (T R OE) g0 1 g1 0 ma IN e 5 5 or GND I CC Quiescent Supply Current ma IN e CC or GND 2
3 DC Characteristics for HC Family Devices 74HC CC T A e 25 C Units Conditio () Typ Limits OLP Quiet Output Maximum Dynamic OL OL Quiet Output Minimum Dynamic OL 5 0 b0 9 b1 2 IHD Minimum High Level Dynamic Input oltage ILD Maximum Low Level Dynamic Input oltage guaranteed by design DC Characteristics for HCT Family Devices CC () 74HCT T A e 25 C 74HCT T A eb40 C to a85 C Min Typ Max Min Max IH High Level Input oltage IL Low Level Input oltage Units Conditio OH High Level IN e IH I OH eb50 ma Output oltage or IL IOH eb8ma OL Low Level IN e IH I OL e 50 ma Output oltage or IL IOL e 8mA I OZ TRI-STATE Output IN e CC or GND Off-State Current 5 5 g0 25 g2 5 ma OUT e CC or GND IN OE e IH or IL I IN Input Leakage (T R OE) Current g0 1 g1 0 ma IN e 5 5 or GND I CC Quiescent Supply Current ma IN e CC or GND I CCT Maximum I CC Input IN e ma Other Inputs e CC or GND I OPD Output Leakage Current (Power 0 0 a0 5 a5 0 ma OUT e 5 5 Down State) 3
4 DC Characteristics for HCT Family Devices OLP Quiet Output Maximum Dynamic OL 74HCT CC T A e 25 C Units Conditio () Typ Limits OL Quiet Output Minimum b1 1 b1 6 Dynamic OL IHD Minimum High Level 2 0 Dynamic Input oltage ILD Maximum Low Level 0 8 Dynamic Input oltage guaranteed by design AC Electrical Characteristics for HC Family Devices CC () 74HC T A e 25 C 74HC T A eb40 C to a85 C Min Typ Max Min Max Units Conditio t PLH Propagation Delay Time 3 3 g C L e 15 pf t PHL CL e 50 pf 5 0 g C L e 15 pf t PZL TRI-STATE Output Enable 3 3 g R L e 1kX C L e15 pf t PZH Time CL e 50 pf 5 0 g C L e 15 pf t PLZ TRI-STATE Output 3 3 g R L e 1kX C L e50 pf t PHZ Disable Time 5 0 g t OSLH Output to Output Skew 3 3 g (Note 1) t OSHL 5 0 g CL e 50 pf C IN (T R OE) Input Capacitance pf CC e Open C I O Output Capacitance 8 pf CC e 5 0 C PD Power Dissipation Capacitance 21 pf (Note 2) Note 1 guaranteed by design t OSLH e lt PLH max b t PLH minl t OSHL e lt PHL max b t PHL minl Note 2 C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load Average operating current can be obtained by the equation I CC (opr ) e C PD CC f IN a I CC 8 (per Bit) 4
5 AC Electrical Characteristics for HCT Family Devices CC () 74HCT T A e 25 C 74HCT T A eb40 C to a85 C Min Typ Max Min Max Units Conditio t PLH Propagation Delay Time 5 0 g C L e 15 pf t PHL CL e 50 pf t PZL TRI-STATE Output Enable 5 0 g R L e 1kX C L e15 pf t PZH Time CL e 50 pf t PLZ TRI-STATE Output 5 0 g0 5 t PHZ Disable Time R L e 1kX C L e50 pf t OSLH Output to Output Skew 5 0 g0 5 (Note 1) t OSHL C IN Input Capacitance pf CC e Open C I O Output Capacitance 9 pf CC e 5 0 C PD Power Dissipation Capacitance 23 pf (Note 2) Note 1 guaranteed by design t OSLH e lt PLH max b t PLH minl t OSHL e lt PHL max b t PHL minl Note 2 C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load Average operating current can be obtained by the equation I CC (opr ) e C PD CC f IN a I CC 8 (per Bit) 5
6 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows TL F
7 Physical Dimeio inches (millimeters) 20-Lead Small Outline Integrated Circuit JEDEC SOIC (M) Order Number 74HC245M 74HC245MX 74HCT245M or 74HCT245MX NS Package Number M20B 20-Lead Small Outline Package EIAJ SOIC (SJ) Order Number 74HC245SJ 74HC245SJX 74HCT245SJ or 74HCT245SJX NS Package Number M20D 7
8 Physical Dimeio millimeters (Continued) 20-Lead Plastic EIAJ SSOP Type I (MSC) Order Number 74HC245MSCX NS Package Number MSC20 8
9 Physical Dimeio millimeters (Continued) 20-Lead Plastic JEDEC TSSOP Type I (MTC) Order Number 74HC245MTC 74HC245MTCX 74HCT245MTC or 74HCT245MTCX NS Package Number MTC20 9
10 74HC245 74HCT245 Octal Bidirectional Traceiver with TRI-STATE Outputs Physical Dimeio inches (millimeters) (Continued) 20-Lead (0 300 Wide) Molded Dual-In-Line Package Order Number 74HCT245N NS Package Number N20A LIFE SUPPORT POLIC NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with itructio for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 c com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any respoibility for use of any circuitry described no circuit patent licees are implied and National reserves the right at any time without notice to change said circuitry and specificatio
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74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset General Description The LVQ174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register.
74LVX273 Low Voltage Octal D-Type Flip-Flop
74LVX273 Low Voltage Octal D-Type Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset
74AC08 74ACT08 Quad 2-Input AND Gate
Quad 2-Input AND Gate General Description The AC/ACT08 contains four, 2-input AND gates. Ordering Code: Features I CC reduced by 50% on 74AC only Outputs source/sink 24 ma Device also available in Tape
MM74HC32 Quad 2-Input OR Gate
Quad 2-Input OR Gate General Description The MM74HC32 OR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
MM74HC139 Dual 2-To-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.
74AC138 74ACT138 1-of-8 Decoder/Demultiplexer
1-of-8 Decoder/Demultiplexer General Description The AC/ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The
MM74HC08 Quad 2-Input AND Gate
Quad 2-Input AND Gate General Description The MM74HC08 AND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
Features. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics
CD4001BM CD4001BC Quad 2-Input NOR Buffered B Series Gate CD4011BM CD4011BC Quad 2-Input NAND Buffered B Series Gate General Description These quad gates are monolithic complementary MOS (CMOS) integrated
Features. Y Wide supply voltage range 3V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL compatibility Fan out of 2
CD40192BM CD40192BC Synchronous 4-Bit Up Down Decade Counter CD40193BM CD40193BC Synchronous 4-Bit Up Down Binary Counter General Description These up down counters are monolithic complementary MOS (CMOS)
CD4029BM CD4029BC Presettable Binary Decade Up Down Counter
CD4029BM CD4029BC Presettable Binary Decade Up Down Counter General Description The CD4029BM CD4029BC is a presettable up down counter which counts in either binary or decade mode depending on the voltage
MM74HC138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 2005 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
74ACT825 8-Bit D-Type Flip-Flop
8-Bit D-Type Flip-Flop General Description The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming
9312 DM9312 One of Eight Line Data Selectors Multiplexers
9312 DM9312 One of Eight Line Data Selectors Multiplexers General Description These data selectors multiplexers contain inverter drivers to supply full complementary on-chip binary decoded data selection
74FR244 Octal Buffer/Line Driver with 3-STATE Outputs
74FR244 Octal Buffer/Line Driver with 3-STATE Outputs General Description The 74FR244 is a non-inverting octal buffer and line driver designed to be employed as memory and address driver, clock driver
MM74HCT138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits
93L34 8-Bit Addressable Latch
93L34 8-Bit Addressable Latch General Description The 93L34 is an 8-bit addressable latch designed for general purpose storage applications in digital systems It is a multifunctional device capable of
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-
54LS352 DM74LS352 Dual 4-Line to 1-Line Data Selectors Multiplexers
54LS352 DM74LS352 Dual 4-Line to 1-Line Data Selectors Multiplexers General Description Each of these data selectors multiplexers contains inverters and drivers to supply fully complementary on-chip binary
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
74VHC123A Dual Retriggerable Monostable Multivibrator
Dual Retriggerable Monostable Multivibrator General Description The VHC123A is an advanced high speed CMOS Monostable Multivibrator fabricated with silicon gate CMOS technology. It achieves the high speed
CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger
CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger General Description The CD4093B consists of four Schmitt-trigger circuits Each circuit functions as a 2-input NAND gate with Schmitt-trigger action on
74VHC221A Dual Non-Retriggerable Monostable Multivibrator
April 1994 Revised May 1999 74VHC221A Dual Non-Retriggerable Monostable Multivibrator General Description The VHC221A is an advanced high speed CMOS Monostable Multivibrator fabricated with silicon gate
54153 DM54153 DM74153 Dual 4-Line to 1-Line Data Selectors Multiplexers
54153 DM54153 DM74153 Dual 4-Line to 1-Line Data Selectors Multiplexers General Description Each of these data selectors multiplexers contains inverters and drivers to supply fully complementary on-chip
MM74HC4020 MM74HC Stage Binary Counter 12-Stage Binary Counter
February 1984 Revised February 1999 MM74HC4020 MM74HC4040 14-Stage Binary Counter 12-Stage Binary Counter General Description The MM74HC4020, MM74HC4040, are high speed binary ripple carry counters. These
MM74HCT08 Quad 2-Input AND Gate
MM74HCT08 Quad 2-Input AND Gate General Description The MM74HCT08 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS low quiescent