EE451/551: Digital Control. Relationship Between s and z Planes. The Relationship Between s and z Planes 11/10/2011

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1 /0/0 EE45/55: Digital Control Chater 6: Digital Control System Design he Relationshi Between s and Planes As noted reviously: s j e e e e r s j where r e and If an analog system has oles at: s n jn a jd jd n a then r e e e and n d Solving these eqns. for, n and yields: ln r, ln, and n r ln r ln r Relationshi Between s and Planes his imlies that time domain seifiations given for a desired osed-loo system resonse an be translated into desired -domain seifiations, i.e., ole loations, and vie-versa through the familiar s-domain seifiations disussed in Chater 5 Primary stri in s lane (aliasing ours outside this region) Lines of onstant time onstant (above) and damed frequeny (below) Lines of onstant daming ratio Remember: Poles ma reditably under the transform, eros do not!

2 /0/0 Samled time domain resonses, Lines of onstant and in the -lane: and their domain ole loations n t For a signal of the form: Ae os t A d samled with a eriod of, we an redit the loation of the -domain oles, i.e., r, using the following table: Note, as the number of samles er time onstant (or eriod) inreases, i.e., fast samling, the system oles move toward the oint = Design Examle Relating Seifiations Design a osed loo system resonse that arox. a seond order system with eak time, 0.89s, d 4 and settling time s %.4 s. From the ses., n we have the onstraints: and.4 n n Solving these eqns. simultaneously yields n 5 and desired osed-loo oles are loated at: s n jn jd 3.54 j3.54 the CP is given by () s s s s 7.08s5.06 n n Design Examle Relating Seifiations If the system is samled with a eriod of 0.0, n then r e e and d rad 4 his imlies that the disrete CP is given by: r r o hek these results, solve for and n: ln r ln ln r ln n ln r ln Matlab Solution >> s_= [ 3.54+j*3.54, 3.54 j*3.54]; >> =0.0;_=ex(s_*) _ = [ i, i] >>r= abs(_) r = [0.936, 0.936] >>theta= angle(_) theta= [ , ] ] >> delta_=onv([ _()],[ _()]) delta_= [ ] >> eta= log(r)/sqrt(log(r)^+theta^) eta = >> wn=sqrt(log(r)^+theta^)/ wn = >> tau=/abs(real(s_())) tau = 0.85 >> tau/ ans = 4.43 >> d=*i/imag(s_()) d =.7749 >> d/ ans = Comare these ratios to the Samles er able for r and theta, does it make sense?

3 /0/0 Matlab Solution Questions? >> H_=tf(,onv([ _()],[ _()]),) ransfer funtion: ^ Samling time: 0.0 >> ste(h_) Aroximating the sto Plane Maing Sine analog systems an be reresented by differential or integral equations in the time domain, three ommon methods are used to aroximate these forms in the disrete time domain, i.e., forward differene, bakward differene and the traeoidal rule for integration (bilinear transform) Forward differene: ys () yk ( ) yk () sy() s Y() Y() Y() s Aroximating the sto Plane Maing Bakward differene: ys () yk () yk ( ) sy( s) Y Y Y s raeoidal Rule (Bilinear ransform): s See Franklin et. al for derivation details Aliation to Ch5 Controller Design Examle # As shown reviously, the design objetives are met by a omensator of the aroximate form: s Converting this ( s) to using the differening methods with =0.0 0 yields: G ( ) forward s s G ( ) bakward s s G ( ) bilinear s s s ( s) 7 Comaring Ste Resonses While bilinear is tyially the referred method, as you an see for roer samling rates, all three methods give arox. the same result 3

4 /0/0 Aliation to Ch5 Controller Design Examle #4 As shown reviously, the design objetives are met by a PD asade omensator of the aroximate form: G ( s) 6s 8 Converting this ( s) to using the differening methods with =0.0 yields: G ( ) forward s s 0.0 G G ( s) bakward s 0.0 G G ( s) bilinear s Aliation to Ch5 Controller Design Examle #4 he first two results, i.e., and G ( ) are nonausal forward bakward and therefore not imlementable without modifiaton; while the last result is also not ratially imlementable without modifiaton sine its requires an infinite amount of energy at the folding frequeny to due to the ole at, e.g.: Aliation to Ch5 Controller Design Examle #4 o fix these issues we remove oles at and insert oles at 0 as needed to make the Fs ratially imlementable, as shown: forward bakward bilinear Resulting Ste Resonses Be areful on drawing onusions about whih differening method gives better results as we aroximated the original ontroller F G (s) Questions? Emirial Digital PID Controller uning he text rooses the following PID ontroller form: K Ki Kd Sine the -F of the ZOH an be aroximated as: s e s G ZOH () s e s the ZOH an be onsidered as a time delay assoiated with the lant equal to half the samling eriod, i.e., if Ls 0 Ls G() s G0() s e then GZOH() s G() s G0() s e where L L 0 4

5 /0/0 Emirial Digital PID Controller uning he angent Method of Ch5 an now be used to determine the arameters K, and L0 for a first-order lus delay model of the lant G ( s), and the digital PID ontroller is then tuned using the Ziegler-Nihols rules using the arameters K, and L An alternate form of PID ontroller often used ommerially: U ( ) ( ) K K i Kd E ( ) K K i Kd K Kd Kd 0 Remember, you imlement the ontroller in the disrete time domain, as shown below: uk ( ) ek ( ) e( k) e( k) u( k) 0 Ziegler Nihols uning of P, PI, PID Controllers Given the lant model arameters, KL,, e.g., using the angent Method, you an tune PID ontrollers using the following sheme designed to rovide disturbane rejetion: From the ste resonse of 0.s G () s e : 4 s K, L.55, 3, 0. 0 L L.6 0 K..5 KL K K i L K L K.8 d Questions? Diret Digital Design Using RL RL rules disussed in Ch5 for the s-lane hold for the -lane L ( ) Based on osed-loo ole loation, how fast is the ste resonse samled? 5

6 /0/0 L ( ) G ( 0.980)( 0.948) Based on osed-loo ole loation, how fast is the ste resonse samled omared to the rior examle? Closed Loo Polynomial, MC and AC he disrete osed-loo olynominal an be omuted as: L ( ) H, where L ( ) G( G ) and L ( ) Solving for the roots of yields the MC and AC: L ( ) and L ( ) Grahial Reresentations of MC and AC G ( ) Common Disrete Controller Forms Some ommon disrete ontroller forms are () : K, where is to right of (s) on the RL lot, () lag: K lag lag where is to left of (lags) on the RL lot, lag and (3) -lag: G lag K lag lag, Common Disrete Controller Forms A roortional ontroller is a simle gain: K K, while a roortional-derivative (PD) ontroller is a seial form of : Note: is laed at ero to ensure K Kd K, ausality a roortional-integral (PI) ontroller is a seial form of lag: K K Note: lag lag is at to i K, ensure e ss =0 and a roortional-integral-derivative (PID) ontroller is a seial form of -lag: K K i lag K Kd 6

7 /0/0 Diret Digital Controller Design Examle # Given the lant: G ( s) samled at 0.0, ss G ( 0.980)( 0.948) design a asade ontroller of the form: K that laes the desired osed-loo system oles at: r and r r (see rior design examle for related time-domain ses.) Diret Digital Controller Design Examle # It is ear from a basi RL lot of the lant that the desired osed oles annot be ahieved by gain alone and that the resulting loi must be biased to move further left within the unit ire (see RL lot of the lant G alone) Given these observations and the RL lot rules, it is reasonable to roose a omensator of fthe form: K his results in the following ye 0 loo gain: E0 K L ( ) Diret Digital Controller Design Examle # he loation of the ontroller ole an be alulated from the AC as: L ( ) tan K L ( ) Diret Digital Controller Design Examle # he ontroller gain an be alulated from the MC as: KL ( ) K 8.90 L ( ) L ( ) L ( ) H L ( ) ( ) Note, H has the desired Design Verifiation Using Coeffiient Mathing It has been shown that the desired osed-loo harateristi olynominal (CP) is given by: Based on a omensator with =0.948, K the loo gain is: L ( ) his results in a osed-loo CP of the form: K K K Comaring the two CPs and solving simultaneous eqns. yields: and K 8.90 Calulation of the Steady State Error he steady-state error to a unit ste inut is given by: ess lim e( k) ste k ste k where k is the osition error onstant given by: k lim L lim ess 0.57 ste k Unlike Examle # of Ch5 whih had a ye loo gain and thus ero steady-state error, the loo gain of this examle is ye 0, resulting in a finite (non-ero) error to a ste inut and an infinite error to a ram inut 7

8 /0/0 Comarison of Closed Loo Ste Resonses Note: hese are ye 0 systems, so you would exet a finite steady state error to a ste inut. Does the grah agree with the omuted e ss? Diret Digital Controller Design Examle #3 Given the lant: G ( s) samled at 0.0, ss3 design a -lag asade ontroller of the form: G K lag lag that t laes the desired d osed-loo l system oles at: r and r r while roduing ero steady-state error to a ste inut (see rior design examle for related time-domain ses.) Controller Design Examle #3 It is ear from a basi RL lot of the lant that the desired osed oles annot be ahieved by gain alone and that the resulting loi must be biased to move left into the unit ire (see rior examle for RL lot of the lant G ( Z)) Given these observations and the RL lot rules, it is reasonable to roose a -lag omensator of the form: K ( 0.980) ( 0.948) his results in a ye loo gain of the form: K L ( ) Alying AC and MC to L ( ): and K4.990 Questions? Note, we are skiing the setion on Frequeny Resonse Design as it is very similar to the Analog Prototye Design Method overed in Ch5 and Ch6, exet that you begin by transforming the disrete lant G () into the w lane rather then using the analog lant G (s) diretly Diret Controller Design By Synthesis It is often ossible to design the ontroller -F diretly from the given lant -F and the desired osed-loo -F as shown: G H G G H G ( ) G H his an to some unique ontroller designs, only found in the disrete domain suh as Deadbeat Controllers that deliver finite settling time; the trik is to design ontrollers that are imlementable, e.g, are ausal and stable! his requires the roer seletion of H 8

9 /0/0 Rules for Seleting H (s) Use the following rules for seleting H to ensure the resulting G is imlementable:. H must have the same ole-ero defiit as G to ensure ausality. H must ontain as eros all of the eros of G that are outside the unit ire to ensure stability 3. Zeros of H must inude all of the oles of G outside the unit ire to ensure stability 4. H () to ensure e 0 ss ste Obviously, erformane of the resulting ontroller relies on an aurate model of the lant G Rules for Seleting H (s) If all of the oles and eros of G are inside the unit ire; we an onsider a desired analog rototye H ( s) of the form: n H ( s) s s n n s whih is maed to H using e as: K 0 where n n n n e sin, e os, e d d 0 and the gain K is seleted to ensure that H () 0 K d H H Rules for Seleting H (s) K 0 0 H K ( ) H K 0 G0 0 Assuming the lant has the form G ( ) with all oles/eros inside the unit ire, by synthesis design: H K GZA S H G00 K 0 L ( ) H K, as desired! L ( ) 0 Examle Based on Ch5 Examle # Given the lant: G( s) samled at 0.0, ss G ( 0.980)( 0.948) and a desired analog rototye H ( s) of the form: 5 H () s s 7.07s5 he following ontroller results from the synthesis design tehnique outlined above (see Ch6_ Ex6.m): ( 0.980)( 0.948) ( )( )( 0.868) Finite Settling ime Design By Synthesis If all oles/eros of G lie within the unit ire, a ossible k hoie of osed-loo -F is H where k must be greater then or equal to the intrinsi delay of the lant, i.e., the differene between the order of the denominator and numerator of the lant's -F his imlies that a unit ste inut is traked kderfetly after k samles and results in what is alled a Deadbeat Controller when is seleted using the synthesis equation, as shown: k k G 9

10 /0/0 Finite Settling ime Design By Synthesis Deadbeat ontrol design is simle with k and being the only arameters; but samled data systems an exhibit intersamle osillations and DAC saturation, so the ontroller must be verified arefully before imlementation as shown (see Ch6_ Ex7.m and assoaited Ch6_ Ex7_ Model.mdl) Simulink Model of a Samle Data System (to) and Its Disrete Equivalent (bottom) Assuming the lant of the rior examle with k, 0.0 results in the following Deadbeat ontroller: ( 0.980)( 0.948) ( )( ) Finite Settling ime Design By Synthesis o avoid intersamle osillations, it is ossible to maintain a onstant ontrol signal after n samles, where n is the order of the disretied lant denominator his is done at the exense of ahieving the minimum ossible settling time, as shown in the rior examle Analysis of the standard dunity feedbak kdisrete ontrol toology shown yields: Y Y R R U H G R G G Solving the equation with the onstraint H (), yields the form of U, and thus H ; is then found using the standard synthesis formula Finite Settling ime Design By Synthesis Assuming the lant and samling eriod of the rior examle: R ( ) ( )( ) G ( )( ) R ( ) Selet H as the denominator of with extra delays, G i.e., in exess of n, removed H ( ) K ( ), where K is seleted to ensure that H K H ( ) H G G H ) ( )( ) ( )( See Ch6_ Ex8. m and Ch6_ Ex8_ Model.mdl for details 0

11 /0/0 Obviously, this design tehnique requires aurate a riori models of both the lant and the system inut (see Ch6_ Ex8.m for details) Note, this ontrol effort is large, i.e., must be generated by more than a simle DAC outut, but less than the rior examle Questions?