A Hybrid Wave-Pipelined Network Router

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1 A Hybrid Wav-Piplind Ntwork Routr José G. Dlgado-Frias Dpartmnt of Elctrical and Computr Enginring Univrsity of Virginia Charlottsvill, VA Jabulani Nyathi Dpartmnt of Elctrical Enginring Stat Univrsity of Nw York Binghamton, NY Abstract In this papr a novl hybrid wav-piplind bit-pattrn associativ routr is prsntd. A routr is an important componnt in communication ntwork systms. Th bitpattrn associativ routr (BPAR) allows for flxibility and can accommodat a larg numbr of routing algorithms. Wav-piplining is a high prformanc approach which implmnts piplining in logic without using intrmdiat rgistrs. In this study a hybrid wav-piplind approach has bn proposd and implmntd. Hybrid wav-piplining allows for th rduction of th dlay diffrnc btwn th maximum and minimum dlays by narrowing th gap btwn ach stag of th systm. This approach yilds narrow computing cons that allow fastr clocks to b run. This is th first study in wav-piplining that dals with a systm that has a substantially diffrnt st of piplin stags. Th bit-pattrn associativ routr has thr stags: condition match, slction function, and port assignmnt. Each stag s data dlay paths ar tightly controlld to optimiz th propr propagation of signals. Th simulation rsults show that using hybrid wav-piplining significantly rducs th clock priod and circuit dlays bcom th limiting factor, prvnting furthr clock cycl tim rduction. 1 Introduction Communication channls btwn any two nods rgardlss of thir physical location within a communication ntwork systm can b stablishd by using routrs at ach nod. Th purpos of th routr would b to rciv, forward, and dlivr mssags. Th routr systm transfrs mssags basd on a routing algorithm which is a crucial lmnt of any communication ntwork [1]. Givn th rconfiguring rquirmnts for many computing systms, a numbr of routing algorithms as wll as ntwork topologis must b supportd. This lads to a nd for a vry high prformanc flxibl routr to support ths rquirmnts. To maximiz a machin s ovrall prformanc and to accommodat rconfiguration in a distributd nvironmnt rquirs matching th application charactristics with a suitabl routing algorithm and topology. Having th capability of changing th routing algorithm at run tim could facilitat smart intrconncts and adaptability that allow changs on th machin s topology for diffrnt applications. A routr intndd to b usd for a numbr of routing algorithms and/or ntwork topologis has to b abl to accommodat a numbr of routing rquirmnts. It is of grat importanc that th routing algorithm xcution tim b xtrmly short. This tim dictats how fast a mssag can advanc through th ntwork, sinc a mssag cannot b transfrrd until an output port has bn slctd by th routing algorithm. Thus, th routing algorithm xcution tim must b rducd to dcras mssag dlays. Othr rquirmnts may includ: flxibility to accommodat modifications to a ntwork, algorithm and/or topology switching with minimum dlay, and programmability to support a larg numbr of routing algorithms and ntwork topologis. In this papr w prsnt a high prformanc hybrid wav-piplind VLSI routr that constituts of svral moduls and uss dynamic circuitry within ths moduls. Wav-piplining is a dsign mthod that nabls piplining in logic without th us of intrmdiat rgistrs [2]. In ordr to raliz practical systms using wav-piplining, it is a rquirmnt that accurat systm lvl and circuit lvl timing analysis b don. At systm lvl, gnralizd timing constraints for propr clocking and systm optimization nd to b considrd. At th circuit lvl, prformanc is dtrmind by th maximum circuit dlay diffrnc in propagating signals within a givn modul of th systm. Accurat analysis and strict control of ths dlays ar rquird in th study of worst cas dlay paths of circuits. Data dpndnt dlays also prsnt a problm that nds to b considrd in th us of wav-piplining. In this study, hybrid wav-piplining; a diffrnt approach to minimizing th clock priod is undrtakn. Sction 2 provids an ovrviw of th bit-pattrn asso-

2 ciativ routr, dscribing th routr opration and th circuits that form th basic blocks of ach modul. In Sction 3 w dscrib hybrid wav-piplining and dmonstrat how th dlay diffrncs ar narrowd, rsulting in clock priod rduction. Som concluding rmarks appar in Sction 4. 2 Routr Functional Organization Th bit-pattrn associativ routr (BPAR) schm supports th xcution of routing algorithms that ar usd in most communication switchs. Th associativ routr uss a contnt addrssabl mmory as its bit-pattrn associativ unit, and this nabls th dstination addrss altrnativs to b considrd in paralll. Th dstination addrss is prsntd as th input to th bit-pattrn associativ unit for comparison with th stord data. Th pattrns stord in th bit-pattrn associativ unit allow th routr to mak a dcision about th dstination port basd on th routing algorithm. Th addrss of a dstination nod D (dn;1 :::d 0 ) nds to b compard to th currnt nod s addrss C (cn;1 :::c 0 ). A routing algorithm compars th bits of th two addrsss; som bits ar ignord sinc thy do not affct th currnt routing dcision. Ths don t car bits usually occur at diffrnt positions for ach potntial path bing considrd and nd to b customizd according to th routing algorithm rquirmnts. To provid th flxibility rquird to support multipl intrconnction ntworks and routing algorithms th bit-pattrn associativ routr must b programmabl. Th rsults of th comparison ar d to th slction function, which thn s th match output with th highst priority to th port assignmnt to slct th word corrsponding to th slctd output port. Figur 1 shows th bit-pattrn associativ routr organization. Th BPAR supports thr basic opration mods: Normal or matching, programming or data loading and rfrshing [3]. In normal mod th prviously loadd data is compard to data prsntd at th sarch argumnt rgistr and th rsults d to th slction function. Th programming mod initializs th mmoris with dstination addrsss, whil rfrshing nabls rplnishing of th loadd data during th normal opration. 2.1 Dynamic CAM Cll (DCAM) Th DCAM cll is th basic building block of th bit-pattrn associativ unit array. It implmnts a comparison btwn an input and th trnary digit condition stord in th cll. A singl DCAM cll shown in Figur 2, consists of ight and a half transistors; transistor T is shard by two clls. Th rad, writ, valuation, and match lin signals ar shard by th clls in a word whil th BIT STORE, NBIT STORE, BIT COMPARE R o w S l c t Dstination Addrss ( From Input Port) Sarch Argumnt Rgistr Bit - Pattrn Associativ Unit (DCAM) Rfrsh (DCAM) match match slction function (SF) no match slctd match To Switching Ntwork (Output Port) Port Assignmnt Rgistr Port Assignmnt (DRAM) Rfrsh (DRAM) R o w S l c t Figur 1. Th bit-pattrn associativ routr organization. and NBIT COMPARE lins ar shard by th corrsponding bit in all words of th matching unit. Th dsign uss a prchargd match lin to allow fast and simpl valuation of th match condition. In Tabl 1 th possibl DCAM cll stord valus ar listd. Transistors Trf0 and Trf1 ar usd for rfrshing. Normal opration involvs comparing th input data to th pattrns stord in th DCAM and dtrmining if a match has bn found. During match opration, th input data is prsntd on th BIT COMPARE lin and its invrs valu on th NBIT COMPARE lin. Bfor th actual matching of ths two valus is prformd, th match lin is prchargd to 1 which indicats a match condition. Th matching of th input data and th stord data is prformd by mans of an xclusiv-or opration implmntd by transistors Tc1 and Tc0 whos gats hold th stord valu. Th match lin is dischargd through a sris transistor pair (Tm and T) and a logic 0 on th match lin indicats a non matching condition whil a logic 1 indicats a matching condition. Tabl 1. Rprsntation of stord data in a DCAM cll. Sb1 Sb0 stat 0 0 X(don t car 0 1 1(on) 1 0 0(zro) 1 1 not allowd 2.2 Slction Function and Port Assignmnt Th slction function should b dsignd to nsur th dtrministic xcution of th routing algorithms. For a givn input (i.. dstination addrss) and a st of pattrns

3 match lin BIT_STORE rad writ valuat BIT_COMPARE Sb1 T w1 Tc1 Tr Trf1 Tm Trf0 NBIT_COMPARE Tw0 Tc0 Sb0 NBIT_STORE Figur 2. CMOS circuit for a DCAM cll. stord in th matching unit, th port assignmnt should always b th sam. Th priority allows only th highst priority pattrn that matchs th currnt input to on to th port assignmnt mmory. Th ncodd priority (EPi) output dpnds on th match at th currnt bit-pattrn and th priority for this row. If both match and priority ar 1 ; thn th ncodd priority is tru. A priority lookahad schm has bn proposd and implmntd; it has bn rportd in [5]. Th port assignmnt mmory or RAM holds information about th output port that has to b assignd aftr a bit-pattrn that matchs th currnt input is found. This mmory is proposd to b implmntd using a dynamic approach. Th slctd row addrss is d from th priority ncodr, th clls in this row rad and thir data latchd in th port assignmnt rgistr. Th DRAM structur is abl to prform an OR function pr column whn multipl RAM rows ar slctd; this is whn multipl matchs ar d on. Th DRAM structur is xplaind in [3]. 3 Hybrid Wav-Piplining T In this sction w outlin som of th challngs of wav-piplining first and thn dscrib th timing constraints for th proposd hybrid wav-piplining approach. Convntional circuit piplining uss intrmdiat latchs in addition to th input and output rgistrs. Intrmdiat latchs (rgistrs) nsur that whn th lading dg of th systm clock coms data gts propagatd from on stag to th nxt in a synchronous mannr. In a systm stup lik this thr is only on st of data btwn rgistr stags. Wav-piplining is an approach aimd to achiv high-prformanc in piplind digital systms by rmoving intrmdiat latchs or rgistrs [4]. Idl tim of individual logic gats within combinational logic blocks can b minimizd using wav-piplining. Som of th challngs of dsigning wav-piplind systms ar: Prvnting data collision; thr must b no data ovrrun in ach circuit block, and it must b nsurd that thr is no ovr committing of th data path. Dsigning ddicatd control circuitry; control logic circuits must b dsignd to oprat synchronously with th circuitry of th piplin stags. Balancing dlay paths; dlay paths must b controlld or qualizd to rduc major discrpancis or diffrncs btwn maximum and minimum dlays [4]. Th rquirmnts statd abov ar not inclusiv but rprsnt som of th most important dsign issus in wavpiplining. Timing constraints for th proposd hybrid wav-piplining approach ar drivd in th sam fashion as in [4]. In many computr/digital systms ach stag has a significantly diffrnt function and circuitry; wid variations in dlays (Dmin and Dmax) may not b tolratd. A common nginring practic is to considr th worst cas dlay (Dmax), to nsur that th systm runs proprly. Dmax plays a vry important rol in th systm s prformanc and saf rgions of opration. Dmin (th shortst dlay path), on th othr hand, givs information about whn th rsults will bgin to mrg. Th quations drivd for th hybrid wav-piplining ar dnotd by th subscript h: To driv th quations that dscrib th timing constraints for th hybrid wav-piplin, th tmporal/spatial diagram rprsnting this schm is prsntd first. Th shadd rgions of Figur 3 indicat that data is not stabl, thrfor, rgistr outputs cannot b sampld. Th computational cons in this diagram hav bn arrangd to rprsnt ach stag within th dsign. W dfin som of th variabls apparing on th figur. Dmin and Dmax ar th minimum and maximum propagation dlays through th stags with Tclk dfining th clock priod. Ts and Th ar th rgistr stup and hold tims, rfrs to th constructiv clock skw whil clk is th rgistr s worst cas uncontrolld clock skw. DR is th rgistr s propagation dlay with dmin(n) bing th minimum dlay ncountrd in propagating data within a singl stag n and Dmin hold, th ovrall minimum dlay of all th stags. Th tim it taks for data to mrg at th output rgistr aftr N clock cycls is TL and it is givn by: T L(h) = NTclk + (1) Clocking th arlist data associatd with wavi rquirs th following condition: T L(h) <Tclk + DR + Dmin hold ; ( clk + Th) (2) whr Dmin hold = dmin(0) + dhold(0) + dmin(1) + dhold(1) + dmin(2) + dhold(2) This quation taks into considration th intrmdiat stags of th dsign. From th abov quation it can b dtrmind that Dmin hold Dmin implying that this dlay diffrnc is lss than Dmax;Dmin of th wav-piplining

4 schm. Th latst possibl tim at which data associatd with wavi can b clockd is givn by: T L(h) >DR + Dmax + Ts + clk (3) Th clock priod for th hybrid approach is dtrmind to b: T clk(h) > (Dmax ; Dmin hold) +Ts + Th +2 clk (4) Th hybrid wav-piplind approach allows for th clock signal s priod to b rducd, hnc an incras in prformanc. A complt analysis of th hybrid wav-piplining schm must includ clock cycl minimization, taking into considration th constraints of th intrnal nods of th systm and th rgistr constraints. Th minimum dlay of th hybrid approach can b writtn to includ th stag hold tims as follows: T min(h) = DR + Dmin hold ; clk ; Th ; (5) Also from Figur 3 it can b noticd that th rgion in which data is not stabl, i.. th diffrnc btwn Dmax ; Dmin hold, is short. It can thn b safly statd that Dmax Dmin hold. Th signal latching tim, xprssion bcoms: DR+Dmin hold+ts+ clk ; <NTclk < Tclk + DR + Dmin hold ; ( clk + Th) ;. systm clock is achivd by using th dlays in th dsign. Ths dlays ar manipulatd to allow data to rippl from on stag to th nxt without any collision. Th diffrnc btwn th maximum (worst cas) dlay and th minimum dlay is of particular intrst in dsigning th timing schm of a wav-piplind bit-pattrn associativ routr [2]. Th buffr insrtion mthod to balanc th dlays dscribd in [4] is not usd, instad spcializd circuitry is dsignd to provid vry prcis timing squncs. Th valuat signal must go to 1 aftr th data d to th DCAM for comparison has stabilizd on th lins BIT COMPARE and NBIT COMPARE. Th circuit that gnrats this signal onc all th lins hav bn st to thir appropriat input valus is shown in Figur 4(a). It is an AND gat whos inputs ar th match lin and th clock signals. Th dlays ncountrd in charging and discharging th match lin ar indicativ of stabl data on th bit lins, hnc th us of th match lin signal to gnrat an valuat signal. Onc valuation has bn compltd th match clock match lin valuat Dmax Dmin_hold windowh Dmin (a) Gnrating th valuat signal. logic dpth stag 0 stag 1 stag 2 dmin(0) d hold(0) dmin(1) i dhold(1) Tsx i + 1 Tpz T prch z valuat p Tpu Tp Tpd D R tim T clk (b) Gnrating th signal. Figur 3. Tmporal/spatial diagram aftr clock priod rduction. Hybrid wav-piplining allows for th rduction of clock cycl tim using th dlays to propagat data from stag to stag without th us of ithr intrmdiat latchs or distributd clocks. 3.1 Control Signals for Th Bit-Pattrn Associativ Unit In this study propagating cohrnt data wavs from on piplin stag to th nxt without th us of a distributd Figur 4. Circuits to gnrat BPAR control signals. lin outputs ar d to th slction function. Thus, th signal must immdiatly b activ following compltion of th valuation procss. Th circuit usd to gnrat th signal is shown in Figur 4(b). Th signal is dsignd to mimic th path a zro on th match lin (nonmatching condition) taks onc valuation complts. Passing a 0 to th slction function provids th maximum dlay that can b xprincd in ing th matching unit s outputs to th slction function and, thrfor, constituts

5 th worst cas propagation dlay for this opration. Th circuits in Figurs 4(a) and 4(b) hav bn dsignd to sns th duration and voltag lvls of ths signals. All th signals prsntd to this point dpnd on th systm clock. 5 4 valuat clock 3.2 Hybrid Wav-Piplining Signals Th signals gnratd by th abov circuits appar in Figur 5(a) along with th clock. Th dlays of th first two stags ar clarly markd in th figur to show a corrlation with th hybrid wav-piplind approach. On Figur 5(a) th minimum dlays, (dmin) and hold tims (dhold) of ach stag ar shown. W hav also includd som rsults from th BPAR chip tst, fabricatd in a 0.5m tchnology. Ths rsults appar in Figurs 5(b) and 7(b). Onc th output of th match lins hav bn rcivd by th slction function a dcision nd to b mad whn mor than on matching condition has bn rcivd. Th slction function is dsignd to propagat a priority status Pi to th ntry blow it indicating whthr it has rgistrd a match. This priority must b propagatd vry fast to prvnt fals starts. Som of th signals of importanc in this schm ar shown in Figur 6. Th slction function s critical opration occurs whn its first and last ntris simultanously rciv inputs indicating that matching conditions hav bn found in th corrsponding bit-pattrn associativ unit ntris. Th first ntry has to propagat a 0 to th last ntry in ordr to prvnt gnration of a pointr to th DRAM by th last ntry. Signals to lssn th possibility of fals starts ar gnratd and ths ar labld nabl. Thy ar dsignd to nsur that vn if a fals start occurs th pointr to th DRAM array is not stablishd. In Figur 6 signals usd to nabl th DRAM pointrs for th first and last ntris from a stup in which th last ntry always finds a match and th first ntry finds a match vry othr clock cycl ar shown. Th plots in Figur 7(a) ar thos of th DRAM pointrs to its first and last ntris. Thy srv to show that an output port assignmnt can b rad from th DRAM array vry on and a half clock cycls. Th computational cons of Figur 8 show th thr stags of th bit-pattrn associativ routr and thir associatd dlays. Each stag accommodats th latst data associatd with th currnt wav by allocating additional tim to procss this data. Th bit-pattrn associativ unit complts worst cas opration in 5.1 ns. This tim includs th input latch dlays, clock skw and hold and stup tims for this stag. Th hold tim for th slction function is vry short, almost qual to th minimum dlay of this stag. This short hold tim is a dirct rsult of th slction function dsign, which nsurs propagation of th priority status to ntris blow th currnt on vry fast by mans of th priority lookahad. Th port assignmnt has a minimum dlay of 0.4 ns and rquirs 3 ns of hold tim. Rduction of Voltag (V) Voltag (V) d min(cam) d hold(cam) d valuat(cam) d (SF) SF = slction function tim (µs) (a) Plot of th bit-pattrn associativ unit control signals. matchlin (b) Evaluat and match lin signals. Figur 5. SPICE simulations and chip tst rsults for valuat and circuitry. d (SF) d hold(sf) DRAMslct 0 d min(ram) output 0 SF=slction Function nabl 0 output 15 nabl 3 d hold(ram) DRAMslct tim (µs) Figur 6. Plots of th nabl signals. th gap btwn Dmax and Dmin at ach stag is prsntd hr graphically with th dlays displayd to show how th clock priod is mad shortr in this dsign.

5 dminram dholdram 0.4 ns 3 ns 4 Voltag (V) 3 2 1 DRAM slct 0 clock DRAM slct 15 0 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 tim (µs) (a) Plot of th DRAM pointrs.

6 5 dminram dholdram 0.4 ns 3 ns 4 Voltag (V) DRAM slct 0 clock DRAM slct tim (µs) (a) Plot of th DRAM pointrs. DRAM output bit 0 logic dpth input latch and CAM slction function (SF) RAM and output latch dminsf dholdsf 0.7 ns 0.8 ns dmincam dholdcam 1.6 ns 3.5ns d 0.9 ns dvaluat 2 ns RAM_output (first ntry) RAM-output (last ntry) tim Figur 8. Dlays of th BPAR translatd to a computational con diagram. Issus such as signal gnration, unvn dlays, and timing hav bn addrssd to synchroniz th piplin. ACKNOWLEDGMENT This work was supportd in part by th National Scinc Foundation undr contract CCR (b) Port Assignmnt output. Figur 7. SPICE simulations and chip tst rsults for output port assignmnt. 4 Concluding Rmarks An xtrmly fast flxibl routr capabl of accommodating a numbr of routing algorithms and ntworks has bn prsntd in this papr. Th bit-pattrn associativ routr is dsignd using a novl schm that combins wav-piplining and convntional piplining producing hybrid wav-piplining. Th hybrid wav-piplining approach narrows th gap btwn Dmin and Dmax rsulting in a rduction of th clock cycl tim. To furthr improv th prformanc of th bit-pattrn associativ routr dynamic circuits along with a high prformanc slction function to rduc priority status propagation dlays ar usd. This study is th first of it s kind; it xamins th dlays within ach modul of th dsign and minimizs thm individually. Rfrncs [1] D. Clark and J. Pasqual, Stratgic Dirctions in Ntworks and Tlcommunications, ACM Computing Survys, vol. 28, no. 4, pp , Dc [2] C. Thomas Gray, Wntai Liu, Ralph K. Cavin, III, Wav Piplining: Thory and CMOS Implmntation, Kluwr Acadmic Publishr [3] J. G. Dlgado-Frias, J. Nyathi and D. H. Summrvill, A Programmabl Dynamic Intrconnction Ntwork Routr with Hiddn Rfrsh IEEE Trans. on Circuits and Systms, I vol. 45, no.11, pp , Nov [4] W. P. Burlson, M. Cisilski, F. Klass and W. Liu, Wav-Piplining: A Tutorial and Rsarch Survy, IEEE Trans. on Vry Larg Scal Intgration (VLSI) Systms, Vol. 6, No. 3, pp , Sptmbr [5] J. G. Dlgado-Frias and J. Nyathi, A High- Prformanc Encodr with Priority Lookahad, IEEE Trans. on Circuits and Systms, I: Fundamntal Thory and Applications, Vol. 47, NO. 9, Sptmbr 2000.

Chapter 6 Folding. Folding

Chapter 6 Folding. Folding Chaptr 6 Folding Wintr 1 Mokhtar Abolaz Folding Th folding transformation is usd to systmatically dtrmin th control circuits in DSP architctur whr multipl algorithm oprations ar tim-multiplxd to a singl