Transmission Level HTS Fault Current Limiter

Transcription

1 Superconductivity for Electric Systems Peer Review U. S. Department of Energy August 7 9, 2007 Transmission Level HTS Fault Current Limiter Chuck Weber & Drew Hazelton SuperPower Shigeki Isojima SEI Isidor Sauers Oak Ridge National Lab Providing HTS Solutions for a New Dimension in Power TODAY!

2 Presentation Outline Program Outline & Objectives Background information on the SFCL Project FY2007 Milestones FY2007 Accomplishments & Results FY08 Planned Performance & Milestones Technology Transfer, Collaborations & Partnerships Summary DOE Peer Review, August 7-9,

3 HTS Fault Current Limiters: New Technology for a Growing Problem As new sources of generation are added, utilities are faced with the threat of higher levels of fault current HTS Fault Current Limiters (FCLs) address the market pull to cost-effectively correct fault current over-duty problems at the transmission voltage level of 138kV and higher The HTS FCLs will reduce the available fault current to a lower, safer level (20%- 50% reduction), so that existing switchgear can still protect the grid Utility market needs at the transmission level: Accommodate increasing fault currents due to added generation Prevent breaker failures & associated problems (e.g., welded contacts, bus bracing, etc.) Maintain flexibility to accommodate load growth and open access Avoid adverse side effects imposed by existing solutions Reduce through fault stresses on aging infrastructure Avoid need for expensive 80kA breaker upgrades HTS FCLs are a natural complement to AC HTS cable systems Discussions with 20+ utilities have consistently validated the need New Generator MFCL Substation C Substation A Substation B DOE Peer Review, August 7-9,

4 SFCL: Project Description & Research Integration Program Goal: Demonstrate SFCL feasibility at transmission level voltage 138kV Cost: Estimated total project cost is $26.1M DoE Funding (thru SPI, SPE* & GridWorks programs) - $13.5M EPRI Funding - $600k Industrial Partners (SP, SEI, BOC, AEP) - $12M Schedule: Project started 6/02, Proof of Concept device demonstrated in 2004, 1-Φ Alpha device in 2008, 3-Φ Beta device in 2010 Project Team: SuperPower; SEI; BOC; AEP DoE National Labs: ORNL (HV, cryogenics), LANL (HTS element evaluation) Technical Advisory Board, NEETRAC * New award for SPE received ~ July 2007 DOE Peer Review, August 7-9,

5 SFCL Program Overview (cont d.) Technical Research Advisory Integration Board (TAB): (cont d.) Evaluate and guide project in conjunction with DOE Readiness Review program Utility members: AEP, New York Power Authority, Southern California Edison, Con Edison, Entergy Academia: Rensselaer Polytechnic Institute (RPI) Funding sponsors: DOE and EPRI National Electrical Energy Testing, Research And Applications Center (NEETRAC) Periodic reviews with utilities with an interest in the project: Florida Power and Light, Exelon, Southern Company, Baltimore Gas and Electric, Entergy, Con Edison NEETRAC project manager sits on TAB Use existing specialized facilities: KEMA Power Test, Chalfont, PA, for short circuit testing 2G module successfully tested in June 2006 Waukesha Electric for Impulse testing up to 900kV High Voltage Working Group SEI, RPI, AEP and ORNL DOE Peer Review, August 7-9,

6 Alpha 138 kv SFCL Design - Main Components Bushings Cryostat Matrix Assembly HTS Elements Single Phase SFCL High Voltage Insulation System Bushings Cryostat insulation system Matrix internal insulation HTS material - 2G for FCL applications Material characterization, current limiting and recovery Energy management, thermal and mechanical strength Material selection and customized manufacturing process for optimum SFCL applications Failure statistics and life expectancy Effects of HTS failure on systems and SFCL device HTS device assembly Overall layout and assembly of HTS Elements and shunt coils Mechanical integrity of assembly and connections Steady state loss reduction Cryogenic system Vessels to provide stable pressurized sub-cooled environment Cryogens and cryo-coolers Systems aspects of SFCL program System studies and utility requirements Instrumentation, system control, protection and condition monitoring procedures DOE Peer Review, August 7-9,

7 Generalized SFCL Specification Development Status: Baseline Design for Program was the AEP SPORN substation site This is a niche application site, operating at 400Arms, 138 kv Prospective fault current 26 ka rms (~90 ka peak) and 13.8 ka rms (~ 37 ka peak) Working with AEP, we have identified a site with broader general application TIDD substation 1,200 A rms, 138 kv Prospective fault current is 13.8 ka rms (~37 ka peak ) Much of our work includes these specifications in our design envelope as they impact such functions as recovery under load, # of parallel tapes, complexity of design, etc. DOE Peer Review, August 7-9,

8 TIDD Substation One-Line Diagram (Partial) Proposed SFCL Installation Location DOE Peer Review, August 7-9,

9 SFCL Testing Specification Development Working with AEP and NEETRAC, developed acceptance testing specification for SFCL device which draws upon the following acceptance standards. 1. Circuit Breakers ANSI C37.06 and C Transformers IEEE C and C Series Reactors IEEE C57.16 Future Plans: Continue to work with AEP to review 5 other utilities to examine target operating conditions for SFCL Verify that acceptance testing plans are sufficient and satisfactory with other utilities. DOE Peer Review, August 7-9,

10 SFCL Design Envelope Established SFCL Alpha Design Parameters System Parameters Voltage [kv rms] 80.0 Load Current [ka rms] Short Circuit Fault Current [ka rms] 14.0 Short Circuit Fault Current [ka peak] 37.0 X/R ratio 30.0 Fault Duration [cycles] 5.0 Overall Dimensions - inside cryostat First peak Limited/Prospective Current ratio [%} Steady state Limited/Prospective Current ratio [%] Over all diameter [mm] Overall Height [mm] Overall dimensions depend on high voltage clearance requirements both in radial and axial spacing directions DOE Peer Review, August 7-9,

11 Presentation Outline Program Outline & Objectives Background information on the SFCL Project FY2007 Milestones FY2007 Accomplishments & Results FY08 Planned Performance & Milestones Technology Transfer, Collaborations & Partnerships Summary DOE Peer Review, August 7-9,

12 FY07 Milestones Develop conceptual design for the Cryogenic Refrigeration System (CRS) Improve shunt coil and connector design Study and understand Recover Under Load (RUL) requirements Modify 2G conductor to improve performance for the FCL application Complete High Voltage design for Alpha device DOE Peer Review, August 7-9,

13 Presentation Outline Program Outline & Objectives Background information on the SFCL Project FY2007 Milestones FY2007 Accomplishments & Results FY08 Planned Performance & Milestones Technology Transfer, Collaborations & Partnerships Summary DOE Peer Review, August 7-9,

14 CRS Conceptual Design DOE Peer Review, August 7-9,

15 Cryogenic System Transient Heat Loads - Fault Transient heat load impacts short term RUL of HTS & long term system recovery - Fault current energy (fault current & number of cycles) drives transient heat load Short Term Recovery Under Load (RUL) HTS elements re-cool to superconducting state Value of shunt impedance impacts RUL HTS element temperature based on total energy deposition HTS elements directly cooled by LN2 bath Impact of external cooling is minimal Recovery time driven by heat transfer from elements to LN2 bath Heat transfer aided by higher operating pressure Higher pressure suppresses visible bubble formation with improved dielectric performance Unit is functional as HTS elements recover Longer Term System Recovery System recovers to baseline operating level Cooling by external cooling system Driven by total energy deposited in the LN2 bath Unit is operational as system recovers, up to a finite energy deposition level DOE Peer Review, August 7-9,

16 Estimated Cryogenic Heat Loads in the SFCL System Steady State Operation Operating current 1,200 A rms Pressure vessel size ~ 2.5 m diameter Total Heat Load W Internal Heat Loads 56-60% I 2 R terminal/connector loss 48-51% ac loss 7-8% dielectric loss 1 % External Heat Loads 40 44% lead loss (incl. conduction) 6 9 % conduction loss % radiation loss % Based on Conceptual Cryostat Designs with stainless steel structures DOE Peer Review, August 7-9,

17 Shunt Coil & Connector Design DOE Peer Review, August 7-9,

18 Test and FEA Modeling of the Multilayer Shunt Coil Shunt Coil 06 KEMA Test: Design shunt coil to withstand both thermal and E-M forces and optimize design for minimal normal losses Design robust connection to 2G elements Preliminary FEA Modeling Results Magnetic Field Distribution Simulation Results: equivalent stress (von Mises) exceeds plastic deformation limit for the given current load at the point of failure. Magnetic Force Distribution DOE Peer Review, August 7-9,

19 Shunt Coil Design Equivalent Stress Map of Circular vs. Race Track Shunt Coil: A) Circular Shunt Coil: ( Reduced to 2D axial symmetry analysis) B) Race Track Shunt Coil: (Requires 3D plane symmetry analysis) Copper 90 MPa; Stainless steel overbanding 156 MPa. Copper 100 MPa; Stainless steel overbanding 175 MPa. Conclusion: no benefit in utilizing more complicated Race Track. Final design was based on the circular cross-section Shunt Coil with Stainless Steel overbanding. DOE Peer Review, August 7-9,

20 Results from KEMA Shunt Coil Testing (6) coils fabricated & tested at KEMA Varying degrees of over-banding and coil length S5 L2 Target operating condition, 27 ka. Coils without over-banding showed signs of insulation breakdown due to hoop 30-35kA (slightly higher than anticipated due to unknown mechanical properties of Formvar isolation in the cryogenic environment) S0 S1 L1 L0 Coils L1 & L2 tested up to 40kA without any signs of damage 4 40kA and 3 40kA series (5 cycle fault, 18 cycle off, 5 cycle fault) Coil S1 tested to destruction Tested to 55kA w/o damage At 60 ka, distortion of buswork indicated At 64 ka, coil failed catastrophically DOE Peer Review, August 7-9,

21 Contact Design Aim: To design a connector with equalized surface current density distribution to avoid tape s thermal failure near the connector. Issue: Hot spots of increased current density near the connector s edges. Solution: Copper Connector Normal state hot spot (vanishes as L increases at superconducting state) The optimized contact design is being developed; taking into account the following: a) Optimized geometry of the contact; Superconducting state hot spot HTS Tape (vanishes as L increases at normal b) Minimizing state) the interface L resistivity according to [1] and [2]. Preliminary FEA simulation results show significant decrease in current density in modified contacts. [1] Preisler E., et al, Supercond. Sci. Highest Technol. current 7 (1994) density in the silver layer 1.3*10 11 A/m 2 [2] Zeimetz B., et al, Journal of Applied Physics, V88(9), 2000, DOE Peer Review, August 7-9,

22 Recovery Under Load DOE Peer Review, August 7-9,

23 RUL Description 2G Elements Recovery Under Load (RUL) Shunt Load current flows through HTS / Shunt circuitry while cooling down from heating during fault transient(s). 5 Cycles Fault 13kA/7kA 5 Cycles Fault 13kA/7kA 5 Cycles Fault 13kA/7kA 5 Cycles Fault 13kA/7kA 5 Cycles Fault 13kA/7kA Breaker opens and locks-out 18 Cycles Load Current 15 sec Load Current 135 sec Load Current 160 sec Load Current Recovery under NO Load Current Typical AEP reclosure sequence DOE Peer Review, August 7-9,

24 SFCL RUL Test Results 40 2G tape - Recovery Under Load (RUL) test, Single tape with Ic = 120 A, 20 cm long, tested with 40 V rms supply, Shunt impedance varies from 2.5 to 10 mohm 40 2G tape - Recovery Under Load (RUL) test, Single tape with Ic = 120 A, 20 cm long, tested with 40 V rms supply, Shunt impedance varies from 2.5 to 10 mohm Recovery time [sec] Recovery time [sec] Energy [J/cm/tape] 0 RUL at I_L=50 Arms, Zsh = 2.5mO RUL at I_L=50 Arms, Zsh = 3.3mO RUL at I_L=50 Arms, Zsh = 5mO RUL at I_L=50 Arms, Zsh = 10mO Energy [J/cm/tape] RUL at I_L=25 Arms RUL at I_L=50 Arms RUL at I_L=60 Arms RUL at I_L=67 Arms Fault energy determines the maximum temperature higher energy per tape takes longer to recover Requires additional test to get a transfer function, Recovery time = f (Energy) DOE Peer Review, August 7-9,

25 SFCL SFCL RUL Test Results 40 2G tape - Recovery Under Load (RUL) test, Single tape with Ic = 120 A, 20 cm long, tested with 40 V rms supply 40 2G tape - Recovery Under Load (RUL) test, Single tape with Ic = 120 A, 20 cm long, tested with 40 V rms supply Recovery time [sec] Recovery time [sec] Shunt Impedance [mohm] Load Current [A rms/tape] RUL at I_L=25 Arms RUL at I_L=50 Arms RUL at I_L=25 Arms RUL at I_L=50 Arms RUL at I_L=60 Arms RUL at I_L=67 Arms RUL at I_L=60 Arms RUL at I_L=67 Arms Low shunt impedance diverts more fault and load current away from tapes and helps to speed up RUL The most critical parameter for RUL is the load current and is provided by systems requirement design to recover under required load DOE Peer Review, August 7-9,

26 Cool-Down and Recovery Voltage Voltage (V) Voltage C-119 Voltage C-115 Voltage C-114 Voltage C-113 Voltage C-110 Voltage C Simulation Time (s) DOE Peer Review, August 7-9,

27 SFCL Sample RUL Test Results V, mv V, mv V, mv Recovery Plot - Voltage across 2G HTS M3-401 Load Current 65 Amps RMS fault t, s Recovery Plot - Voltage across 2G HTS M3-401 Load Current 76 Amps RMS t, s Recovery Plot - Voltage across 2G HTS M3-401 Load Current 91 Amps RMS t, s Voltage across 2G HTS Tape recovery (V=0) Voltage across the 2G HTS Tape No recovery Voltage across 2G HTS Tape Current [ka] Recovery Under Load (RUL) Test Results Recovery Time as a function of a load current Load Current strongly affects recovery time (defined as time when voltage returns to zero) Reaching some critical level of the load current 2G HTS Tape doesn t recover in a reasonable timeframe. 2G tape - Recovery Under Load (RUL) test, Single tape with Ic = 120 A, 20 cm long, tested with 40 V rms supply and with 10 mo 0.10 shunt coil, Load current = 52 A rms Recovery time = Sec Time [ms] Isc [ka] Ish [ka] Voltage [V] Recovery time for 5 mohm shunt = 7 sec. Voltage [V] DOE Peer Review, August 7-9,

28 2G Wire Development for SFCL DOE Peer Review, August 7-9,

29 2G Development for SFCL What drives the 2G conductor design operating in an SFCL environment? System Considerations Operating current - # of tapes Operating voltage length of tape Fault levels energy deposition Parallel shunt current sharing and energy deposition 2G Wire Performance Energy to failure (statistics) Temperature rise and tolerance during fault transient Recovery Under Load (RUL) Heat Transfer Cryogenics (pressure, subcooling) DOE Peer Review, August 7-9,

30 2G Optimization Main Areas for Optimization Substrate & Stabilizer thickness and composition Critical current Enhanced heat transfer to cryogen bath Tape layout, side stabilizer coverage and end termination Each of these areas has tradeoffs More mass (constant current) is better for minimizing temperature rise Lower resistance leads to higher current sharing with fixed shunt impedance Shunt impedance variation limited by system requirements Recovery under load (RUL) performance optimization is key Total Buffer stack 157 nm ~ 80nm alumina Superconductor ~ 30nm STO ~ 30 nm Homo-epi MgO ~ 10nm IBAD MgO ~ 7nm yttria Stabilizer a,b axis Substrate DOE Peer Review, August 7-9,

31 2G Conductor for SFCL Shows Consistent, Excellent Performance High-power SFCL test Prospective current Limited current Peak current through element Response time Element quality range Fast response time 2G 90 ka* 32 ka 3 ka < 1 ms Narrow Current [ka] Current [ka] Time [ms] Voltage across HTS elements [kv] Iprospective I_total_KEMA I_HTS Ish V_total_KEMA Quench speed around 0.5 ms 3.5 Time [ms] I_total_KEMA I_HTS Ish V_total_KEMA Voltage across HTS elements [kv] DOE Peer Review, August 7-9,

32 Weibull Plot of 2G Failures (100 micron Hastelloy, Standard SFCL Tape) Probability of failure [%] G FCL - Probability of failure for 2G tapes as function of energy input Target design point Energy [J/cm/tape] Probability of Failure - Test data Probability of Failure Calculated using Weibull Distributuon DOE Peer Review, August 7-9,

33 A standard 2G wire does not recover under load beyond a certain fraction of Ic RUL after 10 seconds RUL after 80 seconds Itape (A) 400 I (A) Fault Vtape (mv) U (mv) time (s) Fault time (s) = 252 Adc Ic Ic = 252 Adc Iload = 172 Apeak Iload = 179 Apeak Load current at fault ~ 1,600 A Load current at fault ~ 2,600 A The wire did not recover under load, at a load current of 194 A. The absence of recovery under load happens in a narrow transition regime of load current DOE Peer Review, August 7-9,

34 Engineered 2G wire improves recovery time & RUL levels RUL within 12 seconds RUL within 6 seconds I tape (A) U tape (V) I c I load Fault time (s) = 153 Adc = 179 Apeak Load current at fault ~ 3,540 A I tape (A) V tape (mv) time (s) Fault I c = 121 Adc I load = 241 A peak Load current at fault ~ 4,600 A Recovery Under Load at high currents in engineered 2G wires opens path of adoption of 2G FCL in real-grid use. DOE Peer Review, August 7-9,

35 Baseline Element Design 0.4 m Prototype Structure Tested at KEMA in 2006 Open Structure of Parallel 2G tapes to 1 meter long DOE Peer Review, August 7-9,

36 Alternate Element Designs Baseline design has high number of components and large # of connections Reliability issue High heat load (I 2 R at contacts) Alternate Element Designs Designs continue to be non-inductive >> minimal impedance during superconducting operation Significant reduction in contact count (100 s to 10 s) Improved reliability Significant reduction in contact heat load 100 s of W to 10 s of W Recent high power tests indicate comparable 2G performance (failure level) in alternate design configurations as compared to baseline design. Recovery under load demonstrated in alternative designs. DOE Peer Review, August 7-9,

37 High Voltage Design DOE Peer Review, August 7-9,

38 High Voltage Design Development Objectives Main objectives Build confidence to design a 138 kv, 650 kv BIL Fault Current Limiter Improve understanding of the dielectric performance of insulation materials in a cryogenics environment Develop experimental test setups & test SFCL mockups to voltages higher than device ratings, up to 200 kv AC and 900 kv Impulse Develop Finite Element Analysis Simulation tools to compute Electric Field Distribution Develop Transfer Function between FEA and test results Develop design tools based on the experimentally verified transfer functions To demonstrate, with practical test setup, that a HV design for 138 kv application in a cryogenics environment is feasible To accomplish a reliable HV design for HTS devices Identify and Study the Main Insulation Areas Bushings/Leads and Matrix Assembly to Cryostat External Insulation (SEI s responsibility) Matrix Assembly Internal Insulation (SP s responsibility) Bushings/Leads (SEI s responsibility) DOE Peer Review, August 7-9,

39 High Voltage Test Requirements for Alpha It is not possible to achieve standard BIL test waveforms across the terminals - See figure below Tests based on typical 138kV requirements for Breakers, Transformers & Current Limiting Reactors Based on input from AEP and NEETRAC Members Test sequence will follow transformer standard Normal Impulse Wave Shape Tests to be Conducted Proposed SFCL Requirement 60Hz Withstand Based on ANSI Breaker C37.06 Table 4 Partial Discharge Based on ANSI Transformer C Table 6 BIL Lightning Based on ANSI Reactor C57.16 Table 5 Impulse Chopped Wave Based on ANSI Transformer C Table 6 Switching Impulse Partial Discharge Based on ANSI Transformer C Table 6 Acceptance criteria established Expected MFCL Wave Shape Due to Very Low Impedance Configurations for impulse testing: Impulse terminal A wrt to ground, with B open Impulse terminal B wrt to ground with A open A B Tie A & B together and impulse wrt to ground High voltage tests should be conducted with device in both normal and current limiting state DOE Peer Review, August 7-9,

40 High Voltage Characterization SP High Voltage Testing Purpose: To get basic LN2 breakdown data Repeat tests carried ORNL to verify consistency Take at least 20 breakdown data points per setup Vary gaps until breakdown voltage reaches ~200 kv * Items in red have been completed Test Setup HV Electrode LN2 Gap (in.) Sphere Plane ½ Sphere 1/8, ¼, ½,1, 1.5, 2, 3, 4 Sphere Plane 1 Sphere 1/8, ¼, ½,1, 1.5, 2, 3, 4 Sphere Plane 2 Sphere 1/8, ¼, ½,1, 1.5, 2, 3, 4 Rod Plane Rod w/ Sharp Edge 1/8, ¼, ½,1, 1.5, 2, 3, 4 Rod Plane Rod w/ 1/8 Radius 1/8, ¼, ½,1, 1.5, 2, 3, 4 Rod Plane Rod w/ 1/4 Radius 1/8, ¼, ½,1, 1.5, 2, 3, 4 Rod Plane Rod w/ 1/2 Radius 1/8, ¼, ½,1, 1.5, 2, 3, 4 Data Analysis Statistical data analysis mean, standard deviation, Weibull probability of failure analysis Compare test results with FEA analysis results DOE Peer Review, August 7-9,

41 HV Testing of 145 kv Bushing at ORNL Completed Within the capabilities of ORNL s equipment, we were able to test the Trench 145 kv bushing in both air (control) and LN2 with no indications of degradation. The Trench acceptance test based on IEC60137:2003 was used as guidance for the ORNL tests. Thermal cycling of bushing was completed no change in performance Test Condition Trench Acceptance Test ORNL Test - Air ORNL Test LN2 Capacitance and Tan δ pf 0.45% 522 pf 0.7% 533 pf 0.9% 521 pf 0.9% 517 pf 1.0% Lightning Impulse 650 kv for 5 neg pulses 650 kv for 5 neg pulses 650 kv for 5 neg and 5 pos pulses Partial Discharge (1) < 3 pc up to 168 kv < 3 pc up to 100 kv < 3 pc up to 100 kv Test Order 1, 6 2 3, 5 4 Voltage Withstand (2) 275 kv for 60 sec 200 kv for 60 sec 200 kv for 60 sec (1) ORNL limited to 100 kv PD for clean measurement, 150 kv PD measurement had excessive noise. (2) ORNL limited to 200 kv voltage withstand Qualification testing of Trench ORNL DOE Peer Review, August 7-9,

42 138kV Bushing Development - Withstand Voltage Testing First set of tests were conducted in January, 2007 Bushing was thermally cycled 3 times, the a 2 nd set of 60Hz withstand tests with partial discharge measurements were conducted in June, Test 60Hz withstand(dry) With partial discharge measurements Full-wave lightning impulse (dry) Chopped-wave lightning impulse (dry) Conditions and Values (according to proposed SFCL requirements) Partial discharge measurements (125kV for 5 min. 145kV for 120 sec 125kV for 1 hour) 310kV for 1 minute μs,650kV, (-)polarity 3μs chop,715kv, (-)polarity Good Results Partial discharge B.N B.N:1st test Good Good 2nd test 3.2pc 5.6pc Switching-impulse (dry) μs,540kV, (+) and (-)polarity Good Conditions of liquid nitrogen in cryostat: boiling (at 77K and 0 barg) DOE Peer Review, August 7-9,

43 Dielectric Tests of Bushing bushing bushing 60Hz withstand voltage test with PD measurements cryostat for tests Full-wave lightning impulse test DOE Peer Review, August 7-9,

44 2G FCL High Voltage Test Rig FEA results shows how the stress shield ring can be used to reduce stresses in sharp edge geometries Sharp 2G element and connector edges Radial gap [in] Axial gap [in] Shield [Yes/No ] Yes Yes Yes Yes Yes Yes Yes kv [kv/mm] kv [kv/mm kv [kv/mm Using stress Shield rings 6 6 No > 6.5 > 4.6 > 4.5 DOE Peer Review, August 7-9,

45 HV Test Module Assembly 12 Element Mockup 42 Bushing (PTFE or G10 insulated conductor) 600 mm (24 ) Maximum 360 mm (14.2 ) 42 Corona rings Min Maximum 360 mm (14.2 ) (24 ) 0-12 Ground electrode - 12 element mockup assembly to fit into an open bath fiberglass test cryostat - Assembly at SP completed - Sent to ORNL for testing DOE Peer Review, August 7-9,

46 Presentation Outline Program Outline & Objectives Background information on the SFCL Project FY2007 Milestones FY2007 Accomplishments & Results FY08 Planned Performance & Milestones Technology Transfer, Collaborations & Partnerships Summary DOE Peer Review, August 7-9,

47 FY08 Plans Complete detailed design of Alpha device Finalize configuration of Engineered 2G conductor Matrix Assembly Cryogenic Refrigeration System High Voltage insulation system design Bushing design Vessel design Complete component prototyping and evaluation Complete specification outreach to other US utilities Commence fabrication of Alpha device (SPE program) DOE Peer Review, August 7-9,

48 Presentation Outline Program Outline & Objectives Background information on the SFCL Project FY2007 Milestones FY2007 Accomplishments & Results FY08 Planned Performance & Milestones Technology Transfer, Collaborations & Partnerships Summary DOE Peer Review, August 7-9,

49 Technology Transfer, Collaborations & Partnerships Presentations ASC 06 Seattle, WA 8/28-9/1/06 EPRI S/C Workshop Columbus, OH 9/13-14/06 Tech Valley Chamber Executive Institute 10/22/06 Leadership Tech Valley Group 10/23/06 Re-Engagement Readiness Review Mtg 12/ DOE Wire Development Workshop Panama City, FL 1/16-17/2007 DOE Gridworks Program Review Mtg 5/30/07 IEEE PES General Meeting Tampa, FL 6/25-28/07 NEETRAC Advisory Board Updates (4) times ISIS-15 (Erlangen, Germany) 9/27-29/06 No. Colonie HS Technology Night 10/16/06 Knolls Atomic Power Lab (Schenectady, NY) 10/31/06 Defense Manufacturers Conference (Nashville, TN) 11/27-29/06 SCCC Technology Club 1/26/07 Questar III METS Program 1/31/07 National Electricity Devliery Forum (Washington, DC) 2/22/07 Hannover Fair (Hannover, Germany) April 2007 RPI Alumni Group 6/19/07 CEC/ICMC (Chattanooga, TN) July 2007 News Articles Electric Transmission Week 2/19/07 Three companies developing HTS fault current limiters 2/5/07 Growth in power demand creates market potential for new fault current limiters 7/31/06 SuperPower takes new approach to developing HTS fault current limiter DOE Peer Review, August 7-9,

50 Presentation Outline Program Outline & Objectives Background information on the SFCL Project FY2007 Milestones FY2007 Accomplishments & Results FY08 Planned Performance & Milestones Technology Transfer, Collaborations & Partnerships Summary DOE Peer Review, August 7-9,

51 Summary Installation site changed from Sporn to Tidd More representative of a typical 138-kV installation Recovery Under Load (RUL) has gone from 400 A rms to 1,200 A rms 2G Wire Capabilities Reliability of standard 2G wire demonstrated Benefits of engineered 2G wire demonstrated with improved RUL Alternate element design are under evaluation Shunt Coils re-designed and qualified for Tidd application CRS Conceptual Design completed RUL Studies Initiated, significant challenges remain High Voltage Design Bushing qualification well under way HV characterization will be the building blocks that enable a robust matrix assembly design DOE Peer Review, August 7-9,