SIMPLIFIED sra11c AND DYNAMIC MODELS OF THE 3-LOOP ACI1VE POWER FACTOR CORREC11ON SYSTEMS

Transcription

1 J q7j ft SIMPLIFIED srac AND DYNAMIC MODELS OF THE 3-LOOP ACIVE POWER FACTOR CORRECON SYSTEMS A. Abramvitz and S. Ben- Yaav Department f Electrical and Cmputer Engineering Ben-Gurin University f the Negev P. 0. Bx 653, Beer-Sheva 8405, ISRAEL Tel: ; Fax: ; Emai: sby@bguee.bgu.ac.il Abstract. Simple static and dynamic mdels f the 3-lp Active Pwer Factr Crrectin (APFC) system are suggested and analyzed. Analytical expressins fr the gain cnstants and the transfer functins f the feedbac and feedfrward lps f the APFC cntrller circuits are btained and their influence n the static and dynamic behavir f the APFC system is discussed. The thery is supprted by cmputer simulatin. Ke~wrds. PFC, mdeling. Intrductin Active Pwer Factr Crrectin (APFC) systems are generally designed arund high frequency cnverters that are cntrlled by tw feedbac lps. The average utput ltage is regulated by an uter lp whereas the inner lp shapes the line current [I]. The reference f the inner current lp is generated by mdulating the rectified pwer line ltage by the uter lp errr signal. Thus the magnitude f the reference is adjusted dynamically t cmply with the pwer requirements f the lad. The cntrl signal fr the inner lp, needed fr adjusting the current level, is cnveniently derived by cmparing the average current level t the desired reference value. The 3- lp APFC cntrller [-4] generates the current reference signal fr the inner lp by the multiplier-squarer-divider circuit as shwn at Fig. I. The inherent nn-linearity f the reference signal analg cmputatin blc and time varying gains f the pwer stage f the APFC systems pse a cntrl prblem. It is clear that the uter lp f the APFC must have nt nly a slw respnse (limited bandwidth) but als a lw gain s that the utput ripple will be heavily attenuated. Otherwise, while stabilizing the utput ltage, the utput ripple will distrt the input current by penetrating int the reference f the current lp. Hwever, the lw feedbac gain may result in a significant steady state errr, which is interpreted as pr utput ltage regulatin r high utput impedance. The bjective f this paper is t present simple static and dynamic mdels that culd be used in analysis and design f the 3-lp APFC systems. We btain the analytical expressins fr the gains f the feedbac and feedfrward lps f the APFC t characterize the systems lw frequency and static behavir. The prpsed mdels were investigated analytically and verified by simulatin. Basic relatinships The usual case f the APFC is when it is fed tm a AC line. The 3-lp APFC cntrller [-4] generals the current reference signal fr the inner lp by the multipliersquarer-divider circuit as shwn at Fig. I. When driven by a sinusidal line ltage vin (9) = y m sin9, the APFC generates the input current by the fllwing algrithm: iin (9) = Im sin9 = K ( Ye )( ~ }v m'in. ) () Fig. I. The 3-lp APFC system blc diagram. Here 9 is the pwer line angle. ve is the ltage feedbac errr amplifier signal and K is the system gain cnstant. Thus in it's steady state the input current is f a sinusidal shape and in phase with the input ltage. Its amplitude Im is directly prprtinal t the errr amplifier ltage ve and inversely prprtinal ltage V m : t the amplitude f the line Im=K(~) () Due t this relatinship, the average input pwer p av is independent f the amplitude f the line ltage and is a linear functin f the errr amplifier ltage: ImVm K Pav=~=ve(9) (3) The steady state ltage feedbac errr amplifier signal ve(9) appeared in the eq. () abve may be expressed as: ve(9)= (Ve-VT)+ve(9) (4) This expressin cntains a dc term, in bracets, and the secnd harmnics ripple cmpnent ve(9) as well. The term Ve represents the perating pint f the errr amplifier and VT is the threshld ltage f the divider input. The threshld VT set t be greater than the lw saturatin level f the errr amplifier. When the pwer demands f the lad drps, the errr amplifier signal swings belw the threshld, cutts ff the input current bringing the pwer level t zer. It is the difference (Ve -VT) which gverns the steady state pwer flw. The secnd harmnic cmpnent ve(9) at the utput f the ltage errr amplifier, appears as respnse t the utput ltage ripple. This signal is f a lw amplitude and

2 des nt cntribute significantly t the pwer flw and thus wuld nt be f ur cncern here. Hwever, it is ne f the main causes fr input current distrtin. The pwer gain cnstant As stated abve, the errr amplifier is the ne which gverns the steady state pwer flw. Hwever, since the dynamic range f the errr amplifier is limited, the chice f the pwer gain cnstant K shuld be cnsidered with sme care especially fr high pwer systems. The highest pwer transfer f the APFC f Fig. ccurs when the errr amplifier ltage is at its high saturatin level Ve = Vemax. Cmbining equatins (3), (4) we deduce that the minimum alwable value f the pwer gain cnstant Kmin t btain the full rated average pwer p max at the utput as: v Pmax Vemax -VT &'mm - ( ) (5) T ensure a prper peratin f the APFC ne shud design the system with a pwer gain K greater than the minimum value Kmin given by eq. (5) abve. The required pwer gain cnstant K may be fund as fllws. We assume that the pwer stage is capable f sustaining the input current thrughut the entire half cycle f the line perid and with the current lp clsed. tightly regulates the average input current iin (9). Fr line frequencies far belw the current lp crssver. the current lp gain rll-ff is negligible and the current gain f the inner lp may be apprximated by its DC gain which is determined by the current sensing netwr Rs. In the mst cmmn case Rs is just a series resistance. Thus, utput ltage f the current sensing netwr vs(9) = Rsiin(9) is frced t fllw the current prgramming signal vs(9) = vcp(9) generated at the multipliers utput. The inner lp transresistanse is therefre: iin (9) -=R (6) vcp(9) s Using this simplificatin and sme elementary netwr analysis, the pwer gain cnstant K may be fund as: Pav t K= ve -Rs 4 ~O where HfO is the lw pass filter (LPF) DC gain, the teidll. t is the average t pea rati f the rectified line ltage at the input f the LPF, these quantities appear in the denumeratr f eq. (7) due t the divider actin and are squared due t the squarer actin. The term = ~~ is the verall gain f the divider-multiplier-squarer circuits. Here p dentes the prprtinal gain which usually is refered by the manufacturer as the divider-multipli~-squarer gain. Other gain cnstants must be deteidlined ~rdingly t the resistances at the input and utput teidlinals f the dividermultiplier-squarer circuit. This is required because the multiplier perates with currents while the blc diagram f Fig. is rated in lts, thus fr the ltage fed inputs the assciated gain is unity. Fr the divider-multipliersquarer circuits using current inputs and utputs, the gain cnstants shuld be defined accrdingly t the resistances Rm and Rac cnnected t thse terminals as fllws: (7) ~=R. ac =Rm T ensure prper peratin f the APFC, that is, its ability t supply full pwer t the lad, the pwer gain cnstant K as defined by system parameters in eq. (7) has t be greater r equal t the minimum required value f the pwer gain as dictated by eq.(5): t Rm P max ---> (8) 4 Rac R S-0 H~ (V em ax -V T) The value f the pwer gain cnstant K is significantly ~ ~ -~-" ~," ' R ~ f the divider- lwered by the unfarable resistr rati R ac multiplier-squarer as appears in eq. (8). Hwever, the requirement K > Kmin as stated abve is pssible t fulfill in mst f the practical cases since the dc gain f the LP filter HfO is quite lw and the current sensing resistance Rs is made small fr the sae f lw pwer dissipatin. Bth f thse cnditins mae the ~ I term quite large and a RsHf reasnable value f K may be achieved t satisfy eq. (8). It is wrthwhile t mentin that the term () in the denminatr f eq. (3) represents the rati f the average t pea pwer f a sinusidal wave and the (;) term in the denminatr f eq.(7) is the dc t pea ltage rati f the rectified sinusidal wave. These cnstants are inherent t the sine-wave nly and represent wave shape cnstants. Feeding the PFC with input ltage f ther wavefrm (say dc ltage equivalent t the line ltage rms value r even strngly distrted sine) alters the afrementined relatinships. Vltage regulatin r the PFC The steady state DC errr ltage fr any errr amplifier cnfiguratin may be derived frm the abve given equatins (3), (4) and expressed in terms f the average input pwer as: Ve=KPav+VT (9) A cmmn errr amplifier tplgy is shwn at Fig. 3. The amplifiers utput ltage may be expressed as functin f the reference V ref and the utput V ltages f the APFC: V e = VrefHref -V H (0) here H and Href are the dc gain cnstants f the errr amplifier fr its inverting and nn inverting inputs. Fig. 3. Vltage errr amplifier cnfigllratin and its blc diagram.

3 ~ This relatinship states the dependence f the APFC utput ltage n its pwer level. In particularly we can see that the utput ltage f the APFC is a linear functin f pwer. Here we can recgnize the maximum utput ltage f the PFC fr the n lad cnditin as: ( Href YT ) Ymax= Yref~- ~ () and the utput ltage drp under lad as: ~Y=Ymax -Y=m-Pav (3) Substitute Pav = Y 0 and eq. () int () yields the dependence f the utput ltage n the utput dc current 0 as: V=Vmax (4) I + ~ 0 and the utput ltage regulatin as: Y Reg= y- = max + -- KH I (5) The minimum utput ltage which ccurs at full pwer is: Vmin =Vmax -~Pmax (6) As it was mentined abve, the APFC f Fig. supplies the lad a cnstant average pwer which is prprtinal t the errr amplifier signal, see eq. (3). Since the later is limited by its saturatin level Vemax' it inherently limits the pwer transfer t sme maximum value f P max. An attempt t increase the lad pwer beynd P max can nt be fulfllled by the APFC. Thus, in the case f an verlad by a cnstant pwer lad, such as dwnstream DC-DC cnverters, the APFC's utput ltage will drp and the system will eventually cease, hpefully by a prtectin circuitry. In the case f a resistive r cnstant current lad an verlad cnditin may be tlerable. A well designed system culd sustain the lad indefinitely with the APFC's utput ltage drped t maintain its maximum available pwer at the utput, that is VOvl = "p;:;;;il Pmax resistive lad RL and VOvl = -fr 0 current lad 0. Steady state DC mdel r the 3-p PFC fr a the cnstant We prceed t develp the steady state DC mdel f the APFC ltage lp asuming that the line ltage and the lad are eept cnstant. In mst f the practical cases the VT term H Href in eq.(6) abve is much lwer than Vref~ and may be neglected withut significant lss f accuracy. Thus maximum utput ltage may be fairly apprximated as: Href, Vmax = Vref~ (7) YO nw substituting equatin (7) bac int (4) we get We culd rewrite this as: (8) ( Href ~ t) Y=Yref H (9) + ( ~ )(Href~ t) Examining eq. (9) abve reveals that the ltage lp has the fllwing steady state dc characteristics. The steady state dc clsed lp gain is: Y AcL = -= AOL (0) Yref + ~AOL where the steady state dc pen lp gain may be recgnized as: the steady state dc feedbac lp gain as: ~= (HVO ~ ) () and the steady state dc lp gain as: ~AL = ( H ~ t) (3) Thus, the ltage lp may be mdeled by an equivalent scheme f Fig. 4. Eqs. (), (3) abve shw a clear dependence f the APFC lp gains n the lading. Under light lad cnditins, when the term t in the expressins abve tends t infinity. The resulting infinite lp gain ~AOL cuses the utput ltage t apprach its maximum value f Vmax. Under a heavy lad, the lp gain ~AOL as well as the clsed lp gain Ac L. decreases cusing the utput ltage t drp. Examining equatin (4) we can see that the utput ltage drp may be minimized by maximizing the prduct f the pwer gain cnstant K and the ltage errr amplifier gains "vo' "ref" Cnfiguring the errr amplifier as an integratr, with infmite DC gains, results in zer utput ltage drp under any permissible lad cnditins. Dynamic mdel r the uter lps r the 3-lp APFC We nw turn t develp the dynamic mdel f the 3-lp APFC system f Fig.l. Our basic assumptins are: a) the pwer stage is ideal, b) the current lp is ideal. c) there is n energy strage in the pwer stage. Assumptin (a) is justified by the high efficiency f the ff-line cnverters, which may be as high as 95% fr high ltage applicatins. Assumptin (b)!s deduced frm the fllwing reasning. Since the current lp bandwidth is high, its gain rll-ff is negligible within the extremely narrw frequency range defined by the uter lps bandwidth. Therefre, withut significant lss f accuracy, it is pssible t say that the inner lp is seen by the uter lps as if it is a frequency independent blc with fixed

4 gain. It is further assumed that the cnverter under clsed current lp has sufficient gain t frce the input current t fllw the lw frequency reference signal prduced by the multiplier -di vider -squarer: Ve V in lin = R (4) s V f Were V in' V f, Ve dente the instantaneus input, the feedfrward and the errr amplifier ltages respectively, and R ' as was already mentined abve, is the cmbined gain s f the inner lp and the multiplier-divider-squarer. see Fig. I. Due t the lw value f the cnverter inductr, the average energy strage thrughut the line perid is negligible when cmpared t the prcessed pwer. This fact justifies assumptin (c) abve. Treating the pwer stage as if it has n energy strage, we may use the pwer balance relatinship t btain the charging current Ich supplied by the pwer stage t the hld-up capacitr and the lad: V inlin Ve V in Ich ; = -(5) Y Rs V V f This set f tw nn linear but quit simple equatins characterize the actin f the pwer stage under the current lp cntrl tgether with the current shaping netwr (multiplier-divider-squarer) and may be regarded as the large signal mdel. They als culd be used t simulate the APFC circuits n general purpse circuit simulatrs such as SPICE and prvide a gd insight t the APFC peratin n the pwer line perid scale. Each f the equatins (4) and (5) abve may be expanded int multi-variable Taylr series arund the steady state perating pint. We apprximate the increments f the input current amplitude and utput charging current using nly the first rder terms f the expansin. Linearizatin yields a y parameter mdel fr input and utput circuits: i. = y..v. + y. v + Yif v f (6) I I le e i = Yivi + Yeve +Yfvf + Y (7) This new set f first rder linear equatins describe the dynamics f the small signal variatins, where the cefficients Yxx are the first rder partial derivatives and the lwercase ii' i' vi' ve' vf' V designate the small signal perturbatins f the apprpriate variables. Since the eqs. (4) and (5) are nn linear it is expected that their derivatives wuld depend n the perating pint. Therefre. the steady state perating pint cnditins have t be defined t quantify the Yxx cefficients. A natural chice is t defme the steady state perating pint f the APFC by the average value f the cntrl variables V., In Ve' V f' V. The average values f the cntrl signals f the feed frward and feed bac paths may be btained simply by neglecting their ripple cmpnents as fllws: the ave~age utput ltage as its.nminal ;DC value V = VOC. the steady state ltage at th~ utput f the Ye =- R -- -V rills ( 8 ) S V v f t find that the nns value f the line ltage V rms shud be used t calculate the Yxx parameters value. T be cnsistent with this reasning we define the ltage transfer rati M f the APFC as its dc utput ltage VDC t the rms line ltage V rms rati: Vc M= V \"'7 rms this will be useful t simplifiy the average mdel frmulae belw. The resulting expressins fr y parameters are summarized belw: - (~ ) -l-~ M y..- d -- v. ri -=RL ss Vrms (d ii ) K Yie= ~ ss= ~ (d ii ) 7t yit= ~ ss=-hfu~ y.- ~--.!E.!!) d -l- p a v - 0 v. M ss -=RL Vrms Ye= ~ ~ ich ) = VOC K e ss Y= ~ ~ ich ) = -~=- 0 SS ~~ M Pay! (30) ltage errr amplifier is the average signal which may be - fund frm equatin (3) as ve = K P av and the steady state ltage at the utput f the feed-frward filter as its average ~ { ltage vf = -Hf V m = -Hf V rms. The difficulty t t arises when ne cnsiders the chice f the steady state value f the line ltage t be substituted fr evaluatin f the derivatives y(xx). The candidates are the average

5 J The mdel may be applied in design and analysis f the feedbac and feed-frward lps f the 3-lp APFC system f Fig.. We ntice that resistance present in bth input and utput circuits. The small signal input resistance r. equals the steady state resistance emulated by the APFC twards the line. On the ther hand the small signal utput resistance r equals the equivalent lad resistance. Anther feature the mdel disclses prperly well, is the actin f the feed frward path. Indeed, it may be seen that the feed frward path acts against the line variatins in bth the input and the utput circuits. Hwever, the mst prminent feature f the feed frward is the stabilizatin f the ltage feedbac gain Ye which is made invariant f line amplitude variatins. In the usual case, when the average utput ltage is nly slightly depends n the lad, we may cnsider y e als t a gd extent, as lad independent. Simulatin results T chec the validity f the prpsed thery, the APFC circuit f Fig. was simulated by PSPICE prgram. The simulatin diagram is shwn at Fig. 6 and uses the large signal mdel f the pwer stage, eqs. (4), (5). The circuit parameters were set accrding t the manufacturer recmmendatin, as may be fund in references [3] and [4]. The multiplier terminal resistances and its threshld ltage were cded as parameters f the simulatin prgram and set t the fllwing values Rac = 90, Rm=4, VT=lV. The reference ltage was set t VreF 7.5V and the hld-up capacitr t C = 450~F. The errr amplifier saturatin levels were Vemax= 5.8V and Vemin= 0.V. The errr amplifier dc gains were fund as HreF 9.7, H= 0.35 and the LPF dc gain as Hf= Using eq. (7) the theretical pwer gain cnstant was fund as K= 3, and agreed well with that measured frm simulated wavefrms: K= 5.8. Fig. 7(a) shws the simulated wavefrms f the utput ltage V f the APFC laded with a cnstant pwer lad. As it is predicted by the thery, the utput ltage f the APFC, with fmite ltage errr amplifier dc gain, drps steadily with the increase in the pwer level. T create an errr ltage amplifier with an infmite dc gain the lcal feedbac f the amplifier f Fig. 3 was recnfigured int an series branch. With this imprvement the nminal utput ltage became V max=398.6v.as may be seen at Fig. 7(b) the APFC was able t eep its nminal ltage fr all permissible lading. The theretical maximum pwer level f the APFC was fund by eq. (7) as 7W, the inability f the APFC t sustain 300W lad is demnstrated at Fig. 8. The theretical value f the utput ltage as functin f pwer was calculated using eq. (). Fig. 9 presents a cmparisn between the theretical and simulated results. Gd agreement f the results is fund. Fig. 0 shws the dependence f the APFC's utput ltaje V n the multiplier's threshld level VT. Theretical value f the term ~ in eq.(6) was fund as.839v and stands in gd agreement with that measured frm simulatin wavefrms:.8v. The APFC's y -parameters set was calculated as suggested by equatin (30). Accrding t the data abve, we get: Yii= , Yir 0.936, Yie= 36.3, Yi= , Yf = f Fig. 5 the APFC with a resistive lad, RL = 580.Q, was simulated with its line ltage perturbed, by amplitude mdulatin. Cmparisn f the simulated wavefrms f bth circuits may be seen at Fig.. The input current (upper trace) and the utput ltage (lwer trace) f the APFC and its mdel are shwn as a respnse t the perturbed line ltage. A gd agreement f the "real" and equivalent circuits respnses may be fund. Cnclusins Simple static and dynamic mdels f the 3-lp Average Current Mde Active Pwer Factr Crrectin (APFC) system were suggested and analyzed. Analytical expressins fr the APFC's pwer gain cnstant and utput ltage regulatin as functin f circuit parameters where btained. Based n the y- parameter apprach. the small signal equivalent circuit f the uter lps f the APFC was presented. The thery was supprted by cmputer simulatin. The presented mdels described well the static and dynamic behavir f the system. The prpsed thery may be useful in the analysis and design f the uter lps f the 3-lp APFC systems. References [] Williams. I. B.: Design f feedbac lp in Unity pwer factr AC t DC cnverter. IEEE PESC 989 Rec., 989, pp [] Dixn. L. H.. "High pwer factr preregulatrs fr ffline pwer supplies", Unitrde Seminar Prceedings 990 [3] L. H. Dixn, "High pwer factr preregulatr design ptimizatin", Unitrde Seminar Prceedings 99 [4] P. C. Tdd, "UC3854 cntrlled pwer factr crrectin circuit design". Unitrde Applicatins Handb Fig. 6. PSPICE simulatin diagram f the "real" 3-lp APFC f Fig. I. 0.36, y = 4, y 0 =.74. T verify the prpsed mdel e