Pipelined and Parallel Recursive and Adaptive Filters

Transcription

1 VLSI Digital Sigal Processig Systems Pipelied ad Parallel Recursive ad Adaptive Filters La-Da Va 范倫達, Ph. D. Departmet of Computer Sciece Natioal Chiao ug Uiversity aiwa, R.O.C. Fall, 05

2 VLSI Digital Sigal Processig Systems Outlie Itroductio Pipelie Iterleavig i Digital Filter Parallel Processig for IIR Filter Combied Pipeliig ad Parallel Processig for IIR Filters Low-Power IIR Filter Desig Usig Pipeliig ad Parallel Processig Pipelied Adaptive Digital Filters Coclusios La-Da Va VLSI-DSP-0-

3 VLSI Digital Sigal Processig Systems Itroductio type of digital filters for time ivariat system: FIR IIR IIR is preferred sice it ca be implemet i a much lower order. Pipeliig techique: look-ahead computatio ad icremetal block processig techiques relaxed look-ahead trasformatios for pipeliig of LS ad lattice adaptive filters La-Da Va VLSI-DSP-0-3

4 VLSI Digital Sigal Processig Systems Outlie Itroductio Pipelie Iterleavig i Digital Filter Parallel Processig for IIR Filter Combied Pipeliig ad Parallel Processig for IIR Filters Low-Power IIR Filter Desig Usig Pipeliig ad Parallel Processig Pipelied Adaptive Digital Filters Coclusios La-Da Va VLSI-DSP-0-4

5 VLSI Digital Sigal Processig Systems Pipelie iterleavig i Digital Filters Iefficiet sigle/multi-chael iterleavig Efficiet sigle-chael iterleavig Efficiet multi-chael iterleavig La-Da Va VLSI-DSP-0-5

6 VLSI Digital Sigal Processig Systems Iefficiet Sigle/ulti-chael Iterleavig Cosider y+=ay+bu Iteratio period= m a La-Da Va VLSI-DSP-0-6

7 VLSI Digital Sigal Processig Systems Iefficiet Sigle/ulti-chael Iterleavigcot. -stage pipelie versio:isert - additioal latched Clock period decrease timesex:=5 For a sigle time series this array will be useful for oly 0% of the time If 5 idepedet time series are available ==> fully utilized Cosequece: A sample rate times slower tha the clock rate iefficiet utilizatio of processig elemets La-Da Va VLSI-DSP-0-7

8 VLSI Digital Sigal Processig Systems Iefficiet Sigle/ulti-chael Iterleavigcot. La-Da Va VLSI-DSP-0-8

9 VLSI Digital Sigal Processig Systems Efficiet Sigle-Chael Iterleavig Usig look-ahead trasform. Cosider: y+=a[ay+bu]+bu+ Iteratio boud= m + a / La-Da Va VLSI-DSP-0-9

10 Efficiet Sigle-chael Iterleavigcot. VLSI Digital Sigal Processig Systems Aother recursio equivalet equatio: y+=a y+abu+bu+ Iteratio period boud: m + a / La-Da Va VLSI-DSP-0-0

11 Efficiet Sigle-chael Iterleavigcot. VLSI Digital Sigal Processig Systems -steps of look-ahead y a y i0 Iteratio boud: m + a / i a bu i La-Da Va VLSI-DSP-0-

12 Efficiet Sigle-chael Iterleavigcot. VLSI Digital Sigal Processig Systems I a causal system, to perform as before: y=ay0+b0 IF =5 y=a 5 y-4+bu0 u-4,u-3,,u-=0 for causality y-4=a -4 y0 y-i=a -i y0, i=,,.,- he iteratio boud ca be achieved by retimig or cutset trasform La-Da Va VLSI-DSP-0-

13 VLSI Digital Sigal Processig Systems Efficiet ulti-chael Iterleavig La-Da Va VLSI-DSP-0-3

14 VLSI Digital Sigal Processig Systems Outlie Itroductio Pipelie Iterleavig i Digital Filter Parallel Processig for IIR Filter Combied Pipeliig ad Parallel Processig for IIR Filters Low-Power IIR Filter Desig Usig Pipeliig ad Parallel Processig Pipelied Adaptive Digital Filters Coclusios La-Da Va VLSI-DSP-0-4

15 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-5 Example 0.5. /3 Cosider the followig trasfer fuctio architechturel cosider 4 - parallel, k u k u a k u a k u a k y a k y k substitutig u u a u a u a y a y i a bu y a from y u ay y az z z H i i

16 VLSI Digital Sigal Processig Systems pole: z=a ==> z=a 4 Example 0.5. /3 sice a <, a 4 < a, which is closer to the origi ==> improve robustess of the system La-Da Va VLSI-DSP-0-6

17 Next:u4k+7,u4k+8,u4k+9,u4k+0 VLSI Digital Sigal Processig Systems u4k+ u4k+ u4k La-Da Va VLSI-DSP-0-7

18 VLSI Digital Sigal Processig Systems Parallel Processig for IIR Filters Need L multiply-add operatios: hardware cost is high use icremetal block processig to simplify hardware: use y4k to compute y4k+ use y4k+ to compute y4k+ use y4k+ to compute y4k+3 La-Da Va VLSI-DSP-0-8

19 VLSI Digital Sigal Processig Systems Example 0.5. / icremetal block processig sice y+=ay+u y4k+=ay4k+u4k y4k+=ay4k++u4k+ y4k+3=ay4k++u4k+ La-Da Va VLSI-DSP-0-9

20 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-0

21 VLSI Digital Sigal Processig Systems Example /3 System rasfer Fuctio: L=3 La-Da Va VLSI-DSP-0-

22 VLSI Digital Sigal Processig Systems Example /3 La-Da Va VLSI-DSP-0-

23 VLSI Digital Sigal Processig Systems Example /3 y3k+4 y3k+3 La-Da Va VLSI-DSP-0-3

24 VLSI Digital Sigal Processig Systems Parallel Processig for IIR Filters For N-th order IIR filter, its L-level icremetal parallel processig architecture ca be obtaied by computig the first N output samples ylk,ylk+,,ylk+n- idepedetly usig loop update equatios obtaied by clustered look-ahead techique ad the computig the remaiig L-N samples ylk+n,ylk+l- icremetally usig the previous N output samples La-Da Va VLSI-DSP-0-4

25 VLSI Digital Sigal Processig Systems Outlie Itroductio Pipelie Iterleavig i Digital Filter Parallel Processig for IIR Filter Combied Pipeliig ad Parallel Processig for IIR Filters Low-Power IIR Filter Desig Usig Pipeliig ad Parallel Processig Pipelied Adaptive Digital Filters Coclusios La-Da Va VLSI-DSP-0-5

26 VLSI Digital Sigal Processig Systems Cosider: =4,L=3 Example 0.6. /3 H z az La-Da Va VLSI-DSP-0-6

27 VLSI Digital Sigal Processig Systems Example 0.6. /3 La-Da Va VLSI-DSP-0-7

28 VLSI Digital Sigal Processig Systems f 3k+9 f 3k+6 La-Da Va VLSI-DSP-0-8

29 VLSI Digital Sigal Processig Systems Outlie Itroductio Pipelie Iterleavig i Digital Filter Parallel Processig for IIR Filter Combied Pipeliig ad Parallel Processig for IIR Filters Low-Power IIR Filter Desig Usig Pipeliig ad Parallel Processig Pipelied Adaptive Digital Filters Coclusios La-Da Va VLSI-DSP-0-9

30 VLSI Digital Sigal Processig Systems Example 0.7. / Cosider: V 0 =5V,V t =V H z.5548z z z.4996z 0.848z by scattered look - ahead techique with power- of - decompositio : N z z z Z.4996z 0.848z.88z 0.46Z z 0.794z 4 D z z z 8.337z z 8 La-Da Va VLSI-DSP-0-30

31 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP where, where, ,, where, tage use lower supply vol ca smaller capacitace path shorter cretical pipelie: 4 - level arg 0 arg 0 0 seq pip pip s pip pip pip total par seq s seq seq total seq pip e ch pip e ch t total P P Ratio m f C m C P m f C m C P V V k C V k C V V k V C Example 0.7. /

32 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-3 Cosider L=3 9.6% , 3 sice propogatio delay 0.6, seq par s o s o par s o seq o seq par t o o par t o o seq t o P P Ratio f V C f V C P f V C P V V V V k V C V V k V C V V V V u u u y y y Example 0.7. /

33 VLSI Digital Sigal Processig Systems Example 0.7. / La-Da Va VLSI-DSP-0-33

34 VLSI Digital Sigal Processig Systems Outlie Itroductio Pipelie Iterleavig i Digital Filter Parallel Processig for IIR Filter Combied Pipeliig ad Parallel Processig for IIR Filters Low-Power IIR Filter Desig Usig Pipeliig ad Parallel Processig Pipelied Adaptive Digital Filters Coclusios La-Da Va VLSI-DSP-0-34

35 VLSI Digital Sigal Processig Systems Itroductio to a Adaptive Algorithm Adaptive filter: filter with adaptive coefficiet geeral filter block coefficiet update block Widely used i commuicatio, DSP, ad cotrol system Determiistic gradiet / least square algorithm Steepest descet algorithm RLS algorithm Stochastic gradiet algorithm LS algorithm, DLS algorithm Block LS algorithm Gradiet Lattice algorithm Difficult to pipelie due to the presece of log feedback loops Relaxed look-ahead trasformatio techique is used to pipelie the adaptive filter with little or o icrease i hardware at the expese of margial degradatio i the adaptive behavior La-Da Va VLSI-DSP-0-35

36 VLSI Digital Sigal Processig Systems Adaptive Applicatios Chael equalizer System idetificatio Image ehacemet Echo caceller Noise cacellatio Predictor Lie ehacemet Beamformer IO-ODF: V-BLAS La-Da Va VLSI-DSP-0-36

37 VLSI Digital Sigal Processig Systems Notatio. Iput Sigal: X. Desired Output: d 3. Weight Vector: W 4. Adaptatio Factor: μ 5. Error: e 6. isadjustmet: adj 7. ap Number: N 8. Autocorrelatio atrix: R 9. Eigevalue:λ 0. Diagoal atrix : La-Da Va VLSI-DSP-0-37

38 VLSI Digital Sigal Processig Systems where Steepest Descet Algorithm y W X X [ x x... x N ] Note: W [ w0 w... w N ] SSS Strict-sese statioary: A stochastic process xt is called SSS if its statistical properties are ivariat to a shift of the origi. WSS Wide-sese statioary: E{ x t} E{ x t x * t} R La-Da Va VLSI-DSP-0-38

39 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-39 Steepest Descet Algorithm /8 W X d X W d y d e W X X W W X d d e he error at the -th time is

40 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-40 Steepest Descet Algorithm /8 } { } { } { } { } { RW W W P d E W X X E W W X d E d E e E J.. } { N x d x d x d E X d E P

41 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-4 Steepest Descet Algorithm 3/ } { * * * r L r L r L r r r L r r r X X E R } { x * x E r

42 VLSI Digital Sigal Processig Systems Steepest Descet Algorithm 4/8 ake gradiet J P RW Let J 0 W opt R P Wieer-Hopf equatio 949 or Wieer Filter ca be obtaied!! La-Da Va VLSI-DSP-0-4

43 VLSI Digital Sigal Processig Systems Steepest Descet Algorithm 5/8 J E{ d } mi P Wopt J J mi E{ W W opt R W W opt } C W W opt J J mi E{ C RC } La-Da Va VLSI-DSP-0-43

44 VLSI Digital Sigal Processig Systems Steepest Descet Algorithm 6/8 Assume :Symmetricad PositiveDefiitive for Iput Sigal R QQ QQ where diag[ 0... L ] ad Q are orthogoal matrix of R J J J mi mi E{ V E{ C wherev Q V} QQ C C } La-Da Va VLSI-DSP-0-44

45 VLSI Digital Sigal Processig Systems Steepest Descet Algorithm 7/8 Each chage i the weight vector proportioal to the egative of the gradiet vector W W J W P RW La-Da Va VLSI-DSP-0-45

46 VLSI Digital Sigal Processig Systems Steepest Descet Algorithm 8/8 W W J Wopt R P C W Wopt V V V V V 0 I V I - k for all k V max La-Da Va VLSI-DSP-0-46

47 VLSI Digital Sigal Processig Systems LS Algorithm A efficiet implemetatio i software of steepest descet usig measured or estimated gradiets he gradiet of the square of a sigle error sample W W ˆ J ˆ J e X W W μex w0, w, w0 La-Da Va VLSI-DSP-0-47

48 VLSI Digital Sigal Processig Systems Summary of LS Adaptive Algorithm 960 y w x e d y w w e x La-Da Va VLSI-DSP-0-48

49 VLSI Digital Sigal Processig Systems Block Diagram of a Adaptive FIR Filter Drive by the LS Algorithm x z x x x N z z w w w w N 0 y d e La-Da Va VLSI-DSP-0-49

50 VLSI Digital Sigal Processig Systems Adaptive Digital Filter Structure La-Da Va VLSI-DSP-0-50

51 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-5 Relaxed Look-Ahead /6 Cosider: ] [ 0 0 u i u j a y i a y u y a y i i j i

52 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-5 Relaxed Look-Ahead /6 Product Relaxatio ] [ to zero close is if to uity close is a if i i j i i u y a y i u i u j a i u a a i a

53 VLSI Digital Sigal Processig Systems Relaxed Look-Ahead 3/6 Aother approximatio: La-Da Va VLSI-DSP-0-53

54 VLSI Digital Sigal Processig Systems Relaxed Look-Ahead 4/6 Sum relaxatio if u varies slowly over cycles the i0 u i u if u is close to zero the u ca be approximated by u La-Da Va VLSI-DSP-0-54

55 VLSI Digital Sigal Processig Systems Relaxed Look-Ahead 5/6 La-Da Va VLSI-DSP-0-55

56 VLSI Digital Sigal Processig Systems Relaxed Look-Ahead 6/6 Delay relaxatio -level look-ahead pipelied versio assume that the product au is more or less costat over samples La-Da Va VLSI-DSP-0-56

57 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-57 Pipelied LS Adaptive Filter /3 ' : ' over samples,use sum relaxatio much ot chage assume that thegradiet estimate eu does : delay relaxatio -stage look - ahead e tomiimize ˆ i i i i U i e W W i U i e W W i U i e W W U e W W U W d d d e

58 VLSI Digital Sigal Processig Systems La-Da Va VLSI-DSP-0-58 Pipelied LS Adaptive Filter /3 by ad replace small sufficietly is assume ] [ ˆ ' 0 U W d e W W U i U i e W d U W d d d e i

59 VLSI Digital Sigal Processig Systems Pipelied LS Adaptive Filter 3/3 La-Da Va VLSI-DSP-0-59

60 VLSI Digital Sigal Processig Systems Coclusios Itroduce the pipelie filter desig Itroduce the parallel filter desig Explore Relax-Look ahead techiques Demostrate the cocept ad desig of adaptive filters La-Da Va VLSI-DSP-0-60