Cool Chips Technical Overview

Transcription

1 Slide 1 Cool Chips plc Cool Chips Technical Overview

2 Slide 2 Technology Introduction e - = Cool Chips can be shown as a simple schematic using a classic diode. Cool Chips are based off of a technology called a Thermionic Converter. Thermionics are an old technology; invented about Significant development occurred in the US during the 1950s and 60s, by companies like GE and General Atomics. The development effort was virtually abandoned by the mid-1970s. The reasons were simple: the devices did not work unless the two large plates were very close (microns) together, and in a time when semiconductor technology was still undeveloped, this meant hand-assembly. Complicating this was the second factor: in order to function, the thermionic converter required a cesium environment. Cesium is very difficult to work with in hand assembly. So while the technology was moderately efficient, it was not economic. Borealis has solved both of these problems. We can mass-produce, and we have no materials problems. This is solved in large part because the device is not a classic thermionic device. Cool Chips create a thermal difference (pump heat) from inputted power. Because of our solutions, we can operate at very low temperatures, something which classic thermionic converters could never do. And so we have the Cool Chip.

3 Slide 3 Physics Overview Thermionic Converter d=1-10 micron Thermotunnel Converter d=1-10 nm EF EF EF ev EF ev The Thermionic Converter, to minimize space charge, has a distance between the plates on the order of 1-10 microns. This is a gap which can be readily built using today s technology (Borealis has built centimeter-scale chips which have 0.5 micron gaps). The manufacturing problem which ended research in the West by the early 1970s has clearly been solved. However, the other problems remain. In order to get an electron to jump over the barrier, it must have a low work function. The lowest work function materials are based on Alkali metals such as cesium, and they approach 1 ev. Most metals are in the 4-5eV range. At 4-5eV, copious emission does not occur until the cathode is very hot -- hotter than 2000 K. Some metals melt before they emit electrons. Thoriated tungsten, which is used for cathode ray tubes, is heated to 1,950 K. Cooling at these elevated temperatures is not generally useful. So thermionics require a very low work function material. The problem is that these materials have not been found, despite much searching. However, there is another approach which has all the same advantages as thermionics. If the two electrodes are close enough to each other, electrons do not need to jump over a barrier. Under the well-known laws of quantum mechanics, they can tunnel from one side to another. The distance must be on the order of 1-10 nanometers, or 1-10 billionths of a meter. This is much more challenging to build than a 10 micron gap, but if it can be built, there are several key advantages. 1. No low work function material is required. Standard materials can be used. 2. If the spacing is right, the cooling density can in theory be as high as 5000 watts/square centimeter. 3. Lower temperature operation is possible, allowing for temperatures well below freezing, and a broader range of applications. 4. Since the electrons tunnel from one side to the other, there is no space charge. This leads to a large increase in the theoretical efficiency.

4 Slide 4 Physics Overview Theoretical Efficiency Work at Stanford calculated the theoretical output of a thermotunnel device with a vacuum gap + Third-party verification of theory Does not challenge Borealis ownership of the technology Does not pre-date Borealis work Paper published 4 years after Borealis initial patent filings + (Hishinuma Y, Geballe TH, Moyzhes BY, Kenny TW (2001) Refrigeration by combined tunneling and thermionic emission in vacuum: use of nanometer scale design. Applied Physics Letters 78(17): ) The theoretical underpinnings of thermotunneling are well established. There is considerable research showing tunneling characteristics through an insulator, and there is some work discussing tunneling across a gap. But with the exception of work done at Stanford, there is no discussion in the literature about cooling across a gap using thermotunneling. The Stanford paper showed the relationship between the work function of the materials used, the spacing between the electrodes, and the resulting cooling densities which can be achieved. It is recommended that this paper be reviewed carefully when evaluating Cool Chips. For intellectual property reasons it is important to note that the Borealis work in thermotunneling predated that at Stanford by several years. And while the Stanford paper presents an excellent discussion of the theory, no practicable device is presented -- and therefore, there is nothing patentable in the Stanford paper.

5 Slide 5 Prior Devices F.N. Huffman, F.N. Huffman, 1985? Al Al2O3 Al Thickness 2 nm Intercalated Graphite, Cesium - GIC + F.N.Huffman et. al.. Thermotunnel Converter patent 3,169,200 (1965)? F.N.Huffman (1985) Other work in thermotunneling has been done in the past. This work faced several problems which hampered efforts, and prevented development of a workable technology. Fred Huffman worked on thermotunneling for at least a 20 year period. His idea was to use aluminum layers, insulated from each other using thin aluminum oxide layers. The basic premise and physics of this approach is sound, but it suffers from a key problem: as the temperature difference grows, the heat conduction through the very wide and thin insulating layer grows as well. The device was so inefficient with a large T that approximately 1 million layers would be needed to have a useful cooling device. This was clearly uneconomic. 20 years later, Huffman patented the same invention using a better insulator in the middle. This approach requires fewer layers, but the number is still on the order of 100,000 layers. This approach to thermotunneling is quite similar to thermoelectrics. Also called Peltier Devices, these devices resemble the Huffman approach of stacked materials, except that they do not use thermotunneling as the cooling mechanism. But thermoelectrics suffer from precisely the same efficiency problem: there is a large thermal backpath. This problem has been met by attempts to find materials which conduct electricity but thermally insulate. This coefficient, also called ZT, needs to be very high in order to have efficient cooling. Current thermoelectrics in production are 5-8% efficient (measured as a percentage of maximum theoretical cooling). Some new approaches may yield efficiencies on the order of 20-30%. But the ideal insulation material is not a material at all. A vacuum is a better thermal insulator than any solid, and it presents no obstacle for tunneling electrons. The Cool Chips solution is to have a physical gap between the electrodes, which allows for excellent thermal insulation and high electrical conductivity. The result is a technology capable of a T of several hundred degrees in a single stage, with very high efficiency and power density.

6 Slide 6 Development Roadmap, January 2003 Conception Patenting Test Machine Development Sandwich Development Proof of Concept: Tunneling >10 amps Production Design Macro Issues Micro Issues Materials Integration Completion of Working Devices Current Status The Development Roadmap shows what has been achieved, and what lies ahead. Borealis has been working on thermionic cooling since 1994, and the thermotunneling concept was a result of that earlier work. The basic invention of thermotunneling across a gap was completed several years ago, and patenting commenced then. To date, we have completed Sandwich development, and testing inside the test machine. The proof of concept experiment, showing tunneling currents across a gap on the order of 10 amps, was completed in the first half of Production designs are now being explored, and this is expected to continue. The gaps between the electrodes look good, with both broad Macro conformity, and very low surface roughness Micro. The last step before we expect to produce useful working devices is the integration of necessary thin films in the gap.

7 Slide 7 Test Machine Interelectrode Gap Regulation using Piezo Positioners Side View Capacitance sensors Top-down View Gap Piezo positioners with 0.1 nm accuracy The critical notion then, for understanding what makes Cool Chips unique, is that it uses thermotunneling across a gap. The gap itself, however, is very small. Nanometer spacing is very difficult to achieve, and even once it is achieved, maintaining the gap can be problematic. The solution is borrowed from standard Scanning Tunneling Microscopes (STM). In those devices, a very small tip is controlled by a piezo element. Piezo elements are single crystal quartz structures which change their shape, extremely rapidly and precisely, in response to applied voltages. The STM uses a feedback loop to keep the tip close to, but not touching, the surface. The closer two surfaces come to each other, the more current flows across the gap. Capacitance sensors measure that current flow, and provide feedback through an analog loop to control the voltages going to the piezo tube. The Test Machine, which was completed a few years ago (a picture is on Slide 10), uses this same technique, albeit on a larger scale. The piezo elements (shown as green) change their length to keep the electrodes close to each other, but not touching. The speed, accuracy, and reliability of piezo units and this solution means that the device can withstand any external vibration (short of crushing), and thermal gradients between the electrodes of up to 400 C. It is a very rugged solution. The thermal gradient is achieved in part by selecting materials for the anode and cathode which have very different thermal expansion coefficients. Broad surface matching can then be achieved for a large swing in temperature for any given thermal operating range.

8 Slide 8 Sandwich Development Limits of Electrode Polishing Technology 1 cm Collector 0.5 micron Emitter The problem with broad-based thermotunneling across a gap is that the gap required is dwarfed by the amount of unevenness found in any surface. Large, perfectly flat surfaces are almost impossible to create, and they would certainly be too expensive for market production. The best polished surfaces available today, such as a silicon wafer, vary by about 0.5 microns across a square centimeter. 0.5 microns is 500 nanometers, and Cool Chips require spacing on the order of 1-10 nanometers, and this precise spacing needs to spread across much of the area of the electrode. Clearly two polished surfaces cannot be used.

9 Slide 9 Sandwich Development Matching Collector and Emitter Surfaces The Borealis solution is to avoid the need for flat surfaces, and instead have surfaces which match one another. First, we start with a polished silicon wafer. Then we deposit a thin film of titanium on the silicon. The titanium bonds well with the silicon, and provides the metal face for high thermal and electrical conductivity. Then a thin film of silver is deposited on the titanium, with the adhesion between the two carefully regulated. A copper top is then electrochemically grown on the silver. The silicon and the copper have very different thermal expansion coefficients. Freezing the sandwich separates the two electrodes cleanly across the titanium-silver barrier, and the two sides move apart. They can then be brought more closely together, and operate as a tunneling converter. In this way, two surfaces can be made which mirror each other, and which can be brought close enough to allow for copious tunneling currents.

10 Slide 10 Sandwich and Test Machine Photographs of Sandwich Mounting Inside Test Machine This slide shows the test machine (in the center, with tubes connected) and the test sandwiches lined up in the rack to the right. The tubes provide a vacuum source for the test machine. The alligator clips lead to a micrometer which measures voltage and current.

11 Slide 11 Proof of Concept IV CURVE The Proof of Concept was achieved when tunneling currents on the order of 10 amps were measured across a gap. This is several orders of magnitude more current than has ever been reported before in a vacuum tunneling diode at room temperature. The active area for these sandwiches remains pretty small (<1 mm), but is vast in comparison to the nm spacing in the other dimension. Once the Proof of Concept was completed, the task was to increase the active area, so that a significant percentage of the electrodes had the required spacing. At the same time, with an eye on production, Borealis has been working on designing a solution which can be mass-produced, inexpensively. Devices must be easy to fabricate in a dedicated facility. This work moves in parallel with increasing the output of the devices.

12 Slide 12 Development Roadmap, January 2003 Conception Patenting Test Machine Development Sandwich Development Proof of Concept: Tunneling >10 amps Production Design Macro Issues Micro Issues Materials Integration Completion of Working Devices Current Status The Development Roadmap shows what has been achieved, and what lies ahead. Borealis has been working on thermionic cooling since 1994, and the thermotunneling concept was a result of that earlier work. The basic invention of thermotunneling across a gap was completed several years ago, and patenting commenced then. To date, we have completed Sandwich development, and testing inside the test machine. The proof of concept experiment, showing tunneling currents across a gap on the order of 10 amps, was completed in the first half of Production designs are now being explored, and this is expected to continue. The gaps between the electrodes look good, with both broad Macro conformity, and very low surface roughness Micro. The last step before we expect to produce useful working devices is the integration of necessary thin films in the gap.

13 Slide 13 Macro Issues Tasks Development of smaller sandwich (done) Reduction of electrode surface area can increase percentage of active area Electrochemical growth temperature stabilization (done) Electrochemistry process review Cyanide processing may yield higher quality sandwiches. This is optional. Better control of production steps (done) Increased control and understanding of these steps will increase yields Stress free, conformal wafers have been completed. We recently completed what we term the Macro Issues. This was improving the sandwich recipe such that when the electrodes are separated, and then brought back close together, they are broadly conformal. The electrodes need to have a good conformal fit to allow for electron tunneling. In order to increase yields, it is important to first reduce the size of the chips themselves. Production chips, for a number of reasons, will be no larger than 1 square cm, and we have now produced chips of that size (down from 9 square cm). The macro issues become much less problematic when working with a smaller area. In other steps, temperatures have been stabilized, and the overall quality of the process is improved. Note that all the work completed to date has been done in an standard lab environment -- not a clean room. Even a poor quality clean room would certainly improve yields and results. The same is true if better equipment were to be applied. But the production of conformal wafers shows that this step has been completed.

14 Slide 14 Micro Issues, October 2002 SEM and Profilometer testing revealed that there are no local roughness issues precluding the fabrication of high output devices, once the necessary electrode material has been integrated. The smoothness of the wafers are as shown in the following slides.

15 Slide 15 Micro Issues - SEM Imaging Titanium Surface at 20000X Titanium Surface at 60000X This is the bottom electrode, the first layer on top of the Silicon substrate. Images captured with a Scanning Electron Microscope (SEM) lacked sufficient resolution to adequately profile surface roughness. For proper analysis, resolution should be on the order of approximately 5 Angstroms. At the resolution shown here, surfaces appear to be perfectly smooth. In fact, because of this perfect smoothness, the technicians went so far as to recalibrate the SEM equipment to confirm that the images were accurate. The conclusion was that an Optical Interferometry Profilometer would be required to collect data with the necessary resolution.

16 Slide 16 Micro Issues - Profilometry These images represent the Silver layer of the top electrode surface. The results are superb. The local roughness is less than 1 nm, and as such is at the smoothness required for high output devices. REFERENCE: The filled contour plot is a 2 dimensional plot which shows the surface heights as viewed along the instrument's z axis (a bird's eye view). Different heights are represented by different colors. Red shows high points and violet shows low points. The horizontal lines found in the filled contour plot represent the data slice or slices found in the Profile Plot. Oblique plot is a three dimensional display of the data with the x-axis horizontal, the y-axis inclined from horizontal, and the z-axis vertical. Areas with different magnitudes (height) are represented by different colors. Red shows high points and violet shows low points. Measurements are generated using 20x Mirau Objective at 2.0x zoom. PV = peak to valley Ra = The average surface roughness, or average deviation, of all points from a plane fit to the test part surface (this is the most important measurement for developing high output devices). rms = The root-mean-square average of the measured height deviations taken within the evaluation length or area and measured from the mean linear surface.

17 Slide 17 Micro Issues - Profilometry These images represent the Silver layer of the top electrode surface. The results are superb. The local roughness is less than 1 nm, and as such is at the smoothness required for high output devices. REFERENCE: The filled contour plot is a 2 dimensional plot which shows the surface heights as viewed along the instrument's z axis (a bird's eye view). Different heights are represented by different colors. Red shows high points and violet shows low points. The horizontal lines found in the filled contour plot represent the data slice or slices found in the Profile Plot. Oblique plot is a three dimensional display of the data with the x-axis horizontal, the y-axis inclined from horizontal, and the z-axis vertical. Areas with different magnitudes (height) are represented by different colors. Red shows high points and violet shows low points. Measurements are generated using 20x Mirau Objective at 2.0x zoom. PV = peak to valley Ra = The average surface roughness, or average deviation, of all points from a plane fit to the test part surface (this is the most important measurement for developing high output devices). rms = The root-mean-square average of the measured height deviations taken within the evaluation length or area and measured from the mean linear surface.

18 Slide 18 Micro Issues - Profilometry For comparison, this is the perfect flat surface used for calibration. REFERENCE: The filled contour plot is a 2 dimensional plot which shows the surface heights as viewed along the instrument's z axis (a bird's eye view). Different heights are represented by different colors. Red shows high points and violet shows low points. The horizontal lines found in the filled contour plot represent the data slice or slices found in the Profile Plot. Oblique plot is a three dimensional display of the data with the x-axis horizontal, the y-axis inclined from horizontal, and the z-axis vertical. Areas with different magnitudes (height) are represented by different colors. Red shows high points and violet shows low points. Measurements are generated using 20x Mirau Objective at 2.0x zoom. PV = peak to valley Ra = The average surface roughness, or average deviation, of all points from a plane fit to the test part surface (this is the most important measurement for developing high output devices). rms = The root-mean-square average of the measured height deviations taken within the evaluation length or area and measured from the mean linear surface.

19 Slide 19 Materials Integration Select thin films (known cesiated materials) for a given thermal regime Integration of films Tasks Work has commenced, and is expected to take some months to complete The last remaining step is to lower the work function of the electrodes. Because the technology relies on tunneling, and not thermionics, the work functions required are on the order of ev (which are off-theshelf), and not 0.3 ev (which may not exist). The simplest solution is simply to apply a cesium compound to the interior of the chip. There are other materials solutions using alkali compounds which have higher work functions. These may have their own advantages, but cesium would do the job for any anticipated cooling load. Over time, different desired operating parameters will result in variations in the materials used. Lab work is underway.

20 Slide 20 Conclusion of Development Once prior steps are complete, high output, high efficiency Cool Chips will be ready for: Application in high-margin low-volume applications Transition to mass production in dedicated fab Every stage discussed to date occurs in a lab, so lab-scale production of Cool Chips will be the next logical step. The product of lab assembly would be used for testing, applications engineering, operating within certain high performance applications. Initial sales for these applications (which include defense and space applications) would bring the project cash flow positive even before a dedicated fabrication plant came on line to drop the prices to make Cool Chips competitive in low-margin business such as automotive and domestic refrigeration.

21 Slide 21 Efficiency Calculation Intrinsic Efficiency Practical Efficiency Types of Calculations The efficiency of the devices can be understood as two separate pieces: 1: The intrinsic efficiency, considering only the physics of the cooling mechanism 2: The practical efficiency, allowing for losses which occur in real-world devices. These figures are only rough estimates, but they allow for some general conclusions about the efficiency of the Cool Chips technology. These will be taken in turn.

22 Slide 22 Efficiency Calculation Intrinsic Output Calculation Intrinsic output calculations were developed at Stanford + Output up to 5000 watts/cm 2 is projected for room temperature cooling. Projected intrinsic efficiency for Cool Chips is on the order of 65% of Carnot (Maximum possible COP) at outputs of 3-5 watts/cm 2. + (Hishinuma Y, Geballe TH, Moyzhes BY, Kenny TW (2001) Refrigeration by combined tunneling and thermionic emission in vacuum: use of nanometer scale design. Applied Physics Letters 78(17): ) The Stanford paper developed the output figures for tunneling across a gap, and those figures are large. The intrinsic efficiency for Cooling using thermotunneling is high.

23 Slide 23 Theoretical Efficiency The graph is the reproduction of Fig 3 from the Stanford paper. The vertical scale is Watts/cm2 cooling power, the horizontal scale is electric field. This is calculated from E= Vbias/gap size. This quantity scales for example, double both the gap size and the applied voltage and the electric field is the same. Thus it provides a good means of displaying the characteristics of these devices.. The three curves for each work function (in ev) are for temperatures of 200K, 250K and 300K. 300K gives the upper of the three lines.

24 Slide 24 Efficiency Calculation Practical Losses Loss terms for Cool Chips include: Radiation Residual gas Resistive heating Thermal backflow As losses are temperature dependent, they are all calculated as a percentage of Carnot efficiency (maximum possible COP) The calculations presented in this section cover all the major loss terms. To make sure the conclusions are conservative, the assumed heat flux is 3 watts/cm 2. Practical losses will be reduced with increased output.

25 Slide 25 Efficiency Calculation Radiative Losses Radiation losses are proportional to T hot side 4 -T cold side 4. Dropping the temperature by a factor of 5 reduces radiation losses by factor of 625. The Stanford paper predicts <0.1 W/cm 2 at room temperature for black box radiation. Real losses are lower. Effect on Carnot Efficiency Radiation losses are negligible (<1%) Any hot surface radiates heat (which is how the sun works through vacuum). But radiation is very closely tied to the temperature of the hot side. For Cool Chips parameters, the loss is on the order of 1% of Carnot. Radiation is not a significant loss term.

26 Slide 26 Efficiency Calculation Residual Gas Losses Residual gases, a product of all imperfect vacuums, will be an additional efficiency loss term. Effect on Carnot Efficiency <1% due to the small distance between the emitter and collector, which is less than the mean free path of the gas electrons: Residual gases are a problem in classic thermionic converters, which have comparatively large spacing between the anode and cathode. For Cool Chips, the observed thermal conductivity of a gas in an area which is measured in nanometers is less than 1%. This effect, while counterintuitive, has been well documented in the literature, What this slide means is that Cool Chips do not require a vacuum environment. The space between the electrodes can be filled with an inert gas, at atmospheric pressure. This makes sealing the device far simpler, and certainly prolongs its lifespan.

27 Slide 27 Efficiency Calculation Resistive Losses and Heat Conduction Losses via Electrical Connections in an Array 52 C 25 cm 10 A 25 cm 35.5 V 7 C Effect on Carnot Efficiency Using copper, the losses are 12%, depending on assumptions. If a superior connector material is identified, these losses could be partially mitigated. Cool Chips will operate in an array. Because each device uses a high amperage, and a low voltage, it will be most useful to wire them electrically in series, and thermally in parallel. This keeps the amperage constant, and boosts the voltage into the normal range. There are two kinds of losses which will occur with an array. The first is that the wires connecting the chips will run from the hot side, to the cold side. They will provide a thermal backpath, which reduces efficiency. To maximize efficiency, one uses a thin wire. The second loss comes from the fact that a lot of power is flowing across the wire. Resistive heating will occur. To maximize efficiency, one uses a thick wire. This is a classic engineering tradeoff: find the ideal wire thickness to minimize the losses. Using copper, the losses are on the order of 12% of Carnot. This makes the thermal connectors the largest single loss term.

28 Slide 28 Efficiency Calculation Thermal Backflow Losses from Separation These losses are geometry dependent To minimize separation losses, edge supports will be used, with no internal spacers. Thermal backpath is thereby minimized SiO 2 When heat flows from the hot side to the cold side, and it does so through active (hot) electrons, the device is efficient. Cool Chips are designed to only allow electron flow -- there is no direct thermal contact between the hot and cold sides. But when heat can flow without the electrons carrying it with them (as it does through simple conduction), the device loses efficiency. A solidstate converter which has no gap between the hot and cold side is like a dam with holes in it. Some of the water is used to turn the turbine. Some of it just goes through the holes. To maximize this advantage, the device should be built so as to have a long, thin, thermal pathway. Heat, in order to reach the other side, will need to travel the longest path. Efficiency is increased.

29 Slide 29 Efficiency Calculation Thermal Backflow Losses from Separation = ( T)λ A l A=cross-sectional area l = length Geometry and materials will determine the precise separation loss. These will be selected based on device temperature range, efficiency, cost, and other requirements. Effect on Carnot Efficiency Production devices will vary Prototype has a separation loss of <1.2 x 10-3 watts per degree Kelvin? T, or <1% This loss term can be adjusted, depending on device geometry, to have high losses, or low losses. The test machine used by Borealis has a long quartz tube as the thermal backpath, and the losses are very small -- less than 1% of Carnot. It is expected that production devices will have higher separation losses, but keeping these losses within reasonable bounds is straightforward.

30 Slide 30 Efficiency Calculation Total Practical Losses Given the assumptions used in these calculations, total practical losses are on the order of 15% In conclusion, assuming a 3 watt/cm 2 heat flux, the practical losses are on the order of 15% of the theoretical maximum. These are very acceptable losses, and compare quite favourably with other technologies. As the cooling density increases, the practical losses will decrease, since most of these losses occur as a result of the T across the diode. On the other hand, as the T increases (for high performance applications), the practical losses will increase.

31 Slide 31 Efficiency Calculation Overall Efficiency Combining Intrinsic and Practical loss terms, approximate efficiencies are 50-55% of maximum possible COP The result of these efficiency calculations show that Cool Chips are highly competitive with other technologies. Thermoelectrics are 5-8% efficient. If recent breakthroughs are confirmed, they may achieve 20-30% efficiency. Compressors are 40-50% efficient. This is a mature technology, with only incremental improvements in its future. Cool Chips will clearly be far more efficient than the competition.

32 Slide 32 Fabrication Cost Cool Chips are chip-based technologies, with precise, but simple construction. Non-exotic materials with moderate contamination tolerance No costly materials involved in processes Very small devices require small amounts of material Marginal cost of Cool Chips, in production, will be as low as pennies per watt capacity In addition to high efficiency, Cool Chips are expected to be very inexpensive to make. A number of factors come into play when estimating the cost of a product like a turbine or a compressor. The marginal costs (the cost of making one more unit on an already-present assembly line), are heavily dependent on the following factors: 1: Materials quantity. No device can cost less than its parts. And big, heavy machines like turbines and compressors have a lot of steel, copper and iron in them. This is an unavoidable cost. Cool Chips use very little in the way of raw materials -- at least an order of magnitude less than the competition. A single chip, capable of 100 watts of output, will be circular and 1 square cm in active area, and be only a few millimeters thick. 2: Material quality. As machines improve, the specifications for their components become ever more demanding. If the components must be of very high materials purity, a significant cost is added. This cost, unlike, say economies of scale, is not reduced easily. The price of 99% pure iron is far less than % pure iron. Cool Chips can use relatively impure materials. 3: Machining/assembly costs. The more welding, bonding, sealing, etc. which is required, the higher the costs as well. Cool Chips are extremely simple to manufacture -- much less complicated than an Intel 386 processor, for example. 4: Component costs. The more pieces that have to be put together, the more it will cost. Cool Chips have a very small component count, much less than competing technologies.

33 Slide 33 The Big Picture Cool Chips will be a high margin, high volume product which is: In high demand in a growth industry Superior to all existing and projected technologies Proprietary, allowing a 20 year head start Environmentally Friendly